Mixed

Introduction to the Design and Development of Introduction to the Design and Development of Mixed Signal Integrated Circuits Mixed Signal Integrated Circuits

Tutorial 2 Tutorial 2

Prashant BhadriPrashant BhadriRaghuram SrinivasanRaghuram Srinivasan

Sunday, August 7, 2005 Sunday, August 7, 2005 15:3015:30--18:30 pm18:30 pm

IEEE International 45IEEE International 45thth MidMid--West Symposium West Symposium on Circuits and Systems on Circuits and Systems

Cincinnati, OhioCincinnati, Ohio

Copyright InformationCopyright InformationThis presentation is an “Open Access” material and therefore

please credit the presenters if you reproduce any of this information

PresenterPresenter’’s Informations Information

EducationB.S. in Electronics and Communication M.S. in Electrical Engineering Post-Doctoral Fellow at the Doheny Eye Institute, Keck’s School of Medicine University of Southern California, Los Angeles

Research FocusEngineering Solutions in Medical DomainAnalog, Digital, Mixed Signal Circuit Design,Testing and AnalysisField Programmable Gate ArraysProduct Development of Medical Devices

Academic Achievements30 papers presented and published in journals, conferences, and magazines2 provisional patentsRecipient of Rindsberg FellowshipRecipient of SPIE Travel Award

Prashant R BhadriDoctoral Researcher

University of Cincinnati

EducationB.S. in Electrical EngineeringM.S. in Computer Engineering

Research FocusImproving Simulation Time using Multi-Threading in a Frequency Extended VHDL-AMSAnalog, Digital, Mixed signal Circuit Design,Testing and AnalysisFormal Verification Methods to Analog and Mixed-Signal Systems

Raghuram SrinivasanDoctoral Researcher


InformationInformation

Prashant R. Bhadri

Department of ECECS, College of

Engineering, University of Cincinnati, PO Box-210030,Cincinnati, Ohio - 45221

Fax – (513)556-7326

Email: [email protected]

Raghuram Srinivasan

Department of ECECS, College of

Engineering, University of Cincinnati,

PO Box-210030,Cincinnati, Ohio - 45221

Fax – (513)556-7326

Email: [email protected]

Copy of the material available on:

Distributed Processing Laboratory: www.ececs.uc.edu/~dpl

Dr. Fred R. Beyette Homepage: www.ececs.uc.edu/~beyette

Outline of the TutorialOutline of the TutorialMotivationMotivationOverview Overview Detailed Design ProcessDetailed Design ProcessSimulation with VHDLSimulation with VHDL--AMSAMSEvaluation ProcessEvaluation ProcessConclusionsConclusionsAcknowledgementsAcknowledgementsQuestion and Answers Question and Answers

MotivationMotivationMajor need for mixed-signal chips driven by consumer products

Cell phonesMusic playersDigital Cameras

As frequency increases, digital circuits become more analog Clock distribution (PLL’s, pulse shapers, oscillators)Pad design (buffers, protection circuits)Interconnect (become more like transmission lines)Logic cells (become more like RF and microwave circuits)

When Digital becomes Analog?When Digital becomes Analog?

Issues in MixedIssues in Mixed--Circuit DesignCircuit DesignAs feature size decreases, RF circuit issues become dominant in both digital and analog circuits

NoiseCoupling noiseComponent noisePower supply and ground noise

Circuit parametersImpedance mismatchesGain

Major need for analysis methods and tools

Status of MixedStatus of Mixed--Signal DesignSignal DesignCurrent technology supports mixed-signal circuits on a chip

Bi-CMOSCMOS extended with analog insulator layer

Design tools just coming onlineAnalog and Mixed-Signal (AMS) modeling and simulationAMS synthesis (still in research stage)

Comparison of CMOS, Bipolar and BiComparison of CMOS, Bipolar and Bi--CMOSCMOS

Reference: R.J. Baker, CMOS Circuit Design, Layout, and Simulation, Second Edition, John Wiley and Sons, 2005

Common Applications of BiCommon Applications of Bi--CMOSCMOS

Bi-CMOS circuits are used in places where devices with significant drive current can be used to significantly enhance system performanceMany microprocessor designs utilize BiCMOS circuits in their bus controllers, floating point processing unit and the processor core where speed is criticalCircuits where power consumption is a concern (ex. Cache Memory) are implemented in the less power hungry CMOS circuits



MM--S Design FlowS Design Flow

DESIGN

SPECIFICATION

VERIFICATION

FABRICATION

TESTING

Component FlowComponent FlowSpecifications

Functional Descriptions, Algorithms

Architecture

Circuit

Floorplan

Blocks

Abstraction

+

-

Functional Design

Physical Design

Reference: Ken Kundert, Henry Chang, Dan Jeffries, Gilles Lamant, Enrico Malavasi, Fred Sendig, "Design of Mixed-Signal Systems-on-a-Chip", IEEE Trans. on CAD of ICs and Systems, Vol.19, No. 12, pp. 1561-1571, December 2000.

System DomainSystem Domain

Hardware System Hardware System Design FlowDesign Flow

Iterative Design ProcessIterative Design Process

Integrated circuit design:Complex activity Well-defined process

The system is divided into functional blocks (subsystems) Defined first with respect to their interfaces between each other A series of design steps each follow modeling the results Simulation of the model assures the design meets the requirements

Reference: Prashant Bhadri, Raghuram Srinivasan, Prosenjit Mal, Fred Beyette Jr., Harold Carter, “Design and Analysis of Mixed Mode Integrated Circuits” IEEE Potentials Magazine, February 2005, pp: 6-11

MM--S Design vs. Digital DesignS Design vs. Digital Design

Components Components –– Analog/Digital Analog/Digital Design Input Design Input –– Behavioral/StructuralBehavioral/StructuralVerification Verification –– VHDL/Spice/VHDLVHDL/Spice/VHDL--AMSAMSSynthesis Synthesis –– Analog is time consumingAnalog is time consumingFabrication & Testing Fabrication & Testing –– Separate steps for Analog and Separate steps for Analog and Digital ComponentsDigital Components

Specifications Specifications

System Design System Design Circuit Design Circuit Design

Layout Design Layout Design

Verification Design Verification Design

Results Results

Courtesy: Dr. Harold Carter

Flow DescriptionFlow Description

Novel Issues in MNovel Issues in M--S DesignS Design

Specification Specification –– Too many decision parametersToo many decision parametersDesign Design –– Diverse fields of specializations requiredDiverse fields of specializations requiredVerification Verification –– Analysis of multiple domainsAnalysis of multiple domainsEvaluation Evaluation –– Statistical analysisStatistical analysisFabrication Fabrication –– SOC fabrication SOC fabrication

Outline of the TutorialOutline of the TutorialMotivationMotivationOverviewOverviewDetailed Design ProcessDetailed Design ProcessSimulation with VHDLSimulation with VHDL--AMSAMSEvaluation ProcessEvaluation ProcessConclusionsConclusionsAcknowledgementsAcknowledgementsQuestion and Answers Question and Answers

DefinitionsDefinitions

A set of requirements that need to be satisfiedA set of requirements that need to be satisfiedRequirements of a Requirements of a ““GoodGood”” Specification:Specification:

UnambiguousUnambiguousAvoid contradictionsAvoid contradictionsRealizable with current technology capabilitiesRealizable with current technology capabilities

Specification ParametersSpecification ParametersFunctional parameters Functional parameters -- ThroughputThroughputAnalog parameters Analog parameters –– Bandwidth, Gain, Threshold etc.Bandwidth, Gain, Threshold etc.Design parameters Design parameters –– Area, Power, etc.Area, Power, etc.Types of components availableTypes of components availableEnvironment Environment –– Temperature, Pressure etc.Temperature, Pressure etc.Industry Standards provides the base specificationIndustry Standards provides the base specification

Advantages of Clear SpecificationAdvantages of Clear SpecificationQuicker design cycle due to fewer errorsQuicker design cycle due to fewer errorsTesting of components from respective specifications:Testing of components from respective specifications:ex: Virtuoso ex: Virtuoso AptiviaAptivia SpecificationSpecification--driven environmentdriven environment

Driving Design Cycles Driving Design Cycles –– HDL Models are capable of:HDL Models are capable of:Being subjected to behavioral analysis (simulation)Being subjected to behavioral analysis (simulation)Layout generation (ASIC, FPGA)Layout generation (ASIC, FPGA)

Examples of Specification ToolsExamples of Specification Tools

HDL’s: ObjectiveVHDL, SystemVerilog, HDL Monitors, OpenVera, RosettaSoftware: SpecC, SystemC, JavaBehavioral Models: VHDL-AMS/ VHDL/ Matlab

Statecharts/AutomataStatecharts/Automata

Formal

Specification

Challenges in a MChallenges in a M--S EnvironmentS Environment

Increased design parameters, increases constraintsIncreased design parameters, increases constraintsMultiple levels/domains of specificationMultiple levels/domains of specificationConstant updates due to technology advancesConstant updates due to technology advances

System SpecificationSystem SpecificationIn a product development environment, the specification document presents the first set of guidelines for an initial design of the system that would solve a given problemSystem specifications contain explicit details of the design:

SizeSpeed PowerCost Functionality

Constraints on available resources need to be taken into account before developing these for the system and the specification in turn imposes constraints on the design processMost standard designs detailed data sheets are available to design engineers


System DesignSystem Design

Translation of the Translation of the ““SpecsSpecs”” into a microinto a micro--electronic circuitelectronic circuitBefore Beginning:Before Beginning:

Top Down / Bottom UpTop Down / Bottom UpLevel of AbstractionLevel of AbstractionType of Final Design Type of Final Design –– SOC/MS/Analog/DigitalSOC/MS/Analog/DigitalAvailability of Resources Availability of Resources

Example MExample M--S SystemS System

Reference: http://www.techonline.com/community/tech_topic/bluetooth/33005

MM--S Design ProcessS Design ProcessReview SpecificationReview SpecificationDesign Control CircuitryDesign Control CircuitryReplace blocks in design with circuit components Replace blocks in design with circuit components Check if IP/Parameterized models are availableCheck if IP/Parameterized models are availablePower/Layout/Area aware design Power/Layout/Area aware design

Characteristics of a Characteristics of a ““GoodGood”” DesignDesignTradeoff between analog and digital componentsTradeoff between analog and digital componentsReduced layout complexityReduced layout complexityPostPost--fab testabilityfab testabilityFlexibility in design modifications: Flexibility in design modifications:

CorrectionsCorrectionsPosterityPosterity

Challenges in MChallenges in M--S DesignS Design

Full custom design vs. IP reuseFull custom design vs. IP reuseMultiple domains make controller design more complexMultiple domains make controller design more complexOptimization choices much fewerOptimization choices much fewerStricter Design Rules Stricter Design Rules

System DesignSystem Design

Use of Hardware Description Languages (HDL’s) for describing a system in the Register Transfer Level (also called RTL) Higher levels of abstraction (e.g., behavioral level) are employed for larger designs; lower levels (e.g., gate level, transistor level) for smaller designs This shift from purely digital to Mixed-Signal (MS) systems has risen due to the high values of operating frequencies in communication circuits and shrinking feature sizesDesign productivity is one of the major issues of concern in VLSI systems With the size of the chip decreasing exponentially, the complexity of the gates has been increasing exponentially but design methodologies have not kept up with the circuit complexity


Design HierarchyDesign Hierarchy

Bread Board Bread Board

Printed Circuit Board Printed Circuit Board

SMTSMT

ASIC ASIC

Block Level Implementation Block Level Implementation

Lakshminarayanan Ramasamy, “ ASIC System Development of MEMS Bio-Chip Analyzer with Calibration, Signal Capture and Display Circuit”, Masters Thesis, March 2005

PCB & SMT Implementation PCB & SMT Implementation

Lakshminarayanan Ramasamy, “ ASIC System Development of MEMS Bio-Chip Analyzer with Calibration, Signal Capture and Display Circuit”, Masters Thesis, March 2005

MM--S Design S Design

Photocurrent is generated that is amplified and processed

Conversion of the signal from analog to digital with standard CMOS digital circuitry or use the analog signal directly to the next stage of the circuitry

Various implementations of photoreceiver circuits is presented where the front end is an optical detector followed by amplifier and processing.

Photoreceiver Flow Diagram* Photoreceiver Flow Diagram*

*Prashant Bhadri et.al.,“Design and implementation of CMOS photoreceivers”, Proc. SPIE: Optical Information Systems II, October 2004, Vol. 5557, p. 173-184

Optical Detector ConfigurationsOptical Detector Configurations

Response to optical illumination in the visible to IR wavelength range Photodetectors fabricated through the MOSIS foundry serviceTypes of photodetectors are:

P-diffusion to N-well N-well to P-substrateCombination Bipolar Junction Phototransistor

CMOS Photodetector* CMOS Photodetector*

Reference: Prashant Bhadri et. al, “Implementation of CMOS photodetectors in optoelectronic circuits” Proc. IEEE: Lasers and Electro-Optics Society, The 15th Annual Meeting of the IEEE, November 2002, Vol. 2, p. 683 - 684

ASIC CircuitASIC Circuit

User threshold programmable photoreceiver that monolithically integrates at chip level with the Multi Technology-FPGAUser programmed with the receiver threshold set to one of eight sensitivity levels The output from the photoreceiver cell can be stored in SRAM cellsBy decoding three programming bits (IN0, IN1, IN2) 8 different threshold levels can be established and hence the user can program the sensitivity of the receiver

*Prashant Bhadri et.al.,“Design and implementation of CMOS photoreceivers”, Proc. SPIE: Optical Information Systems II, October 2004, Vol. 5557, p. 173-184

N-well/p-substrate photo-diode

Guard Rings

Transimpedance Amp. Differential Amp.

Threshold generation

Metal Shielding

Layout Level Layout Level

Reference: Prosenjit Mal et.al.,“Development of a Multi-technology FPGA: A Reconfigurable Architecture for Photonic Information Processing” Proc. SPIE: Emerging Optoelectronic Applications, June 2004, Vol. 5363, p. 27-38

System Layout System Layout


SummarySummary

Commercial FPGA devices are electronic Need for incorporation of nontraditional multi technologies into CMOS VLSI systemsProposed a novel architecture that extends the flexibility, rapid prototyping and reusability benefits associated with conventional electronics into the multi-technology domain

Top Level FPGA Design Top Level FPGA Design

MTB Floor Plan MTB Floor Plan

MTFPGA Chip Layout MTFPGA Chip Layout


Circuit DesignCircuit DesignThe circuits are designed as cell libraries and then simulated using one of many available circuit simulators These designs are close to the required specification values as a general idea is obtained during this step The challenges are in the form of shrinking chip design requirements, pushing the power and performance boundaries and the need to integrate most of the applicationsDue to the gradual evolution of the semiconductor process technology, new types of circuit architecture are being implementedAs many of the innovative applications assume very low-cost implementations of circuit building blocks, low-cost technology such as CMOS


Gate Layout Gate Layout Layout can be very time consuming

Design gates to fit together nicelyBuild a library of standard cells

Standard cell design methodologyVDD and GND should abut (standard height)Adjacent gates should satisfy design rulesNMOS at bottom and PMOS at topAll gates include well and substrate contacts

Other IssuesNoise Power Delay

Chip NoiseChip NoiseCircuit noise includes all the disturbances by the circuit’s topologyInterconnect noise includes noise coming from capacitive or inductive coupling between interconnectsPower supply noise, which refers to deviations of the supply and ground voltages from their nominal valuesSubstrate noise in mixed-signal integrated circuits:

For Example:The charge injected in the substrate by the logic gates during the transitions may interfere severely with the operation of sensitive analog circuits

Reference: Bartolo’s Thesis, Chapter 1

Shot Noise Shot Noise In a transistor the major contributor to noise is called shot noise.The formula for shot noise in a diode is given as:

Reference: Lowen, S.B et.al,“ Power-law shot noise”, Information Theory, IEEE Transactions on Volume 36, Issue 6, Nov. 1990 Page(s):1302 - 1318

Thermal Noise Thermal Noise The noise generated by the agitation and interaction of electrons is called thermal noise. The internal kinetic energy of a particle can be expressed through its temperature.The kinetic energy of a body is zero at a temperature of absolute zero. The noise generated by a resistor, for example, is proportional to its absolute temperature as well as the bandwidth over which the noise is to be measured.

Reference: Bing Wang,et.al; “MOSFET thermal noise modeling for analog integrated circuits”, Solid-State Circuits, IEEE Journal of Volume 29, Issue 7, July 1994 Page(s):833 - 835 ue 6, Nov. 1990 Page(s):1302 - 1318

Problem Problem Solution Solution

Charge InjectionCharge Injection

Reference: http://kabuki.eecs.berkeley.edu/~gchien/thesis/Masters/appB/appendixB.pdf

When the switch is on, the voltage across the sampling capacitor tracks the time-varying input signal within the bandwidth. Some charges are present in the MOS channel, this is a result of forming a conducting channel under the MOS gate. When the switch is turned off, charges either flow to the input source or to the sampling capacitor and create a small voltage which . is a function of several parameters which include input impedance, source impedance, clock falling edge.

Clock FeedClock Feed--throughthrough

When the clock voltage on the gate switches between high and low, this voltage.drop is coupled into the signal via the capacitor divider.The clock feed-through can be corrected to the first order by using a differential signal path. As long as the error is present on both signal inputs and the same magnitude, it can be cancelled by taking the input differentially. This technique, once again, depends on the absolute matching of transistors.

Reference: http://kabuki.eecs.berkeley.edu/~gchien/thesis/Masters/appB/appendixB.pdf

Ground Bounce Ground Bounce

Reference: http://klabs.org/richcontent/Tutorial/new_modules/ground_bounce.pdf

For significant flows the voltage drop across this inductor is given by:VB = L dI/dt

For a 50 mA current change over 3 ns in a 3mm x 1 cm line VB = 50 mV which is enough “noise” to disrupt digital signal quality.

LatchLatch--upup

This spiking problem leads to a condition called latch-upFalling edge spike goes through C2 turning on transistor Q2

Current flow through Q2 causes voltage drop across RW1 and RW2 turning on transistor Q1

Current flow through Q1 causes voltage drop across RS1 and RS2 further turning on Q2

Rising edge spike has same effect starting with pass through C1


Solutions to LatchSolutions to Latch--upup

Slow the rise/fall time to reduce the size of the spikesReduce the size of drain region to reduce C1 and C2.Reduce RW1 and RS2 by placing substrate and well contacts close to the transistor drainsPlace n+ and p+ regions around critical circuits. These features (called guard rings) are effective but take space and limit the ability to use poly as an interconnect layer


Layout Design Layout Design It is very important for a layout designer to understand the bounds of laying out a circuit as it depends on the type of the circuit designed This step characterizes a chip as a whole where a circuit is laid out, then extracted and its functionality checkedDuring the extraction process a large number of parasitic including capacitances, inductances and resistances is obtained that lead to more complications in circuit design Therefore one of the fundamental limitations of high speed design is to have a strong understanding of layout extractionMost of the layouts are implemented using software tools like Magic, Cadence, and Tanner Tools etc


DefinitionsDefinitions

Process of virtually simulating the design and checking Process of virtually simulating the design and checking conformance with the specsconformance with the specsAdvantages of Verification:Advantages of Verification:

Early error detectionEarly error detectionFine tuning the design based on verification outputFine tuning the design based on verification outputReliable time metrics can be obtainedReliable time metrics can be obtained

Verification in a MVerification in a M--S EnvironmentS EnvironmentMultiple domains, multiple abstraction levelsSimulation cycle handles notion of time in discrete and continuous valuesSeparate simulation engines, working with the same set of signalsOutput Analysis in Time/Frequency

Spice Circuit SimulatorSpice Circuit SimulatorFirst IC evaluation softwareHas inbuilt components models for circuit elementsAllows different levels of models for varying accuracy requirementsProvides accurate measurement for power and timingSupports only structural models

Comparison of Spice and VHDLComparison of Spice and VHDL--AMSAMS

Behavioral ModelsBehavioral Models

Power/Area AnalysisPower/Area Analysis

Equation Set AnalysisEquation Set Analysis

Mixed Time ModelingMixed Time Modeling

Digital ComponentsDigital Components

Multiple Analysis ModesMultiple Analysis Modes

SpiceSpiceVHDLVHDL--AMSAMSParameterParameter

Evolution of MEvolution of M--S S HDLHDL’’ssMAST MAST –– Developed during the early 80Developed during the early 80’’s, required s, required expert usersexpert usersVHDLVHDL--AMS AMS –– First version of the LRM in 1993, First version of the LRM in 1993, shifted burden from user to simulatorshifted burden from user to simulatorVerilogVerilog--AMS AMS –– Extension of Verilog Extension of Verilog

Highlights of VHDLHighlights of VHDL--AMS AMS

Inclusion of continuous valued Inclusion of continuous valued ““quantitiesquantities””Allows design entry at the behavioral or structural levelsAllows design entry at the behavioral or structural levelsNo concept of components like Spice, only equation setsNo concept of components like Spice, only equation setsAnalog solution based on numerical integrationAnalog solution based on numerical integration

VHDLVHDL--AMS Simulator DesignAMS Simulator Design

VHDL-AMS

SPICE VHDL

WARPED Kernel

SIMULATOR KERNEL

DAESOLVER

TyVISDIGITAL KERNELFES

LEXICALANALZER

LIBRARIES

Challenges in MChallenges in M--S VerificationS Verification

Convergence Convergence –– not always a guaranteenot always a guaranteeLarge variations in time stepsLarge variations in time stepsParasitic capacitances Parasitic capacitances –– model order and E.M effectsmodel order and E.M effects““Ripple EffectRipple Effect””: Whole design needs to be verified during : Whole design needs to be verified during design modificationsdesign modificationsHigh Frequency Analysis support still primitiveHigh Frequency Analysis support still primitive

Verification Verification Verification is the process by which the correctness of the design and implementation details is compared to the original specifications Hardware description languages model complex systems A/D components SOC’s have given rise to Analog and Mixed Signal (AMS) tools These tools combine methods from traditional circuit simulators like SPICE and digital simulation kernels like VHDL to deal with both of these components Any unsatisfactory or incorrect parameters can be detected and the design can be modified to correct the errors or approach certain tolerance levels


Electronic Circuit Design ProcessElectronic Circuit Design Process

A CMOS foundry takes a wafer of silicon and processes it into an array of circuits (called die).

The wafer will also contain test structures, process monitoring plugs and alignment reticules.

The individual die are diced from the wafer and packaged into a variety of electronic devices.


MOSIS: The MOS Integration ServiceMOSIS: The MOS Integration Service

The MOS Integration Service (MOSIS) provides a low cost method for implementing CMOS designs.The service works by purchasing fabrication runs from commercial CMOS foundries and distributing the cost over a larger number of circuit designers.For more information visit the MOSIS web page at www.mosis.org

MOSIS WEBSITE MOSIS WEBSITE

OxidationOxidation LithographyLithography Implantation Implantation DiffusionDiffusion

AnnealingAnnealingMetal Metal DepositionDeposition

Wafer CleaningWafer Cleaning EpitaxialEpitaxialGrowth Growth

Metal Layer?Metal Layer?

Fabricated Fabricated ChipChip

NONO

YESYES

Fabrication Process Fabrication Process DescriptionDescription


Fabrication Fabrication The chip is fabricated (generally on lightly doped p-type or n-type silicon wafer) using specific fabrication technology (i.e. TSMC 0.35µm or IBM 0.13µm process etc.) that has been specified at circuit design level or before A series of photolithographic mask layers are designed depending on type process and number of steps involvedSubsequently, the whole design runs through several fabrication steps that involve oxidation, photo-lithography (developing photo-resist layers, exposing to UV and etching), implantation of p+ or n+ source/drain region, metallization for forming contacts and developing field oxide for isolation of transistorsFabrication processes are characterized by minimum feature size in a transistor, gate oxide thickness, no. of poly and metal layers available for interconnections, sheet resistances of different wells, doped regions, and metal and poly-silicon


Block Diagram of the Photoreceiver

Testing Overview Testing Overview

Photoreceiver Circuit Photoreceiver Layout

Photoreceiver Testing

Logic Analyzer Testing

Courtesy: Dr. Prosenjit Mal

LD Drive

Cubicle SplitterOptical Power Meter

Fiber Coupler

Optical Fiber Detector/Receiver

Laser Diode

Multi-meter Power SourceComputer(LabVIEWProgram)

P1 P3P2

P4

Example of Mixed Signal {Optical} TestingExample of Mixed Signal {Optical} Testing


ExampleExample

Optical input power changes from 0 –1mWMost sensitive settings (000) switches around 450µWLeast sensitive settings (111) switches around 675µWUser can fine tune the range with Vadj

Vadj can be changed 0 – 3.3V corresponds to input range shift of 90µW

General MGeneral M--S Tests S Tests Continuity Tests:

Detecting on Chip ESD Validating Connectivity between Device and TesterFault Elimination Breakdown Test:

Current LimitVoltage Limit

Power Supply Test: IDDQMetal Errors – shorted tracesImplant/Diffusion errors – shorted substrateFaulty ESD ClampsOpen/Floating WellsOpen/Floating Digital gate input

Reference: Prof. Forrest Brewer www. bears.ece.ucsb.edu/class/ece224b/Lecture3mixedtest.ppt

Impedance MeasurementZ=V/I (Usually Z=DV/DI)

Force V, measure I (High Impedance)Force I, Measure V (Low Impedance)

Defined Testing LevelsReduce possibility of DUT damageIncrease accuracy of measurement

Power Analysis Testing over Operation Range

Voltage/Current/FreqMemory devicesProcessors

General MGeneral M--S Tests (Contd.) S Tests (Contd.)

Reference: Prof. Forrest Brewer www. bears.ece.ucsb.edu/class/ece224b/Lecture3mixedtest.ppt

Testing Testing To facilitate the testing process, a number of test structures are evenly distributed all over the chipTest station equipment includes pattern generator, logic analyzer, probe station, semi-conductor parameter analyzer, oscilloscope etcWhile pattern generator and logic analyzer are used for digital test pattern generations and measurements, other equipment facilitate probing of device parameters and analog data measurementsThe chip is run on through a number of test vector sets which are generated from computer using various test algorithms In conclusion, the circuit is verified for its functionalities and specifications. Also tests are run for a period of time to check any variation of performance



VHDLVHDL--AMS OverviewAMS OverviewCapabilitiesLanguage OverviewSolution CycleSolvabilityDiscontinuities Predefined AttributesConclusionReferences

Half Wave RectifierHalf Wave RectifierBEGIN -- behavior

--diode equationsif( vDiode >= (-1.0 * Vt)) USE

eqn1_1: iDiode == saturation_current * (exp(vDiode/Vt) - 1.0);

ELSIF ((vDiode < (-3.0 * Vt)) AND (vDiode > -BV)) use

eqn1_2: iDiode == neg_sat;ELSE

eqn1_3: iDiode == neg_sat * (exp(-(BV + vDiode)/Vt) - 1.0 +

saturation_current);END USE ;

--resistor equationeqn2: v2 == 100.0 * i2;

--voltage source equationeqn4: vs == 5.0 * sin(2.0 * 3.14 *

100000.0 *

real(time'pos(now)) * 1.0e-15 );

END behavior ;

Bouncing Ball ModelBouncing Ball ModelENTITY bouncing_ball IS END ENTITY bouncing_ball; ARCHITECTURE simple OF bouncing_ball IS QUANTITY v: real; QUANTITY s: real; CONSTANT G: real := 9.81; CONSTANT Air_Res: real := 0.1; BEGIN -- specify initial

conditions using the break statement

b1:BREAK v => 0.0, s => 30.0;b2:BREAK v => -0.7*v WHEN

NOT(s'above(0.0)); velocity: v == s'dot ;

acceleration: v'dot == -G; END ARCHITECTURE simple;

∑∑--∆∆ ModulatorModulator

BEGIN

comp1: comprport map(clk_enable , analog_vin, dac_out);

and1: andCompport map(clk_in, clk_enable, enable_count);

count1: counterport map(clear, enable_count, counter_op);

da_conv: dacport map(counter_op, dac_out, electrical'reference);

MM--S SimulationS SimulationMixed representations of time, synchronizationMixed representations of time, synchronizationMultiple physical domainsMultiple physical domainsConservative and nonConservative and non--conservative modelsconservative modelsSolvability, ConvergenceSolvability, Convergence

VHDLVHDL--AMS AMS –– VHDL 1076.1VHDL 1076.1--19991999Superset of VHDL 1076 Superset of VHDL 1076 Analysis types Analysis types –– transient, noise, small signal frequencytransient, noise, small signal frequencySolve Differential Algebraic Equations (DAE)Solve Differential Algebraic Equations (DAE)Tolerances, discontinuity handlingTolerances, discontinuity handling

Language OverviewLanguage OverviewNature definitionsNature definitionsTerminals and QuantitiesTerminals and QuantitiesQuantity Attributes Quantity Attributes –– Implicit quantities/signalsImplicit quantities/signalsMixedMixed--signal interfacessignal interfacesMixedMixed--signal descriptions of behaviorsignal descriptions of behavior

QuantitiesQuantities

Represents an unknown in the set of Represents an unknown in the set of DAEsDAEsContinuous time waveformContinuous time waveformPrePre--defined attributes create implicit quantitiesdefined attributes create implicit quantities

. . .

ARCHITECTURE sinebehavior OF sineSource IS

QUANTITY Irsine THROUGH ta2 TO tb2;

QUANTITY resistor: REAL;

. . .

Types of QuantitiesTypes of QuantitiesENTITY example ISPORT (

QUANTITY interface_q: REAL;TERMINAL elec_p, elec_n: ELECTRICAL);

END ENTITY example;

ARCHITECTURE simple OF example ISQUANTITY v1, v2 ACROSS i1, i2, i3 THROUGH

elec_p TO elec_n;QUANTITY free_q: REAL;. . .

PORT QUANTITY

BRANCH QUANTITY

FREE QUANTITY

TerminalTerminal

Represents a node in an electrical circuitRepresents a node in an electrical circuitSupport for structural composition with conservative semanticsSupport for structural composition with conservative semanticsBelongs to a NATUREBelongs to a NATURE

ENTITY diode IS

. . .

PORT ( TERMINAL anode, cathode: ELECTRICAL);

END ENTITY diode;

Electrical Systems EnvironmentElectrical Systems EnvironmentPACKAGE electrical_system ISSUBTYPE voltage IS REAL TOLERANCE “default_voltage”;SUBTYPE current IS REAL TOLERANCE “default_current”;SUBTYPE charge IS REAL TOLERANCE “default_charge”;NATURE electrical IS

voltage ACROSS -- across typecurrent THROUGH -- through typeelectrical_ref REFERENCE; -- reference type

ALIAS ground IS electrical_reference;NATURE electrical_vector IS

ARRAY ( NATURAL RANGE <>) OF ELECTRICAL;END PACKAGE electrical_system;

Nature DefinitionNature Definition

Electrical nature in package electrical systemElectrical nature in package electrical systemRepresents a physical discipline/energy domainRepresents a physical discipline/energy domainEach node is of a certain natureEach node is of a certain natureDefines the types of quantities incident on the terminalDefines the types of quantities incident on the terminalSubnatureSubnature declaration declaration –– different tolerance levelsdifferent tolerance levelsOther nature definitions: thermal, translational, rotational, Other nature definitions: thermal, translational, rotational, fluidic, magnetic, etc.. fluidic, magnetic, etc..

Relation between ElementsRelation between Elements

NatureNature TerminalTerminal

QuantityQuantity

Type Type InformationInformation

Structure Structure InformationInformation

Simultaneous Statement(1)Simultaneous Statement(1)

Expresses relationship between quantities Expresses relationship between quantities –– used by the analog solverused by the analog solverMay appear anywhere a concurrent statement may appearMay appear anywhere a concurrent statement may appear

ARCHITECTURE simple OF bouncing_ball IS. . .BEGIN. . .velocity: v == s'dot ; acceleration: v'dot == -G;. . .

Simultaneous Statements(2)Simultaneous Statements(2)LHS and RHS LHS and RHS –– Floating point typeFloating point typeOne quantity must appear in each simultaneous statementOne quantity must appear in each simultaneous statementTolerance group determined by the quantities Tolerance group determined by the quantities Other Forms of Simultaneous StatementsOther Forms of Simultaneous Statements

Simultaneous IF statementSimultaneous IF statementSimultaneous CASE statementSimultaneous CASE statementSimultaneous procedural statement Simultaneous procedural statement –– functions functions

DAE Solvers and ToleranceDAE Solvers and Tolerance

DAE – Differential Algebraic EquationsSolver – Uses numerical integration to reduce DAE’s to linear/non-linear equationsTolerance – Accept all solutions within a certain amount of varianceNecessary to adjust for accuracy of numerical methods

Simulation CycleSimulation Cycle

Analysis

Elaboration

Simulation

Syntax, Semantics

Flatten out processes & signals

Digital/Analog Solver

Sierra Sierra –– VHDLVHDL--AMS SimulatorAMS Simulator

VHDL-AMS Intermediate RepresentationC++

SimulationOperationGraphical

Operation

SCRAMSCRAM

TyVISTyVIS/SIERRA/SIERRA

PLOTTERPLOTTER

Analog/DAE SolverAnalog/DAE Solver

SEAMS: Simulation Environment for VHDL-AMS – Frey et al., 1998 Winter Simulation Conference

SolvabilitySolvability

General Solvability General Solvability -- # of equations equals # of unknown # of equations equals # of unknown quantitiesquantitiesFor VHDLFor VHDL--AMS:AMS:

#(Equations) = #(through quantities) + #(free #(Equations) = #(through quantities) + #(free quantities) + #(interface quantities of mode OUT)quantities) + #(interface quantities of mode OUT)Each scalar simultaneous statement creates one Each scalar simultaneous statement creates one equationequation

Sample Solvability ProblemSample Solvability Problem

ENTITY battery IS

PORT ( TERMINAL plus, minus:

electrical );

END ENTITY battery;

ARCHITECTURE simple OF battery IS

CONSTANT v_nominal: REAL := 9.0;

QUANTITY v ACROSS plus TO minus;

BEGIN

v = = v_nominal;

END ARCHITECTURE simple;

ENTITY battery IS

PORT ( TERMINAL plus, minus:

electrical );

END ENTITY battery;

ARCHITECTURE simple OF battery IS

CONSTANT v_nominal: REAL := 9.0;

QUANTITY v ACROSS i THROUGH plus TO minus;

BEGIN

v = = v_nominal;

END ARCHITECTURE simple;

Solvability Solvability –– Simultaneous IF StatementSimultaneous IF StatementENTITY sfgAmp IS

GENERIC ( gain: REAL := REAL’HIGH);PORT (QUANTITY input: IN REAL;

QUANTITY output: OUT REAL);END ENTITY sfgAmp;

ARCHITECTURE ideal OF sfgAmp ISBEGIN

IF gain /= REAL’HIGH USEoutput = = gain * input;

ELSE input = = 0.0;

END USE;END ARCHITECTURE ideal;

Same # in each USE clause

DiscontinuitiesDiscontinuities

BEGIN -- specify initial b1:BREAK v => 0.0, s => 30.0;b2:BREAK v => -0.7*v

WHEN NOT(s'above(0.0)); velocity: v == s'dot ; acceleration: v'dot == -G; END ARCHITECTURE simple;

BREAK !

Break StatementBreak Statement

Prompts analog solver to reset its statePrompts analog solver to reset its stateCoincides with a digital eventCoincides with a digital eventExplicitly say which event Explicitly say which event –– to improve simulation speedto improve simulation speedIs also employed to specify initial conditionsIs also employed to specify initial conditionsA model not having a BREAK at a discontinuity is A model not having a BREAK at a discontinuity is erroneous!erroneous!

Predefined AttributesPredefined AttributesImplicit signals/quantities created:

Quantity Attributes

Q’above(E), Q’dot, Q’integ, Q’slew(n1,n2)Frequency domain: Q’ztf( num, den, t, initial_delay), Q’ltf( num, den)

Signal AttributesS’ramp( n1, n2), S’slew( n1, n2)

SummarySummaryUse VHDL-AMS for your M-S circuits!Some Sources:www.ececs.uc.edu/~dpl : University of Cincinnatiwww.syssim.ecs.soton.ac.uk: Southampton, UKwww.dolphin.fr: Dolphin Systems - Smashwww.mentor.com: Mentor Graphics – Advance MS

ReferencesReferencesThe System Designer's Guide to VHDL-AMS – Ashenden et al.Modeling Semicondutor Devices using the VHDL-AMS Language – KasulaSrinivas, MS Thesis, University of Cincinnati, 1998.Introduction to the VHDL-AMS Language – Christen et al., Tutorial Presented at DAC, 1999 VHDL 1076.1 LRM – IEEE Press, 2003


Performance Evaluation using RPerformance Evaluation using R--Software Software

Introduction Introduction

‘‘RR’’ statistical software was initially introduced by Ross statistical software was initially introduced by Ross IhakaIhaka and and Robert Gentleman at Robert Gentleman at Department of Statistics of University of Department of Statistics of University of Auckland, New ZealandAuckland, New Zealand during 1990sduring 1990sSince 1997: international Since 1997: international ““RR--corecore”” team of 15 people collaborated in an team of 15 people collaborated in an effort to make it an open sourceeffort to make it an open source

R is a language and environment for statistical computing and grR is a language and environment for statistical computing and graphics.aphics.

R provides a wide variety of statistical (linear and nonlinear R provides a wide variety of statistical (linear and nonlinear modellingmodelling, , classical statistical tests, timeclassical statistical tests, time--series analysis, classification, clustering, series analysis, classification, clustering, ...) and graphical techniques, and is highly extensible...) and graphical techniques, and is highly extensible..

Reference: 1. Huang Chen - www.math.ntu.edu.tw/~hchen/ Prediction/notes/R-programming.ppt2. The R Project for Statistical Computing - http://www.r-project.org/

Highlights of R Highlights of R R is a language and environment for data manipulation, calculatiR is a language and environment for data manipulation, calculation on and graphical display:and graphical display:--

R is similar to the awardR is similar to the award--winning S system, which was developed winning S system, which was developed at Bell Laboratories by John Chambers et al.at Bell Laboratories by John Chambers et al.a large, coherent, integrated collection of intermediate tools fa large, coherent, integrated collection of intermediate tools for or interactive data analysis,interactive data analysis,graphical facilities for data analysis and display either directgraphical facilities for data analysis and display either directly at ly at the computer or on hardcopythe computer or on hardcopya well developed programming language which includes a well developed programming language which includes conditionals, loops, user defined recursive functions and input conditionals, loops, user defined recursive functions and input and output facilities. and output facilities.


The core of R is an interpreted computer language:The core of R is an interpreted computer language:--It allows branching and looping as well as modular programming It allows branching and looping as well as modular programming using functions. using functions. Most of the userMost of the user--visible functions in R are written in R, calling visible functions in R are written in R, calling upon a smaller set of internal primitives. upon a smaller set of internal primitives. It is possible for the user to interface to procedures written iIt is possible for the user to interface to procedures written in C, n C, C++ or FORTRAN languages for efficiency, and also to write C++ or FORTRAN languages for efficiency, and also to write additional primitivesadditional primitives


What R Does & Does Not ?What R Does & Does Not ?

Data handling and storageMatrix algebraHash tables and regular expressionsHigh-level data analytic and statistical functionsGraphicsProgramming language: loops, branching, subroutines

Not a database, but connects to DBMSsNo graphical user interfaces, but connects to Java, TclTkLanguage interpreter can be very slow, but allows to call own C/C++ code No spreadsheet view of data, but connects to Excel/MsOfficeNo professional / commercial support


Data Analysis and PresentationData Analysis and PresentationThe R distribution contains functionality for large number of The R distribution contains functionality for large number of statistical procedures. statistical procedures.

Linear and generalized linear modelsLinear and generalized linear modelsNonlinear regression modelsNonlinear regression modelsTime series analysisTime series analysisClassical parametric and nonparametric testsClassical parametric and nonparametric testsClustering Clustering SmoothingSmoothing

Large set of functions which provide a flexible graphical Large set of functions which provide a flexible graphical environment for creating various kinds of data presentations.environment for creating various kinds of data presentations.


ReferencesReferences““The New S Language: A Programming Environment for DataThe New S Language: A Programming Environment for DataAnalysis and GraphicsAnalysis and Graphics”” by Richard A. Becker, John M. Chambers by Richard A. Becker, John M. Chambers and Allan R. and Allan R. WilksWilks (the (the ““Blue BookBlue Book””) . ) .

““Statistical Models in SStatistical Models in S”” edited by John M. Chambers and Trevor J. edited by John M. Chambers and Trevor J. HastieHastie (the (the ““White BookWhite Book””))

Internet site Internet site (via (via http://cran.rhttp://cran.r--project.orgproject.org).).


SYSTEMSYSTEM

Factors

SystemInputs

SystemOutputs

Responses

WHAT IS A SYSTEM ?WHAT IS A SYSTEM ?


Experimental ResearchExperimental ResearchDefineSystemDefineDefineSystemSystem

IdentifyFactors

and Levels

IdentifyIdentifyFactorsFactors

and Levelsand Levels

IdentifyResponse(s)

IdentifyIdentifyResponse(s)Response(s)

Define system outputs firstThen define system inputsFinally, define behavior (i.e., transfer function)

Identify system parameters that vary (many)Reduce parameters to important factors (few)Identify values (i.e., levels) for each factor

Identify time or space effects of interest

DesignExperiments

DesignDesignExperimentsExperiments Identify factor-level experiments


Create and Execute System; Analyze DataCreate and Execute System; Analyze Data

DefineWorkloadDefineDefine

WorkloadWorkload

CreateSystemCreateCreateSystemSystem

ExecuteSystem

ExecuteExecuteSystemSystem

Workloads are inputs that are applied to systemWorkload can be a factor (but often isn't)

Create system so it can be executedReal prototypeSimulation modelEmpirical equations

Execute system for each factor-level bindingCollect and archive response data

Analyze & DisplayData

Analyze & DisplayAnalyze & DisplayDataData

Analyze data according to experiment designEvaluate raw and analyzed data for errorsDisplay raw and analyzed data to draw conclusions


ExamplesExamplesANALOG SIMULATIONWhich of three solvers is best?Which of three solvers is best?What is the system?What is the system?ResponsesResponses

Fastest simulation timeFastest simulation timeMost accurate resultMost accurate resultMost robust to types of circuits Most robust to types of circuits being simulatedbeing simulated

FactorsFactorsSolverSolverType of circuit modelType of circuit modelMatrix data structureMatrix data structure

EPITAXIAL GROWTHNew method using nonNew method using non--linear temp profilelinear temp profileWhat is the system?What is the system?ResponsesResponses

Total timeTotal timeQuality of layerQuality of layerTotal energy requiredTotal energy requiredMaximum layer Maximum layer thicknessthickness

FactorsFactorsTemperature profileTemperature profileOxygen densityOxygen densityInitial temperatureInitial temperatureAmbient temperatureAmbient temperature


Generic Model for Network Protocol Generic Model for Network Protocol

System: wireless network with new protocol Workload:

10 messages applied at single sourceEach message identical configuration

Experiment outputRoundtrip latency per message (ms)

LatencyLatency2222232319191818151520202626171719191717

Data file “latency.dat”


SummaryLatency

Min. :15.00 1st Qu.:17.25 Median :19.00 Mean :19.60 3rd Qu.:21.50 Max. :26.00

Box Plot Box Plot Scatter Plot Scatter Plot

Mean: 19.6 msVariance: 10.71 ms2

Std Dev: 3.27 ms

Data Distribution Data Distribution


Verify Model PreconditionsVerify Model PreconditionsCheck randomness

Use plot of residuals around meanResiduals appear random

Check normal distributionUse quantile-quantile plotPattern adheres consistently along ideal Q-Q line


Confidence IntervalsConfidence Intervals

Sample mean vs Population mean

CI: > 30 samples

CI: < 30 samples

Reference: Raj Jain, “The Art of Computer Systems Performance Analysis,” Wiley, 1991.Courtesy: Dr. Harold Carter

TT-- Test AnalysisTest Analysist.testt.test (dataset1,conf.level = 0.99)(dataset1,conf.level = 0.99)One Sample tOne Sample t--testtestdata: dataset1 data: dataset1 t = 18.9382, t = 18.9382, dfdf = 9, p= 9, p--value = 1.468evalue = 1.468e--0808alternative hypothesis: true mean is not alternative hypothesis: true mean is not equal to 0 equal to 0 99 percent confidence interval:99 percent confidence interval:16.2366 22.9634 16.2366 22.9634 sample estimates:sample estimates:mean of x mean of x

19.6 19.6

t.testt.test (dataset1,conf.level = 0.95)(dataset1,conf.level = 0.95)One Sample tOne Sample t--testtest

data: dataset1 data: dataset1 t = 18.9382, t = 18.9382, dfdf = 9, p= 9, p--value = 1.468evalue = 1.468e--0808alternative hypothesis: true mean is not alternative hypothesis: true mean is not equal to 0 equal to 0 95 percent confidence interval:95 percent confidence interval:17.25879 21.94121 17.25879 21.94121 sample estimates:sample estimates:mean of x mean of x

19.6 19.6


Scatter and Line PlotsScatter and Line Plots

Depth Resistance1 1.6890152 4.4867223 7.9152094 6.3623885 11.8307396 12.3291047 14.0113968 17.6000949 19.02214610 21.513802

Regression PlotRegression Plot Residual Plot Residual Plot

Normally Distributed ErrorNormally Distributed Error

Linear Regression StatisticsLinear Regression Statisticsmodel = lm(Resistance ~ Depth)summary(model)

Residuals:Min 1Q Median 3Q Max

-2.11330 -0.40679 0.05759 0.51211 1.57310

Coefficients:Estimate Std. Error t value Pr(>|t|)

(Intercept) -0.05863 0.76366 -0.077 0.94Depth 2.13358 0.12308 17.336 1.25e-07 ***---Signif. codes: 0 `***' 0.001 `**' 0.01 `*' 0.05 `.' 0.1 ` ' 1

Residual standard error: 1.118 on 8 degrees of freedomMultiple R-Squared: 0.9741, Adjusted R-squared: 0.9708F-statistic: 300.5 on 1 and 8 DF, p-value: 1.249e-07


Comparing Two Sets of DataComparing Two Sets of Data

Example: Consider two wireless different access points. Which one is faster?

Inputs: same set of 10 messages communicated through both access points.

Response (usecs):Latency1 Latency2

22 1923 2019 2418 2015 1420 1826 2117 1719 1717 18

Approach:Take difference of data and

determine CI of difference.If CI straddles zero, cannot tell

which access point is faster.

CI95% = (-1.27, 2.87) usecs

Confidence interval straddles zero. Thus, cannot determine which is faster with 95% confidence


Plots with Error BarsPlots with Error Bars

Execution time of SuperLU linear Execution time of SuperLU linear system solution on parallel computersystem solution on parallel computer

Ax = bAx = bFor each p, ran problem multiple For each p, ran problem multiple times with same matrix size but times with same matrix size but different valuesdifferent valuesDetermined mean and CI for Determined mean and CI for each p to obtain curve and error each p to obtain curve and error intervalsintervals


Statistical Point Analysis Statistical Point Analysis

Output from ModelOutput from Model Mean, Std Dev, Mean, Std Dev, Variance, Box PlotVariance, Box Plot

Check for Randomness Check for Randomness Residual AnalysisResidual Analysis

Check for Distribution Check for Distribution QQ--Q Plot Q Plot Confidence IntervalConfidence IntervalTT--test Analysis test Analysis

CompareCompareSpecificationSpecification Decision Decision


ConclusionsConclusionsIncreasing trend towards highly integrated systems, there is an ever growing demand for hardware based on SOC technology Development of these complex components places correspondingly multifarious demands on the design engineer, New CAD and simulation resources are providing system and chip designers with the design tools necessary for integrated CMOS hardware New CAD tools can be used with a standard design methodology to produce mixed technology designs Integrate analog, digital and mixed signal into a single device design that can be fabricated through a conventional CMOS fabrication processDesign methodology and new CAD/simulation tools allow the designengineer to focus on the intricacies of mixed mode integrated circuit design (ex noise reduction, signal cross-talk, etc.) without loosing site of chip functionality or system level performance specification



Dr. Carla Purdy

Associate Professor

Department of ECECS


Dr. Harold W Carter

Professor and Dept. Head

Department of ECECS


Dr. Fred R Beyette Jr.

Associate Professor

Department of ECECS


Aaron C. Barnes, M.S

Co-Director, Microsurgery

Advanced Design Lab

Doheny Retina Institute

Univ. of Southern California

Alla S. Kumar

Graduate Student

Department of ECECS


L. Ramasamy, M.S

Doctoral Researcher

Department of ECECS


Question and AnswersQuestion and Answers

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