Lecture No.1

7/21/2019 Lecture No.1

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DSP Processor DSP Processor

GULAM AMERGULAM AMER Head of the Department Head of the Department

Electronics & Instrumentation EngineeringElectronics & Instrumentation Engineering



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IntroductionIntroduction

Digital signals & systemsDigital signals & systems

DSP (Digital Signal Processing)DSP (Digital Signal Processing)

Digital Signal Processors (DSPs) vs GeneralDigital Signal Processors (DSPs) vs General

Purpose Processors (GPPs)Purpose Processors (GPPs)



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DSPs FeaturesDSPs Features

High speed DSP computationsHigh speed DSP computations Specialized instruction set

High performance repetitive numeric calculations

ast & efficient memory accesses

Special mechanism for real!time "#$Special mechanism for real!time "#$ %o poer consumption%o poer consumption

%o cost in comparison ith GPPs%o cost in comparison ith GPPs



'

DSPs General ApplicationsDSPs General Applications

Digital cellular phonesDigital cellular phones

Satellite communicationsSatellite communications

Seismic analysisSeismic analysis ehicle collision avoidanceehicle collision avoidance

Secure communicationsSecure communications

oice over "nternetoice over "nternet

ape less anseringape less anseringmachinesmachines

*otor control*otor control

Sonar Sonar

oice mailoice mail

Digital camerasDigital cameras

+avigation e,uipment +avigation e,uipment *odems (P$S- "SD+-*odems (P$S- "SD+-

ca.le-///)ca.le-///)

0udio production0udio production

+oise cancellation +oise cancellation ideoconferencingideoconferencing

*edical ultrasound*edical ultrasound

*usic synthesis- effects*usic synthesis- effects

1adar 1adar



DSPs μPs ApplicationsDSPs μPs Applications

Speech and audio compressionSpeech and audio compression

ilteringiltering

*odulation and demodulation*odulation and demodulation

rror correction coding and decodingrror correction coding and decoding

0udio processing (e/g/- surround sound- noise reduction-0udio processing (e/g/- surround sound- noise reduction-

e,ualization- sample rate conversion- echo cancellation)e,ualization- sample rate conversion- echo cancellation)

Signaling (e/g/- D* detection)Signaling (e/g/- D* detection)

Speech recognitionSpeech recognition

Signal synthesis (e/g/- music- speech synthesis)Signal synthesis (e/g/- music- speech synthesis)



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DSPs CharacteristicsDSPs Characteristics

5/5/ Data path & internal 0%6 architectureData path & internal 0%6 architecture

2/2/

Specialized instruction setSpecialized instruction set

3/3/ 7ternal memory architecture7ternal memory architecture

'/'/ Specialized addressing modesSpecialized addressing modes

// Specialized e7ecution controlSpecialized e7ecution control

4/4/ Specialized peripherals for DSPSpecialized peripherals for DSP



Data PathData Path

DSPsDSPs

Performs all 9ey arithmeticPerforms all 9ey arithmetic

operations in 5 cycle/operations in 5 cycle/

Hardare support forHardare support for

managing numeric fidelity:managing numeric fidelity: Shifters

Guard .its

Saturation

GPPsGPPs

*ultiplies often ta9e ;5*ultiplies often ta9e ;5

cyclecycle

Shifts often ta9e ;5 cycleShifts often ta9e ;5 cycle

$ther operations (e/g/$ther operations (e/g/

saturation- rounding)saturation- rounding)

typically ta9e multipletypically ta9e multiple

cyclescycles


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DSPs Data Path ExampleDSPs Data Path Example

0 representative conventionalfi7ed!point DSP processor data

path (from the *otorola

DSP4=77- a 2'!.it- fi7ed point

processor family)


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Instruction SetInstruction Set

DSPs

Specialized- comple7Specialized- comple7

instructionsinstructions

*ultiple operations per*ultiple operations per

instruction (e/g/ usinginstruction (e/g/ using

%"?)%"?)

GPPs

General!purposeGeneral!purpose

instructionsinstructions

ypically only oneypically only one

operation per instructionoperation per instruction


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VLIWVLIW

*a@or features:*a@or features: *ultiple independent

operations per cycle Pac9ed into a single large

AinstructionB or Apac9etB

*ore regular- orthogonal-

1"SC!li9e operations %arge-

uniform register sets

ery long instruction ordery long instruction ord

(%"?) architectures are(%"?) architectures are

garnering increased attentiongarnering increased attentionfor DSP applications/for DSP applications/



Memor ArchitectureMemor Architecture

DSPs

Harvard architectureHarvard architecture

2!' memory accesses#cycle2!' memory accesses#cycle

+o cacheson!chip +o cacheson!chip

S10*S10*

GPPs

on +eumann architectureon +eumann architecture

ypically 5 access#cycleypically 5 access#cycle

*ay use caches*ay use caches



Von !eumann ArchitectureVon !eumann Architecture

he on +eumann memory

architecture- common among micro

controllers/ Since there is only onedata .us- operands cannot .e loadedhile instructions are fetched-creating a .ottlenec9 that slos thee7ecution of DSP algorithms/



"ar#ard Architecture"ar#ard Architecture

0 Harvard architecture- common tomany DSP processors/ he processor can simultaneously access

the to memory .an9s using toindependent sets of .uses- alloingoperands to .e loaded hile

fetching instructions//


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Addressin$ ModesAddressin$ Modes

DSPs

Dedicated addressDedicated address

generation unitsgeneration units

Specialized addressingSpecialized addressing

modesE e/g/:modesE e/g/: 0uto!increment

*odulo (circular) Fit!reversed (for )

Good immediate dataGood immediate data

supportsupport

GPPs

$ften- no separate address$ften- no separate address

generation unitgeneration unit

General!purposeGeneral!purpose

addressing modesaddressing modes



Execution ControlExecution Control

Hardare support for fast loopingHardare support for fast looping

AAast interruptsB for "#$ handlingast interruptsB for "#$ handling

1eal!time de.ugging support1eal!time de.ugging support



PeripheralsPeripherals

Host portsHost ports

Fit "#$ portsFit "#$ ports

$n!chip D*0 controller $n!chip D*0 controller

Cloc9 generatorsCloc9 generators

Synchronous serial portsSynchronous serial ports

Parallel portsParallel ports

imersimers

$n!chip 0#D- D#0 converters$n!chip 0#D- D#0 converters



DSPs classi%ications &'(DSPs classi%ications &'(

Fy arithmetic formatFy arithmetic format i7ed!point

loating!point

Floc9 floating!point

Fy data idthFy data idth

ypical fi7ed!point DSPs: 54!.it ypical floating!point DSPs: 32!.it

Fy memory organizationFy memory organization

Fy multiprocessor supportFy multiprocessor support


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DSPs classi%ications &)(DSPs classi%ications &)(

Fy speedFy speed *illion of instruction per second (*"PS)

0 .asic operation (e/g/ *0C)

0 .asic algorithm (e/g/ - "1 or ""1 filter)

Fenchmar9 programs

Fy poer consumptionFy poer consumption $perating voltage

Sleep or idle mode

Programma.le cloc9 dividers

Peripheral control


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DSPs E#olutionDSPs E#olution

irst generation (" *S32=5=)irst generation (" *S32=5=)

Second generation (*otorola DSP4==5- 0&Second generation (*otorola DSP4==5- 0&

DSP540- 0nalog Dev/ 0DSP!25==- " *S32=C=)DSP540- 0nalog Dev/ 0DSP!25==- " *S32=C=)

hird generation (*otorola DSP43=5- "hird generation (*otorola DSP43=5- "

*S32=C'5- " *S32=C<=- *otorola *C4<34)*S32=C'5- " *S32=C<=- *otorola *C4<34)

ourth generation (" *S32=C42=5- "ntel Pentiumourth generation (" *S32=C42=5- "ntel Pentium**)**)



2=

First Generation &'*+)(First Generation &'*+)(

54!.it fi7ed!point54!.it fi7ed!point

Harvard architectureHarvard architecture

0ccumulator 0ccumulator

Specialized instruction setSpecialized instruction set

3>= ns *0C time (22< ns3>= ns *0C time (22< ns

today)today)



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Second Generation &'*+,(Second Generation &'*+,(

2'!.it data- instructions2'!.it data- instructions

3 memory spaces (- - P)3 memory spaces (- - P)

Parallel movesParallel moves

Single! and multiSingle! and multi

instructioninstruction

hardarehardare

loopsloops

*odulo addressing*odulo addressing

8 ns *0C (25 ns today)8 ns *0C (25 ns today)



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-hird Generation &'**.(-hird Generation &'**.(

nhanced conventional DSP architecturesnhanced conventional DSP architectures

3/= or 3/3 volts3/= or 3/3 volts

*ore on!chip memory*ore on!chip memory

0pplication!specific function units in data path or as0pplication!specific function units in data path or as

co!processorsco!processors

*ore sophisticated de.ugging and application*ore sophisticated de.ugging and applicationdevelopment toolsdevelopment tools

DSP cores (Pine & $a9 from DSP G/- cDSP from ")DSP cores (Pine & $a9 from DSP G/- cDSP from ")

2= ns *0C (5= ns today)2= ns *0C (5= ns today)



23

Fourth Generation &'**+(Fourth Generation &'**+(

Flazing cloc9 speeds and super scalar architecturesFlazing cloc9 speeds and super scalar architectures

%"?!li9e architectures- achieve top performance%"?!li9e architectures- achieve top performance

via high parallelism and increased cloc9 speedsvia high parallelism and increased cloc9 speeds

3 ns *0C throughput3 ns *0C throughput

7pensive- poer!hungry7pensive- poer!hungry



2'

DSPs E#olution ChartDSPs E#olution Chart



2

DSPs Per%ormance ChartDSPs Per%ormance Chart

7ecution times for a 24!

point comple7 in

microseconds



24

/ole o% GPPs &'(/ole o% GPPs &'(

0dded capa.ilities:0dded capa.ilities: 0dd single!instruction- multiple!data instruction set

e7tensions (e/g/- ** Pentium) "ntegrate a fi7ed!point DSP processor!li9e data path and

related resources ith an e7isting mC#mP core (e/g/ Hitachi

SH!DSP)

0dd a DSP co!processor to an e7isting mC#mP core (e/g/-01* Piccolo)

Create an all!ne- hy.rid architecture (e/g/ Siemens riCore)



28

/ole o% GPPs &)(/ole o% GPPs &)(

0ssisted capa.ilities:0ssisted capa.ilities: ery high cloc9 rates (==!5=== *Hz)

Super scalar (Amulti!issueB) architectures

Single!cycle multiplication and arithmetic ops/

Good memory .andidth

Franch prediction

"n some cases- single!instruction- multiple!data (S"*D)

ops

Caching & pipelining



2<

ConclusionConclusion

DSP processor performance has increased .y a factor of a.outDSP processor performance has increased .y a factor of a.out

5=7 over the past 5 years (I'=J#year)5=7 over the past 5 years (I'=J#year)

Processor architectures for DSP ill .e increasingly specializedProcessor architectures for DSP ill .e increasingly specializedfor applications- especially communications applicationsfor applications- especially communications applications

General!purpose processors ill .ecome via.le for many DSPGeneral!purpose processors ill .ecome via.le for many DSP

applicationsapplications

6sers of processors for DSP ill have an e7panding array of6sers of processors for DSP ill have an e7panding array ofchoiceschoices

Selecting processors re,uires a careful- application!specificSelecting processors re,uires a careful- application!specific

analysisanalysis



We0 Lin1s 2 In%ormationWe0 Lin1s 2 In%ormation

http://www.bdti.com http://www.bdti.com

http://www.eg3.com/dsphttp://www.eg3.com/dsp

Buyer’s Guide to DSP Processors Buyer’s Guide to DSP Processors- Fer9eley- California:- Fer9eley- California:

Fer9eley Design echnology- "nc/- 5>>'- 5>>- 5>>8- 5>>>/Fer9eley Design echnology- "nc/- 5>>'- 5>>- 5>>8- 5>>>/

Phil %apsley- Keff Fier- 0mit Shoham- and dard 0/ %ee-Phil %apsley- Keff Fier- 0mit Shoham- and dard 0/ %ee-

DSP Processor Fundamentals: Architectures and Features DSP Processor Fundamentals: Architectures and Features--Fer9eley- California: Fer9eley Design echnology- "nc/-Fer9eley- California: Fer9eley Design echnology- "nc/-

5>>4/5>>4/

?ill Strauss-?ill Strauss- DSP Strategies 2002 DSP Strategies 2002- empe- 0rizona:- empe- 0rizona:

orard Concepts 5>>>orard Concepts 5>>>

Lecture No.1

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