High Frequency Resonant SEPIC Converter with Wide · PDF file1397 High Frequency Resonant SEPIC Converter with Wide Input and Output Voltage Ranges Jingying Hu†, Anthony D....

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High Frequency Resonant SEPIC Converter withWide Input and Output Voltage Ranges

Jingying Hu†, Anthony D. Sagneri†, Juan M. Rivas† §, Yehui Han†, Seth M. Davis‡, David J. Perreault††LABORATORY FOR ELECTROMAGNETIC AND ELECTRONIC SYSTEMS

MASSACHUSETTS INSTITUTE OF TECHNOLOGY, ROOM 10–171CAMBRIDGE, MASSACHUSETTS 02139

EMAIL: [email protected]

‡CHARLES STARK DRAPER LABORATORY

555 TECHNOLOGY SQUARE

CAMBRIDGE, MA 02139

§GE GLOBAL RESEARCH

1 RESEARCH CIRCLE

NISKAYUNA, NY 12309

Abstract—This document presents a resonant SEPIC converterand control method suitable for high frequency (HF) and veryhigh frequency (VHF) dc-dc power conversion. The proposed de-sign features high efficiency over a wide input and output voltagerange, up-and-down voltage conversion, small size, and excellenttransient performance. In addition, a resonant gate drive schemeis presented which provides rapid startup and low-loss at HFand VHF frequencies. The converter regulates the output usingan on-off control scheme modulating at a fixed frequency. Thiscontrol method enables fast transient response and efficient lightload operation while providing controlled spectral characteristicsof the input and output waveforms. An experimental prototypehas been built and evaluated. The prototype converter, built withtwo commercial vertical MOSFETs, operates at a fixed switchingfrequency of 20 MHz, with an input voltage range of 3.6V to 7.2V,an output voltage range of 3V to 9V and an output power ratingof up to 3W. The converter achieves higher than 80% efficiencyacross the entire input voltage range at nominal output voltage,and maintains good efficiency across the whole operating range.

Index Terms—resonant dc-dc converter, quasi-resonant SEPICconverter, high frequency, VHF integrated power converter,class E inverter, resonant gate drive, resonant rectifier, on-offcontrol.

I. INTRODUCTION

MANY portable electronic applications could benefit froma power converter able to achieve high efficiency across

wide input and output voltage ranges at a small size. However,it is difficult for many conventional power converter designsto provide wide operation range while maintaining high effi-ciency, especially if both up-and-down voltage conversion isto be achieved. Furthermore, the bulk energy storage requiredat contemporary switching frequencies of a few megahertzand below limits the degree of miniaturization that can beachieved and hampers fast transient response. Therefore, de-sign methods that reduce energy storage requirements andexpand efficient operation range are desirable. In this paper,

we exploit the use of resonant switching and gating along withfixed frequency control techniques to achieve these goals.

This paper introduces a quasi-resonant SEPIC converter,resonant gate drive and associated control methods suitable forconverter designs at frequencies above 10 MHz. Unlike manyresonant converter designs [1]–[4], the proposed approachprovides high efficiency over very wide input and outputvoltage ranges and power levels. It also provides up-and-down conversion, and requires little energy storage whichallows for excellent transient response. Unlike conventionalquasi-resonant and multi-resonant converters [3], [4], no bulkinductor is used and the converter operates at fixed frequencyand duty ratio. These attributes reduce passive component size,improve response speed, and enable the use of low-loss si-nusoidal resonant gating. Furthermore, a new fixed-frequencyon/off control is introduced which provides good control overinput and output frequency content. The proposed design isdiscussed in the context of a prototype converter operating overwide input voltage (3.6 - 7.2V), output voltage (3 - 9V) andpower (0.3 - 3W) ranges. Section II presents the new proposedcircuit design and discusses its operation. A low-loss resonantgate drive method suitable for this application is explained indetail in Section III, followed by a discussion of the convertercontrol scheme in Section IV. Section V presents the designand experimental validation of a converter implementing theapproach.

II. A NEW RESONANT SEPIC CONVERTER

Fig. 1 shows the power stage of the proposed converter.The topology used here has some topological similaritieswith both the conventional SEPIC converter [5] and with themulti-resonant SEPIC converter proposed in [4]. However, thedetailed component placement and sizing, operating character-istics, and control approach are all very different from previousdesigns.

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+−

+−

M1

CEX

CEX2

D1

CS

LP

LF

VIN VOUT

+

_

+

-

VDS VR

Fig. 1. Schematic of the proposed resonant SEPIC converter topology.

First, consider the circuit topology. The conventional SEPICconverter has two bulk (ac choke) inductors, and yields hardswitching of the switch and diode. The multi-resonant SEPIC[4] utilizes similar bulk inductors, but explicitly introducescapacitances in parallel with the switch and diode along witha resonant inductor in series with the coupling capacitor CS

to achieve zero-voltage soft switching of the switch and diode.The design introduced here also explicitly utilizes capacitancesin parallel with the switch and diode. However, in contrastto previous resonant SEPIC designs [3], [4], the design herehas no bulk inductors. Rather, it uses only two resonantinductors: one inductor, LF , resonates with the net switchcapacitance, COSS + CEX , for resonant inversion, while theother inductor, LP , resonates with the rectifier capacitance,CEX2, for resonant rectification. This design method leadsto reduced magnetic component count, along with greatlyincreased response speed.

A further major difference between the converter proposedhere and previous resonant SEPIC converters relates to control.Unlike conventional designs which used variable frequencycontrol to regulate the output [3], [4], the design here operatesat fixed switching frequency and duty ratio. (As discussed inSection IV, output control is instead achieved through on/offcontrol, in which the entire converter is modulated on andoff at a modulation frequency that is far below the switchingfrequency [6]–[11].) Operation at a fixed frequency and dutyratio enables the elimination of bulk magnetic components(as described above) and facilitates the use of highly efficientsinusoidal resonant gating (as described in Section IV). More-over, it enables zero-voltage soft switching to be maintainedover wide input and output voltage ranges, and eliminates thevariation in device stress with converter load that occurs inmany resonant designs [3], [4].

Operation of this converter can be understood as a linkingof two subsystems: a resonant inverter and a resonant rectifier.The design procedure for the proposed topology involvesdesigning the rectifier and inverter individually, coupling theinverter and rectifier together, then retuning as necessary toaccount for nonlinear interactions between the inverter andrectifier. We treat these steps in the following subsections.

A. Rectifier Design

The design procedure of a full dc-dc converter starts with therectifier. The particular resonant rectifier topology of interest

+−IIN LR

D1

CEX2

COUT

VOUT

+

_

VR

Fig. 2. Circuit model for the resonant rectifier used in tuning the rectifiercomponents.

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Fig. 3. Fundamentals of rectifier voltage, VR and current, IIN of theresonant rectifier of Fig. 2 tuned to look resistive at an operating frequency of20MHz. Simulation is for a rectifier built with a DFLS230L schottky diode,LR=118nH, CEX2=150pF, and VOUT =7V.

here is illustrated in Fig. 2 (along with a sinusoidal drivesource used in the rectifier design). A similar rectifier structurewas exploited in [7] but under different driving conditions. Therectifier utilizes a resonant tank comprising a resonant inductorLR (which provides a dc path for the output current) and acapacitance including an external capacitor CEX2 along withadditional parasitic junction capacitance from the diode.

To design the rectifier, we start by assuming that it isdriven by a sinusoidal current source of magnitude IIN ata given output voltage VOUT , as illustrated in Fig. 2. (It isrecognized that the actual drive waveform is not sinusoidal;this fact is addressed in a later tuning step.) For a desiredoutput power level and operating frequency, the rectifier istuned to appear resistive in a describing function sense byadjusting CEX2 and LR. That is, we adjust CEX2 and LR

such that the fundamental component of VR is in phase withthe drive waveform IIN (or alternatively has some phaseshift, thus presenting an equivalent reactive component.) Indoing this, we start by assuming a drive amplitude IIN . Wealso adjust the values of LR and CEX2 and/or the assumeddrive level IIN to ensure that the desired power is deliveredthrough the rectifier. The equivalent rectifier impedance at


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TABLE ITUNED AND DETUNED RECTIFIER COMPONENT VALUES

LR 90 nH 118 nH 118 nHCEX2 150 pF 50 pF 150 pF|ZEQV | 18.07 Ω 19.08 Ω 18.12 Ω∠ZEQV 36.9 o 47.69 o 0POUT 2.28 W 2.97 W 4.12 WEfficiency 89.6% 90.6% 91.4%

+− REQV

CF

LF

LS

CSVIN

Fig. 4. Resonant inverter including a matching circuit and equivalent loadresistance. This circuit model is used for tuning the inverter.

the operating frequency is calculated as the complex ratioZEQV = VR,1/IIN , where VR,1 is the fundamental of VR.This equivalent impedance can be used in place of the rectifierfor designing the resonant inverter, assuming that the majorityof the output power delivered to the load is transferred throughthe fundamental.

The following design example of a 4W rectifier at a nominaloutput voltage of 7V illustrates the tuning procedure de-scribed above. The rectifier uses a commercial Schottky diodeDFLS230L (having an approximate capacitance of 70pF) andis driven by a sinusoidal current source IIN with an amplitudeof 0.7A. The value of LR of the resonant rectifier is selected inconjunction with CEX2 so that the fundamental rectifier inputvoltage VR is in phase with rectifier input current IIN . Fig. 3shows the input current and voltage of a resonant rectifier (likethe one in Fig. 2) simulated using PSPICE. For the simulationshown, LR = 118nH , CEX2 = 150pF , VOUT = 7V , andthe sinusoidal input current IIN = 0.7A at a frequency of20MHz. The average power delivered to the load under theseconditions is 4.12W . In Fig. 3, the fundamental componentof the input voltage and the current are in phase resulting ina rectifier with an equivalent resistance (at the fundamental)of approximately 17.14Ω. As the values of LR and CEX2

are changed, output power level and the phase relationshipbetween VR and IIN change. As the phase difference betweenVR and IIN increases, the losses due to reactive currents rise,reducing the output power and the overall efficiency of therectifier, as shown in Table I.

B. Inverter Design

Consider the inverter network of Fig. 4, which includesimpedance matching from the inverter to the equivalent recti-fier impedance. Inverter tuning begins by selecting appropriatematching components. (The matching inductance is later ab-sorbed as part of the rectifier.)

Assuming that most power is transferred through the fun-damental, the maximum equivalent resistance RMAX neededto deliver an output power level of POUT with a fundamen-

tal voltage at the MOSFET drain, VDS,1 can be calculatedfrom RMAX = V 2

DS,1/(2 ∗ POUT ),where RMAX is the“transformed” resistance loading the drain-to-source port ofthe inverter. As Fig. 5 illustrates, the drain waveform of theresonant SEPIC converter is similar to that of a conventionalClass-E inverter. Therefore, one possible starting point toobtain RMAX is to approximate the fundamental voltage asin the Class-E inverter case, VDS,1 = 1.6 ∗ VIN , [12]. (Itis recognized that the actual VDS,1 of the resonant SEPICconverter is not exactly 1.6 ∗ VIN , the effects of which canbe addressed by adjusting output power when coupling theinverter and rectifier together.)

When the rectifier equivalent resistance, REQV , is higherthan the value RMAX to meet the output power requirement,a matching network consisting of LS and CS is requiredto transform the load impedance to a lower value [7], [13],[14]. The approximate transformation ratio can be obtainedas RMAX/REQV . One possible starting point to selectingthe component values for LS and CS is to design a match-ing network such that a transformation ratio RMAX/REQV

occurs at the desired operating frequency. Additional minoradjustments on these component values may be done later inconjunction with tuning CF and LF with a simulation tool(e.g. PSPICE) to achieve a resulting drain-to-source switchingwaveform VDS that has ZVS and zero dv/dt at turn on. Inpractice, the resonance of LS and CS can be set to be exactlyat the switching frequency, or slightly above or below theresonant frequency, all of which are typically viable and willlead to a working design. In a given application, one tuningmay result in more achievable component values and thereforemay be more favorable compared to the others. Once matchingnetwork components have been selected, inductance LS maybe absorbed into the rectifier inductance LR.

The input resonant network, comprising LF and CF , largelyshapes the frequency at which the drain waveform rings upand down. For an inverter operating at a 50% duty ratio, onepossible starting point for LF is to tune the input resonantnetwork such that its resonance frequency is at twice theswitching frequency, as in (1). This tuning selection is similarto that of the “second harmonic” class E inverter in [15], [16].

LF =1

16π2f2SW CF

(1)

Note that the capacitor CF includes the parasitic capacitanceof the semiconductor switch and possibly an external capacitorCEX . In some applications where the packaging inductanceof the semiconductor switch is significant, selecting CF tobe solely provided by the device capacitance may be a goodchoice, because it prevents waveform distortion caused byadditional ringing between the external capacitance and thepackage inductance. In other cases where the circulatingcurrent is significant, it is a better choice to add additionalhigh-Q ceramic capacitance in parallel with the lossy deviceparasitic capacitance to reduce the circulating current loss. Onestarting point for CF is to assume it is comprised solely ofparasitic capacitance of the semiconductor switch, allowingan initial value of LF to be calculated. Since LF significantlyimpacts the transient response speed, a small LF is generally


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preferred. If the starting point of CF leads to too large a valueof LF , additional parallel capacitance CEX may be added untilthe value of LF is in the desired range.

Once the initial values of LF , CF , LS and CS are de-termined from the procedure above, additional tuning can bemade via minor adjustments of the component values alongwith the duty ratio until the resulting drain-to-source switchingwaveform VDS achieves ZVS and zero dv/dt turn on, the so-called class E switching waveform.

Using the equivalent resistance REQV = 17.14Ω fromthe rectifier design discussed previously, a 20MHz inverterutilizing two commercial vertical MOSFETs SPN1443 inparallel can be designed in the following manner: a matchingnetwork which transforms the equivalent rectifier impedancefrom 17.14Ω to 4Ω at about the operating frequency is requiredin order to deliver 4W at an input voltage of 3.6V . Thecomponent values for such a matching network are LS =76nH and CS = 1120pF . If CF is to be comprised solelyof the parasitic capacitance of SPN1443 (about 160pF), theresulting LF is about 141nH , a condition which deterioratesthe transient response speed and overall closed-loop efficiency.In this design, it is found through time-domain simulations thatit is desirable to add additional high-Q ceramic capacitance inparallel with the lossy device parasitic capacitance to reducethe overall loss and to reduce the component value (and size)of the input inductor LF . A starting value for LF is chosen tobe 22nH (so that the inductance is small enough to allow forfast transient response and large enough to not be significantlyaffected by low-Q board parasitic inductance), resulting in anexternal capacitor CEX of 550pF at a 50% duty ratio.

C. dc/dc Retuning

An entire converter design may be accomplished by con-necting the tuned inverter to the resonant rectifier. When theinverter and rectifier are connected, the circuit waveforms andthe output power level may be slightly different than that pre-dicted by the inverter loaded with the equivalent impedance,due to the non-linear interaction between the inverter/matchingnetwork with the rectifier. Minor additional tuning may thusbe required to achieve ZVS and the required power level. Thefinal component values for a complete converter using theexample rectifier and inverter design described in this sectionwill be presented in Section V. A complete discussion of thetuning methodology for these components is found in [17].

Fig. 5 shows the idealized drain and rectifier voltage wave-forms for the proposed design over a range of input voltagesusing the techniques outlined in previous subsections (thecomponent values are included in the description of Fig. 5).It can be seen that zero-voltage soft switching is achieved atfixed frequency and duty ratio across a wide range of inputvoltages.

III. GATE DRIVER

At HF and VHF frequencies, traditional hard-switched gatedrives typically incur too much loss for acceptable efficiency,especially for low power converters. Resonant gating canreduce the gating loss significantly at these frequencies [7]–[9],

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Fig. 5. Simulated drain (VDS ) and rectifier (VR) voltages for a 20 MHzconverter operating with Vout = 7 V, LF = 22nH , CEX = 780pF ,CEX2 = 100pF , CS = 1270pF , and LP = 41nH . Inductor Q of70 and capacitor Q of 3000 is assumed. Two SPN1443 MOSFETs anda DFLS230L diode are used.

ENABLE

LS

LP

D2

M3

U1 U2 x 8

U3

CP

CGD

CGS

Rg

Fig. 6. Resonant sinusoidal gate drive circuit with MOSFET gate model.

[18]. By recovering a portion of the gate energy each cycle,much lower power is required to drive the gate, minimizingthe impact that gating loss has on overall converter efficiency.

While use of fixed-frequency and fixed-duty-ratio operationreduces driver complexity, the use of on-off control of theoutput introduces some important requirements. In addition toachieving low power operation at steady state, a practical gatedrive for our system must settle rapidly at startup and shut-down to maintain good converter transient response and highefficiency under modulation. A low-loss gate drive method isdesigned to meet these criteria for this converter. Fig. 6 showsa schematic of the resonant driver circuit we have adopted.The detailed design approach and the operation of the gatedrive is summarized as follows:

In the driver of Fig. 6, a bank of CMOS inverters drivesthe gate via a tuned resonant network. The shunt branch ofLP and CP is inductive at the switching frequency (withCP simply acting as a dc block). LP is sized to partiallycancel the gate admittance, leaving the parallel combinationof LP and the gate capacitive, but with higher impedancethan the gate capacitance alone. LP thus provides some ofthe reactive power needed to charge and discharge the gate.LS serves multiple functions. First, it is resonant with the


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TABLE IIGATE DRIVE COMPONENT VALUES

U1 NC7SZ08U2, U3 NC7WZ04LS 110 nHLP 72 nHCP 0.1 μFD2 MA27D27M3 FDV303N

parallel combination of the LP and CGATE near the switchingfrequency such that there is significant voltage gain from theCMOS inverter bank to the gate at the switching frequency.Second, it provides a high impedance to harmonic voltagesapplied by the CMOS inverter, reducing inverter loss.

The tuning method applied to the resonant gate drive issimilar to that described in [9], with slight changes due todifferent device and overall system characteristics. Unlike [9],an optimal gate drive design cannot be achieved with thephase of a drain to gate transfer function close to 180◦.Achieving such a phase angle will either incur too muchgating loss or require a large LS and a small LP which willslow the gate drive startup and deteriorate the overall systemperformance (The MOSFET used here present an equivalentRg of 1.17 Ω, Cgs of 550 pF and Cgd of 43 pF). Fortunately,for this application, the drain-to-gate feedback is not crucialto achieving the desired amplitude at the gate. A better overallefficiency is achieved with a drain-to-gate phase angle around250◦. Fig. 7 shows the gate-to-drain transfer function andgate-to-driver transfer function for such a gate drive design.Component values for this gate drive are shown in Table II.More details of the gate drive design appear in [17].

To provide on/off modulation capability, the CMOS inverterbank is driven by an oscillator signal that is gated by an enableinput. The enable input provides on/off control. Moreover,an active pull-down network comprising a CMOS inverter(U3), a MOSFET (M3), and a diode (D2) helps providerapid shutdown at turnoff. This gate drive enables startupand shutdown of the converter (to steady state) within fourswitching cycles as shown in Fig. 8. This is sufficiently fastto maintain good efficiency under on-off modulation.

IV. CONTROL STRATEGY

This control strategy employed is an on-off control scheme,in which switching of the converter is gated on and offto control the average power delivered to the output. Thefrequency at which the converter is modulated on and offis much lower than the converter switching frequency. Inthis approach, the power stage components are sized for thethe very high switching frequency, while the converter inputand output filters (e.g. capacitors) are sized for the lowermodulation frequency.

One on-off control method, voltage hysteretic control (orbang-bang control), has been implemented in previous reso-nant converter designs [6]–[11], [18]. Voltage hysteretic on-off control offers advantages such as a well-controlled voltageband, good efficiency at very light load, and unconditionalstability. However, the input and output waveforms have

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Fig. 7. Gate drive transfer functions.

variable frequency content (owing to the variable-frequencymodulation) making this control method undesirable in someapplications (such as communication systems), and increasingthe difficulty of designing input and output filters.

To address the variable frequency components residing inthe input/output waveforms, a new approach, in which the on-time of the converter is pulse-width modulated within a fixedmodulation period, is utilized to implement the on-off controlmethod. Unlike hysteretic on-off control, PWM on-off controloperates at a fixed modulation frequency, leading to well-defined frequency content at the converter input and output.On the other hand, efficiency tends to decline at extreme lightloads, when the converter may operate for only a few switchingcycles each modulation period. The characteristics of thiscontrol method are similar in many regards to conventionalfixed-frequency PWM. However, instead of modulating thevoltage applied to a filter, the power delivered to the outputcapacitor and load is modulated.

The basic control approach is illustrated in Fig. 9, and amore detailed illustration of one particular circuit design and


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Fig. 8. Experimental On/Off transient response operating at VIN =3.6V andVOUT =5.2V

Gc(s) Hplant(s)

Hsense(s)

d

dc-dcconvertercompensator

vOUTVREF

Fig. 9. Block diagram for PWM on/off control method

its control block diagram are shown in Fig. 10. The controllerin our prototype is implemented with a conventional PWMchip whose PWM output is the enable signal of the powerstage gate drive. The converter power stage can be modeledas a one-pole system with the converter approximated as acontrolled current source feeding the output capacitor andload COUT and RLOAD, where RLOAD is the effective loadresistance of the converter. The transfer function of the plant,

−

+ Vref

PWM

Converter

Vout R1

R2 C2

R3

C3

C4

R4

CoutOn/Off

Rload

Signal

(a) On/off PWM control of a resonant dc-dc converter.

KPWM KDC-DC

RLOAD

RLOADCOUTs+1

R2R3

R1R2+R1R3+R2R3

1

R3

( 1

C3s+

R4

R4C4s+1)

+

-

VIN

vOUTiOUTd

VREF

(b) Block diagram model of the closed-loop system

Fig. 10. Implementation of PWM control for the prototype converter.

HPLANT (s) = VOUT (s)/d, where d is the duty ratio of theenable signal, is given by

HPLANT (s) =VOUT

d= Kdc−dc ∗ Rload

RloadCOUT s + 1(2)

In (2), KDC−DC is the dc converter output current under(constant) open-loop operation at a fixed input and outputvoltage. Values for KDC−DC can be found by direct measure-ment or simulation of the converter power stage at differentoperating points VIN , VOUT . Fig. 11 shows plots of KDC−DC

for the prototype converter for various operating conditions.The controller should be designed to be stable for all valuesof KDC−DC in the operating range (Here between 0.8 and1.55A). The transfer functions for the duty ratio controller,including sensor gain, error amplifier/compensation gain, andPWM modulator KPWM , are developed as is conventional induty ratio control. The circuits and models in our particularprototype are as illustrated in Fig. 10.

The PWM on-off control implementation utilizes a low-power Bi-CMOS PWM chip UCC2813. An error amplifierinternal to the chip with a reference voltage of 2V is employedto implement a P-I controller. The P-I controller looks atthe output voltage of the converter and integrates the errorbetween the reference voltage and the output voltage to obtainan error voltage. The error voltage is then compared with thesawtooth voltage of the PWM chip to generate a commandsignal turning the converter cell on and off at a duty ratio suchthat the output remains regulated even as the load changes. Thecomponent values of the P-I controller are listed in Table III.

To design a stable controller across an entire operatingrange, the plant is modeled at its lightest load condition where


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1

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Kd

cdc

Kdcdc vs. Vin

Vout=5VVout=7VVout=9V

Fig. 11. KDCDC for various operating conditions for the prototypeconverter.

TABLE IIIPWM CONTROLLER COMPONENT VALUES

R1 22 k ΩR2 8.2 k ΩC2 5 pFR3 10 k ΩC3 5 pFC4 15 pFR4 470 k Ω

the phase margin is the smallest (in this case, at the lowestinput voltage and highest output voltage), using the open-loop output current and power measurements of the converter.Once the model for an open-loop converter is determined, aP-I controller can be designed using the block diagram inFig. 10(b). In this model, KPWM is a gain factor introduced bythe PWM sawtooth waveform which converts an error voltageto a duty ratio (in this case, KPWM = 1/2.5), and R1, R2,R3, R4, C3 and C4 are the components of the output voltagedivider and the P-I controller in Fig. 10(a). The bode plot forthe loop gain at VOUT = 9V and output voltage deviationresponses to load steps of are shown in Fig. 12.

Note that the response speed illustrated in Fig. 12 is notlimited by energy storage or dynamics of the plant (thepower stage); instead it is limited by the bandwidth of thecontroller being restricted to a fraction of the PWM mod-ulation frequency. Thus, it is possible to further improvetransient response of the system through a fixed-frequencyPWM controller with hysteresis override. This modificationcan take advantage of the response speed of a hystereticcontroller during load-step transient operation, while providingcontrolled frequency content at the converter input and outputduring steady-state operation.

V. EXPERIMENTAL RESULTS

This section presents the design and experimental evaluationof the proposed resonant SEPIC converter. Table IV lists theconverter specifications. The converter operates at 20 MHz andutilizes two commercial 30 V vertical MOSFETs in parallel.

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TABLE IVEXPERIMENTAL DC-DC CONVERTER SPECIFICATIONS

Input Voltage Range 3.6 - 7.2 VOutput Voltage Range 3 - 9 VSwitching Frequency 20 MHzOutput Power 0.3 - 3 W

Fig. 13. Photograph of 20 MHz experimental prototype.

A photograph of the prototype of a dc-dc converter based onthe topology introduced in Section II is shown in Fig. 13. Thevalues of the power stage components are given in Table V.Note that the capacitor CEX is the external capacitance inparallel with the parasitic output capacitance of the MOSFETs,COSS . The control and gate drive circuitry is placed on theother side of the printed circuit board (not shown).

As can be seen in Table V, the largest inductor in the powerstage is 41 nH. The small sizes of the inductors are due bothto the high operating frequency of the converter (20 MHz),and to the resonant nature of the topology as described inSection II.

Converter waveforms are presented in Fig. 14, which showsmeasured drain, gate and rectifier voltages for minimum VIN

and maximum VIN at nominal VOUT . From the experimentalwaveforms, the topology indeed provides good zero voltageswitching characteristics. However, a degree of overlap lossdue to device capacitance, CGD can be observed in the design.Open-loop efficiency and power over the input voltage rangeare illustrated in Fig. 15, where the input voltage is swept from3.6 to 7.2 V, while the output voltage is kept at its nominalvalue, 7 V. A more complete open-loop efficiency plot takenover the entire operating range of the converter is shown inFig. 16. It is clear from these two figures that this topologyprovides good efficiency across a very wide operating rangeand up and down voltage conversion. This and all following

TABLE VPOWER STAGE COMPONENT VALUES

LF 22 nHLR 41 nHCEX 780 pFCEX3 100 pFCS 1270 pFM1 SPN1443 x 2D1 DSFL230L

−20 −10 0 10 20 30 40 50−25

−20

−15

−10

−5

0

5

10

15

20

25

30

time [ns]

Vo

ltag

e [V

]

Drain and Gate Voltage, Nominal Vout

Vin=3.6Vin=7.2

Fig. 14. Drain, rectifier and gate voltages for experimental 20 MHz converteroperating with Vout = 7 V.

3.5 4 4.5 5 5.5 6 6.5 7 7.52

4

6

8

10Output Power and Efficiency vs. Input Voltage (Nominal Vout)

Vin [V]

Ou

tpu

t P

ow

er [

W]

3.5 4 4.5 5 5.5 6 6.5 7 7.580

81

82

83

84

Eff

icie

ncy

[%

]

POUT

Efficiency

Fig. 15. Output power and efficiency over the input range at Vout = 7 V.

efficiency measurements include the losses of the gate driverand control circuitry.

Fig. 16 also shows the efficiency under closed loop oper-ation across the entire input and output voltage ranges forthe rated 3W output power. Ideally, when the converter isturned off, it consumes no power, and for the time when itis turned on, it operates in its most efficient state. In practice,there is quiescent loss in the control circuitry along with asmall amount of power loss during the turn-on and turn-offtransients, which explains the minor differences in efficiencyunder open-loop and closed-loop conditions.

The modulation frequency at which is the converter is turnedon and off is 170 kHz. Fig. 17 shows the gate voltage of themain switch, and illustrates how the converter is turned onand off as the output is regulated. Fig. 8 shows the details ofthe turn-on and turn-off transients. Fig. 18 shows the outputvoltage ripple when the converter is regulating the output at7.3V . The ripple is dominantly due to the on/off modulationat 170 kHz. The approximately 100mV ripple can be reduced(if so desired) by increasing the output capacitance. However,this is done at the expense of reducing the speed at whichthe output voltage can dynamically adjusted. It is important tonote that while the modulation frequency in Fig. 17 is 170kHz,the converter cell is operating at 20MHz.


1405

4 5 6 770

72

74

76

78

80

82

84

86

88

90

Vin [V]

Eff

icie

ncy

[%

]Efficiency vs Vin

4 5 6 770

72

74

76

78

80

82

84

86

88

90

Vin [V]

Eff

icie

ncy

[%

]

Efficiency vs Vin

vout=3.1Vvout=4.4vvout=5.2vvout=7vvout=8.7v

Fig. 16. Closed-loop (left) and open-loop (right) efficiency over the entireoperating range.

0 5 10 15−5

0

5

10Enable Signal

Vo

ltag

e [V

]

0 5 10 15−5

0

5

10Gate Voltage

time [us]

Vo

ltag

e [V

]

Fig. 17. Controller output signal and gate drive.

0 2 4 6 8 10−0.1

−0.05

0

0.05

0.1Output Ripple

Vo

ltag

e [V

]

0 2 4 6 8 10−2

0

2

4

6

8Modulation Command Signal

time [us]

Vo

ltag

e [V

]

Fig. 18. Output voltage ripple during steady-state closed-loop operation. Onecan see the 170 kHz ripple due to PWM on/off control. The 20 MHz ”Hash”(undersampled) due to the 20 MHz switching operation when the converteris enabled can also be seen.

In conventional dc-dc converters, the total required outputcapacitance is determined by the allowed voltage ripple and thedesired transient performance. It is often the latter conditionthat determines the minimum capacitance, calling for a largercapacitance than demanded by output ripple requirementsalone. However, the resonant SEPIC converter, with its in-herently fast transient response due to small valued inductors,does not have this problem. The output capacitor is sized solelybased on the desired on/off modulation frequency and outputripple, not by transient response limitations.

In addition to the advantages in size, weight and costrealized from smaller passive components, in increase inswitching frequency also leads to improved transient perfor-mance. Because of the small amount of energy stored in thepassive components in each switching cycle, the converter canquickly adjust to changes in load conditions. To illustrate this,Fig. 19 shows the measured output voltage when the outputpower is changed from 0.5W to 3.5W , and from 3.5W to0.5W by stepping the load. This transient response capabilitycan be attributed to the small inductors and capacitors requiredfor this topology at high frequency along with the controlscheme.

VI. CONCLUSION

This document presents a resonant SEPIC converter suitablefor extremely high frequency operation and for operatingacross a wide input and output voltage range. The topol-ogy addresses several shortcomings of conventional resonantSEPIC converters through the development of topology, gatedrive method and control scheme. The merits of these designmethods are verified via a 20MHz prototype with an inputvoltage range from 3.6V to 7.2V, an output voltage range of 3Vto 9V and a rated output power of 3W. The converter utilizesa low-loss sinusoidal gate drive and an on-off control methodmodulating at fixed frequency, provides both fast transientresponse and good control over spectral characteristics of theinput and output voltage. As this paper has demonstrated,it is possible for resonant SEPIC converters to achieve awide operating range, a small size and excellent transientresponse while maintaining good efficiency. It is hoped thatthese techniques will contribute to future development of low-power converters operating over wide ranges and extremehigh frequencies to meet the increasing demands of modernportable electronics.

REFERENCES

[1] R. Redl, B. Molnar, and N. Sokal, “Class E resonant regulated dc/dcpower converters: Analysis of operations and experimental results at1.5 MHz,” IEEE Transactions on Power Electronics, vol. PE-1, no. 2,pp. 111–120, April 1986.

[2] R. Redl and N. Sokal, “A new class-E dc/dc converter family withreduced parts count: Derivation, topologies, and design considerations,”in Technical Papers of the Fourth International High Frequency PowerConversion Conference, pp. 395–415, 1989.

[3] F. Lee, “High-frequency quasi-resonant converter technologies,” in Pro-ceedings of the IEEE, vol. 76, pp. 377–390, April 1988.

[4] W. Tabisz and F. Lee, “Zero-voltage-switching multiresonant technique-a novel approach to improve performance of high-frequency quasi-resonant converters,” IEEE Transactions on Power Electronics, vol. 4,pp. 450–458, Oct. 1989.


1406

0 50 100 150 200−5

0

5


Vo

ltag

e [V

]

0 50 100 150 200

−0.2

−0.1

0

0.1

0.2

Output Voltage Deviation

time [us]

Vo

ltag

e [V

]

(a) 0.5W to 3.5W load step

0 50 100 150 200−5

0

5


Vo

ltag

e [V

]

0 50 100 150 200

−0.2

−0.1

0

0.1

0.2

Output Voltage Deviation

time [us]

Vo

ltag

e [V

]

(b) 3.5W to 0.5W load step

Fig. 19. Experimental load step transient response with PWM controlleralone. Conditions are for VIN =4V and VOUT,REF =7.3V.

[5] R. Erickson and D. Maksimovic, Fundamentals of Power Electronics.Norwell, MA: (Kluwer Academic Publishers), 2000.

[6] Y. Lee and Y. Cheng, “A 580 khz switching regulator using on-offcontrol,” Journal of the Institution of Electronic and Radio Engineers,vol. 57, no. 5, pp. 221–226, September/October 1987.

[7] J. Rivas, D. Jackson, O. Leitermann, A. Sagneri, Y. Han, and D. Per-reault, “Design considerations for very high frequency dc-dc converters,”in Power Electronics Specialists Conference, 2006. PESC ’06. 37thIEEE, pp. 1–11, 18-22 June 2006.

[8] J. Rivas, R. Wahby, J. Shafran, and D. Perreault, “New architectures forradio-frequency dc/dc power conversion,” IEEE Transactions on PowerElectronics, vol. 21, pp. 380–393, March 2006.

[9] R. C. Pilawa-Podgurski, A. D. Sagneri, J. M. Rivas, D. I. Anderson,and D. J. Perreault, “Very high frequency resonant boost converters,” inPower Electronics Specialist Conference Proceedings, June 2007.

[10] J. M. Rivas, ”Radio Frequency dc-dc Power Conversion”. PhD thesis,Dept. of Electrical Engineering and Computer Science, MassachusettsInstitute of Technology, September 2006.

[11] A. D. Sagneri, “Design of a very high frequency dc-dc boost converter,”Master’s thesis, Massachusetts Institute of Technology, Cambridge, MA,February 2007.

[12] N. O. Sokal, “Class-E RF Power Amplifiers,” QEX, pp. 9–20, Jan/Feb2001.

[13] W. Everitt and G. Anner, Communications Engineering. New York:(McGraw-Hill), third ed., 1956.

[14] Y. Han and D. J. Perreault, “Analysis and design of high efficiencymatching networks,” IEEE Transactions on Power Electronics, vol. Vol.21, No. 5, pp. pp. 1484–1491, Sept. 2006.

[15] H. Koizumi, I. M., and M. S., “Class E2 dc/dc converter with secondharmonic resonant class e inverter and class e rectifier,” in Thirs AnnualApplied Power Electronics Conference Proceedings, pp. 1012–1018,1994.

[16] M. Iwadare, S. Mori, and K. Ikeda, “Even harmonic resonant class etuned power amplifier without rf choke,” in Electronics and Communi-cations in Japan, vol. 79, pp. 23–30, Jan. 1996.

[17] J. Hu, “Design of a low-voltage low-power dc-dc hf converter,” Master’sthesis, Dept. of Electrical Engineering and Computer Science, Mas-sachusetts Institute of Technology, 2008.

[18] J. R. Warren, III, K. A. Rosowski, and D. J. Perreault, “Transistor se-lection and design of a VHF dc-dc power converter,” IEEE Transactionson Power Electronics, vol. Vol.23 No. 1, January 2008.


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