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Stuart SutherlandVerilog design consultant, specializing in Verilog training
Hardware design engineer with a Computer Science degreeHeavily involved with Verilog since 1988
Member of IEEE 1364 Verilog standards group since 1993Co-chair of Verilog PLI task forceTechnical editor of PLI sections of the IEEE 1364 Verilog Language Reference Manual
Member of the Accellera committee defining SystemVerilogInvolved with the formation of the “Verilog++” committee that started SystemVerilogTechnical editor of SystemVerilog Reference Manual
SystemVerilog is an extension of the IEEE 1364 Verilog-2001 standard
Adds C and C++ language constructs to VerilogAdds interfaces to VerilogAdds assertions to VerilogAdds many other features to Verilog
SystemVerilog is the next generation of the Verilog standard!Gives Verilog a much higher level of modeling abstractionGives Verilog new capabilities for design verificationExpected to be adopted by the IEEE in the next revision to the 1364 Verilog standard
Engineers must design more gates in less timethan ever before
Requires designing at a more abstract levelRequires using new verification techniquesRequires system level design/verification languages
But…Hardware is still built with silicon!
System level designs must be implemented in gatesThe logic gates must still meet timing, area, EMF, thermal and other implementation requirementsHDLs, such as Verilog are still part of the design flow!
To show that SystemVerilog is an evolution of VerilogVerilog 1.0 is the IEEE 1364-1995 “Verilog-1995” standard
The first generation of a true Verilog languageBased on the original Verilog HDL created by Gateway Design Automation in 1984
Verilog 2.0 is the IEEE 1364-2001 “Verilog-2001” standardThe second generation of the Verilog languageThe first major enhancement to Verilog since its creation
SystemVerilog 3.x is the Accellera extensions to theVerilog-2001 standard
The third generation of the Verilog languageMany significant enhancements…as will be shown
Accellera is a not-for-profit consortium of:Electronic Design Automation (EDA) design tool vendorsASIC manufacturersSystems companies
Accellera's mission is to:Focus on identifying new EDA standardsAssist in the development of EDA standards and formatsFoster the adoption of new EDA methodologies
Accellera was formed in 2000 through the unification of Open Verilog International and VHDL International
Renown industry experts are defining SystemVerilogSimulation algorithm expertsSynthesis compiler expertsVerification expertsVerilog design engineers and consultantsIEEE 1364 Verilog standard working group members
The IEEE 1364 standards group is the official governing body of the Verilog language
Defined the 1364-1995 “Verilog-1995” standardDefined the 1364-2001 “Verilog-2001” standard
It took the IEEE 5 years to define and ratify Verilog-2001Our design needs are changing much faster
than the IEEE can react!
Accellera is accelerating the IEEE standardization processCan define a de facto standard in months instead of yearsAccellera will donate SystemVerilog to the IEEE to become part of the next IEEE Verilog standard
Accellera’s primary goal is to promote EDA standardsSponsor IEEE standards groups (Verilog, VHDL, SDF...)Think tank for new standards
SystemVerilog development was coordinated with IEEE14 members of the IEEE 1364 Verilog Standards Group also participated on Accellera SystemVerilog committees1364 representatives had official “corporate” voting rights on SystemVerilog, the same as other companies1364 standards meetings often include discussion of what is in SystemVerilog
Accellera plans to turn SystemVerilog over to the IEEE 1364 to integrate into the Verilog standard
Two good ways to extend Verilog...Start from scratch (re-invent the wheel)
First decide how new constructs will be addedInvent the syntax and semantics for each new constructCommittee members debate and debate and debate...Years later, if consensus is reached, extensions are released to EDA companies to implement
Start with proven technologiesLearn from other companies trials and errorsPick the best features from many sourcesSyntax is not as uniform because of many sourcesMuch faster time-to-market than re-inventing the wheel
SystemVerilog is derived from proven technology:SUPERLOG architectural modeling language (Co-design)PSL-Sugar assertions (IBM)ForSpec assertions (Intel)OVL assertion library (Verplex)OpenVERA assertions (Synopsys)OpenVERA hardware verification language (Synopsys)DirectC programming interface (Synopsys)Other donations from several companies (Novas, 0-in, Real Intent,...)
Accellera spent two years integrating these donationsRemoving overlapMaking syntax look like Verilog
SystemVerilog also extends to ability to specify an ending name with endmodule, endinterface, endprimitive, endprogram, endtask, endfunction, endclass, endpropertyand endsequence
The ending name must match the name used with the corresponding beginning of the code block
module my_chip (...);...task get_data (...)
...endtask: get_data
endmodule: my_chip
Specifying ending names helps to make large blocks of code more readable, but does not affect functionality in any way
In Verilog, there is no simple way to fill a vector with all 1’sparameter N = 64;reg [N-1:0] data_bus;data_bus = 64’hFFFFFFFFFFFFFFF; //set all bits of data_bus to 1
reg [N-1:0] data_bus;data_bus = x’1; //set all bits of data_bus to 1
SystemVerilog enhances assignments of a literal valueAll bits of a vector can be filled with a literal 1-bit value
x’0 fills all bits on the left-hand side with 0x’1 fills all bits on the left-hand side with 1x’z fills all bits on the left-hand side with zx’x fills all bits on the left-hand side with x
vector width must be hard coded
could also use operations, such as replicate or invert
In Verilog, the term “reg” confuses new usersThe name would seem to infer a hardware registerIn reality, reg is a general purpose variable that can represent either combinational logic or sequential logic
SystemVerilog’s 4-state logic type is identical to a reglogic is a more intuitive name for new Verilog users
Historically, logic comes from the Superlog language, where it had different semantic rules than regSystemVerilog made the rules equivalent for backward compatibility with existing Verilog modelsVerilog also has equivalent keywords, (e.g. wire and tri)that historically once had different semantics
Verilog uses 4-state logicMost hardware can be modeled with 2-state logicSynthesis mostly only considers 2-state values
The SystemVerilog 2-state bit typeModels RTL logic the way synthesis sees the logicAllows easy mixing of 2-state and 4-state in the same designUses the same rules with all SystemVerilog tools
reg mode;
always @(a, b, mode)if (mode)
y = a + b;else
y = a - b;
Synthesis does not take into consideration that mode could have an X or Z value
Verilog restricts the data types that can be connected to module ports
Only net types on the receiving sideNets, regs or integers on the driving sideChoosing the correct type frustrates Verilog modelers
SystemVerilog removes all restrictions on port connectionsAny data type on either side of the portReal numbers (floating point) can pass through portsArrays can be passed through portsStructures can be passed through ports
SystemVerilog enhances Verilog tasks and functionsStatic and automatic storage enhancementsDefault directions for formal argumentsDefault data types for formal argumentsPassing arrays and structures as argumentsPassing arguments by namePassing arguments by reference (pointers)Function outputs and inoutsC-like function returnsVoid functionsImplicit statement grouping
Static and Automatic StorageIn Tasks and Functions
Verilog-1995 has static tasks and functionsAll storage is allocated once and shared by all calls
Verilog-2001 adds automatic tasks and functionsAll storage is allocated each time the block is enteredCan be called while a previous call is still executing(allows re-entrant tasks and recursive functions)
SystemVerilog adds:Static storage in an automatic task or functionAutomatic storage in a static task or function
RTL enhancementsMake it easier to model for synthesisRemove model ambiguityReduce pre- and post-simulation mismatchesAllow all tools to generate warnings if model does not match designer’s intent
Just a few of the enhancements in this category will be shown
The always procedure is a general purpose procedureUsed to model combinational logic, latched logic, sequential logicand testbench logicSoftware tools must “infer” (guess ) what type of hardware an engineer intended based on procedure content and context
always @(posedge clock)begin
if (mode) q1 = a + belse q1 = a - b;q2 <= q1 | (q2<< 2);q2++;
The always_comb procedure models combinational logicalways_comb
if (!mode)y = a + b;
elsey = a - b;
always_comb is different from a normal always procedureThe sensitivity list is inferred
Includes every variable read by the procedureVariables on the left-hand side of assignments cannot be written to by any other procedureThe procedure is automatically triggered at time zero
Ensures the outputs are consistent with the inputs at time zero
no sensitivity list
Tools can know the designer’s intent, and verify that the code models combinational behavior
contents must follow synthesis requirements for combinational logic
The always_latch procedure models combinational logic with storage
always_latchif (enable) q <= d;
no sensitivity list
Tools can know the intent, and verify the code models latched behavior
always_latch is different from a normal always procedureHas same required rules as always_comb
The sensitivity list is inferred (same rules as always_comb)Variables on the left-hand side of assignments cannot be written to by any other procedureThe procedure is automatically triggered at time zero
Software tools may apply different additional checksE.g. don’t need to check that all LHS variables are updated
Tools can know the intent, and verify the code models sequential logic behavior
always_ff is different from a normal always procedureThe sensitivity list must specify an edge for each signalNo event controls are permitted within the procedure
Verilog defines that if—else—if decisions and case statements execute with priority encoding
In simulation, only the first matching branch is executedSynthesis will infer parallel execution based on context
Parallel evaluation after synthesis may causes a mismatch inpre-synthesis and post-synthesis simulation results
SystemVerilog adds unique and priority keywords:Priority-encoded or parallel evaluation can be explicitly defined for both simulation and synthesisSoftware tools can warn if case or if—else decisions do not match the behavior specified
In SystemVerilog allows the designer to specify his intentCan eliminate any ambiguity between simulation interpretations and synthesis implementationsSoftware tools can issue warnings if the code might not behave according to the stated intent
always_combbeginnext_state = state; //default for each branch belowunique case(state)red: if (sensor = 1) next_state = green;yellow: if (yellow_downcnt = 0) next_state = red;green: if (green_downcnt = 0) next_state = yellow;
The ++ and -- operators behave as a blocking assignment!A parallel process may read the value of an incremented/decremented variable before or after the change
Guideline: Never use ++ and -- in logic that occurs on a clock edge!
always_ff @(posedge clock) case (state)
HOLD: if (count == MAX)...
always_ff @(posedge clock) if (reset_n) count <= 0;else count++;
//same as count = count + 1;
Is count sampled before or after it is incremented?
SystemVerilog’s enumerated types can be abstract, as in CDefault’s to an int data type (2-state logic)Only specify the names of the enumerated valuesFirst name default’s to a value of 0, second name to 1, ...
enum {WAIT, LOAD, READY} states;
enum bit [2:0] {WAIT=3’b001, LOAD=3’b010, READY=3’b100} states;
Optionally, SystemVerilog enumerated types can be defined with hardware implementation characteristics
Can specify a different data typeCan specify a specific vector sizeCan specify specific values for each name
The implementation of enumerated types is not complete without their “methods”
<enum_variable>.first — returns the value of the first member in the enumerated list<enum_variable>.last — returns the value of the last member in the enumerated list<enum_variable>.next(<N>) — returns value of the Nth next value in the enumerated list<enum_variable>.prev(<N>) — returns value of the Nth previous value in the enumerated list<enum_variable>.num — returns the number of elements in the enumerated list<enum_variable>.name — returns the name of the current value in the enumeration variable
if (synched) next_state = State.next; // increment by 1 stateelse (next_state = State.prev(2); // decrement by 2 states$display("Next state will be %s (%b)", NextState.name, next_state);
Data encapsulation enhancementsBundle several discrete signals or data togetherTransfer whole groups of signals or data at onceAllow operations on a bundle of signals or data
Just a few of the enhancements in this category will be shown
Modules can only see the signals in the modport being usedinterface chip_bus (input bit clk, test_clk);bit request, grant, ready;logic [63:0] address, data;logic [7:0] opcode; modport master (output request, address,
Tasks and functions can be declared within interfacesCan represent complex bus transactionsModules can be modeled at an abstract level
Can execute transactions without referencing specific signals interface chip_bus (input bit clk);bit request, grant, ready;logic [63:0] address, data;task Read (...);
Unpacked arrays can be assigned using a list of values in { }braces for each array dimension (similar to C)int d [0:1][0:3] = { {7,3,0,5},{2,0,1,6} };
The { } braces are the C array initialize tokens, not the Verilog concatenate operator!
Must have a set of braces for each array dimension
d[0][0] is initialized to 7d[0][1] is initialized to 3d[0][2] is initialized to 0d[0][3] is initialized to 5d[1][0] is initialized to 2d[1][1] is initialized to 0d[1][2] is initialized to 1d[1][3] is initialized to 6
int d [0:1][0:3] = { 2{7,3,0,5} }; d[0][0] is initialized to 7d[0][1] is initialized to 3d[0][2] is initialized to 0d[0][3] is initialized to 5d[1][0] is initialized to 7d[1][1] is initialized to 3d[1][2] is initialized to 0d[1][3] is initialized to 5
A replicate operator can be used to fill unpacked arrays
A “packed array” is an array of sub fields within a vectorCan only use be 1-bit data types: reg, logic, bit, wire, ...A Verilog “vector” is a 1-dimensional packed array
a 2-dimensional “packed array” of logic variablesreg [3:0][7:0] a;
Can be used to bundle several variables into one objectCan assign to individual signals within the structureCan assign to the structure as a wholeCan pass structures through ports and to tasks or functions
An array is a collection of elements that are all the same type and size;A structure is a collection of elements that can be different types and sizes
SystemVerilog provides a compilation unit name spaceAllows declarations of variables, functions, etc. outside of modulesExternal declarations are visible to all code compiled at same timeExternal names can be directly referenced as $unit.<name>
bit reset; //external reset
typedef struct {int i0, i1;bit [15:0] opcode;
} instruction_t;
module top; //instance of top-level moduleinstruction_t out, in;...register i1 (out, in, clock, reset);
endmodule
module register (output instruction_t q, ...)...always @(posedge clk or posedge $unit.reset)
External variable
External user-defined type
When a name is referenced:• First, follow Verilog search rules• Second, look in $unit
SystemVerilog adds packages to the Verilog HDLUsed to contain declarations that are used in many models
Modules can directly reference declarations in a packageModules can import specific declarations from a packageModules can import only what is needed from a package
package definitions;typedef struct {
int i0, i1;bit [15:0] opcode;
} instruction_t;endpackage
module register (output definitions::instruction_t q, ...)...
module top; //instance of top-level moduleimport definitions::*; // import whatever is needed from packageinstruction_t out, in;...
Packages can contain net and variable declarations, task and function definitions, type definitions, class definitions, coverage definitions, operator overload definitions, ...
Abstract modeling enhancementsModel more functionality with fewer lines of codeMore like programming than register transfer level codeMight not be synthesizable (today)Important for Behavioral Modeling and Bus Functional Modeling
Just a few of the enhancements in this category will be shown
Verilog has hardware-centric data typesIntended to represent real connections in a chip or systemAt the system and RTL level, models only need 2-state logic
Tri-state busses are the only place 4-state logic is needed
SystemVerilog adds several new data typesC-like data types create a bridge between C and Verilog
byte — an 8-bit 2-state integershortint — a 16-bit 2-state integer, similar to a C shortint — a 32-bit 2-state integer, similar to a C intlongint — a 64-bit 2-state integer, similar to a C longlongshortreal — a 32-bit single-precision floating point, the same as a C floatvoid — no value (used for function returns)
Verilog uses the disable statement as a go-toCauses a named group of statements to jump to the end
SystemVerilog adds the C language jump statements:break — works like the C breakcontinue — works like the C continuereturn(<value>) — return from a non-void functionreturn — return from a task or void function
task send_packet(...);if (^data == 1’bx) begin
$display(“Error...”);return; //abort task
end...
endtask
function real absolute(input real a);if (a >= 0.0) return(a);else return(-a);
endfunction
The return statement allows terminating a task or function before reaching the end
Verilog uses the Programming Language Interface (PLI) to allow Verilog code to call C language code
Powerful capabilities such as traversing hierarchy, controlling simulation, modifying delays and synchronizing to simulation timeDifficult to learnToo complex of an interface for many types of applications
SystemVerilog adds a “Direct Programming Interface” (DPI)Verilog code can directly call C functionsC functions can directly call Verilog tasks and functionsNo PLI is needed for these direct function calls
Cannot do everything the PLI can doCan do many things more easily than the PLIIdeal for interfacing to bus-functional models written in C
Sequences can be defined outside of the design models, and “bound” to the design
An assertion can be bound to a specific instance of a module or interfaceAn assertion can be bound to all instances of a module or interface
Binding assertions enables “black box” verificationThe verification engineer defines assertions outside of the design modelsThe verification engineer does not need to change the model in any way
Verilog has no special clock semantics for verificationVerification engineers must define special test clocks to avoid race conditions with the design clock
SystemVerilog adds a special “clocking domain” constructSpecifies a test “input skew” and “output skew”
Ensures verification events are offset from the design clockAllows the test bench to use the same clock(s) as the design, without having race conditions with the design
Verilog uses hardware vector types to store stringsEach character is stored as its 8-bit ASCII codeNo convenient way to work with the string values
reg [31*8:1] myString;myString = “hello world”;
string myString = “hello world”;
SystemVerilog provides a special built-in string data typeStored as a dynamic array — length changes with size of stringBuilt-in methods are used to work with the string
SystemVerilog includes built-in class definitions to synchronize verification activity
SemaphoresRepresents a bucket with a fixed number of keysBuilt-in class methods used to check keys in and outProcess can check out one or more keys, and return them laterIf not enough keys are available, the process execution stops and waits for keys before continuing (gives mutually exclusive control)
MailboxesRepresents a FIFO to exchange messages between processesBuilt-in methods allow adding a message or retrieving a messageIf no message is available, the process can either wait until a message is added, or continue and check again later
Verilog uses the Programming Language Interface (PLI) to allow Verilog code to call C language code
Powerful capabilities such as traversing hierarchy, controlling simulation, modifying delays and synchronizing to simulation timeDifficult to learnToo complex of an interface for many types of applications
SystemVerilog adds a “Direct Programming Interface” (DPI)Verilog code can directly call C functionsC functions can directly call Verilog functionsNo PLI is needed for these direct function calls
Cannot do everything the PLI can doCan do many things more easily than the PLIIdeal for interfacing to bus-functional models written in C
There are many more enhancements to Verilog that were not covered in this presentation
Tagged unionsStatic and automatic variablesConst constantsNested modulesCoverageAssertion API, coverage API, extensions to Verilog VPIAnd many more enhancements...
Backward compatibility was top priority during the development of SystemVerilog
The SystemVerilog committee integrated donations from several languages
Donations were reviewed construct by constructConstructs were modified as needed to integrate with VerilogGoal was for existing Verilog models to run with no changes
Only compatibility issue is new keywordsSystemVerilog adds several new keywords to Verilog
New keywords may conflict with signal names in existing Verilog models
Keyword conflict can be handled by parsers and compilersInvocation options, compiler directives, ...
SystemVerilog is an evolution of the Verilog-2001 standardNew levels of modeling abstraction to handle large designsBridges the canyon between system design and implementation
Accellera is developing the SystemVerilog standardA working standard can be completed in months instead of years
Sutherland HDL offers Advanced SystemVerilog Training2-state modeling techniques with SystemVerilog’s new data typesWorking with structures, unions and compound arraysCorrectly using new procedures and operators, and avoiding “gotchas”Design verification using assertions, classes and program blocksThe power of interfaces
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