AMIQ www.amiq.com VERISSIMO SystemVerilog Testbench Linter Overview SystemVerilog is a rich object–oriented programming language that provides powerful constructs and a high level of programming flexibility. Such capabilities meet the needs of today’s complex design and verification requirements, but at the same time introduce new challenges in code development. For example, the possibility of implementing the same functionality in multiple ways may impact the simulation performance or lead to unexpected behavior. The SystemVerilog compiler checks whether the source code follows the Language Reference Manual (LRM) rules. Thus, the compiler captures only language specific syntax and semantic errors. Therefore, the absence of compilation errors does not give any indication of code reliability and maintainability, or that the best coding practices have been applied. Nor it implies that compliancy with the recommended methodologies has been met. The Verissimo SystemVerilog testbench linter is a coding guideline and verification methodology compliance checker that enables engineers to perform an additional audit of their testbenches. With this tool they can check whether the code is free of language pitfalls and semantic or style issues, and compliant with the appropriate methodologies. Verissimo can be customized to check specific corporate coding guidelines to ensure consistency and best practices in code developing at the company level. Types of Checks The Verissimo linter performs a thorough static analysis of the source code. It checks the following areas: Suspicious language usage such as non-standard syntax and problematic delta cycle usage or system calls. Semantic issues that are not caught by the SystemVerilog compiler; for example, an overridden non-virtual method, which will likely result in an unexpected behavior. Improper styling like confusing declaration order and naming conventions. Verification methodology violations such as inappropriate object creation, missing calls, and constructs that should be avoided. Built-in Repository of Generic SystemVerilog and UVM Checks AMIQ’s Verissimo provides a comprehensive library of generic SystemVerilog and Universal Verification Methodology (UVM) checks. The UVM compliance-checking rules are written in accordance with the verification methodology guidelines from the UVM World (www.uvmworld.org). Users can create custom rule sets by selecting from the hundreds of built-in checks in the linter’s library, those that correspond to their requirements. Custom Checks Users can create new rules according to their requirements, by using a dedicated Java application programming interface (API). The API comes with the linter and allows the user to query the linter’s internal database to find the relevant information. Visualizing and Analyzing the Results Verissimo runs both in batch and graphical user interface (GUI) modes. It includes a report generator that can be used to save the results of a linting session as a text or HTML file. The checks can be layered on different levels of severity such as error, warning, and informative. Users can use pragmas that are embedded in the code, to turn the checks ON/OFF or change their severity. They can do this individually or by category, as well as by line range, file, and directory. The linter also allows users to annotate rules and share the notes with the team. The Verissimo linter integrates with the Design and Verification Tools (DVT) integrated development environment (IDE). Users can perform linting and then visualize the results in the DVT GUI, which offers an elegant way to read and understand the error and warning messages. With DVT, the messages can be easily sorted and filtered by category, severity, and source location. In addition, the DVT’s code navigation features such as hyperlinks, allow the users to jump instantly to the problematic source line to fix the issue flagged by the linter. Then, all that remains to do is to run a new linting session to validate the fix.