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AMIQ www.amiq.com VERISSIMO SystemVerilog Testbench Linter Overview SystemVerilog is a rich object–oriented programming language that provides powerful constructs and a high level of programming flexibility. Such capabilities meet the needs of today’s complex design and verification requirements, but at the same time introduce new challenges in code development. For example, the possibility of implementing the same functionality in multiple ways may impact the simulation performance or lead to unexpected behavior. The SystemVerilog compiler checks whether the source code follows the Language Reference Manual (LRM) rules. Thus, the compiler captures only language specific syntax and semantic errors. Therefore, the absence of compilation errors does not give any indication of code reliability and maintainability, or that the best coding practices have been applied. Nor it implies that compliancy with the recommended methodologies has been met. The Verissimo SystemVerilog testbench linter is a coding guideline and verification methodology compliance checker that enables engineers to perform an additional audit of their testbenches. With this tool they can check whether the code is free of language pitfalls and semantic or style issues, and compliant with the appropriate methodologies. Verissimo can be customized to check specific corporate coding guidelines to ensure consistency and best practices in code developing at the company level. Types of Checks The Verissimo linter performs a thorough static analysis of the source code. It checks the following areas: Suspicious language usage such as non-standard syntax and problematic delta cycle usage or system calls. Semantic issues that are not caught by the SystemVerilog compiler; for example, an overridden non-virtual method, which will likely result in an unexpected behavior. Improper styling like confusing declaration order and naming conventions. Verification methodology violations such as inappropriate object creation, missing calls, and constructs that should be avoided. Built-in Repository of Generic SystemVerilog and UVM Checks AMIQ’s Verissimo provides a comprehensive library of generic SystemVerilog and Universal Verification Methodology (UVM) checks. The UVM compliance-checking rules are written in accordance with the verification methodology guidelines from the UVM World (www.uvmworld.org). Users can create custom rule sets by selecting from the hundreds of built-in checks in the linter’s library, those that correspond to their requirements. Custom Checks Users can create new rules according to their requirements, by using a dedicated Java application programming interface (API). The API comes with the linter and allows the user to query the linter’s internal database to find the relevant information. Visualizing and Analyzing the Results Verissimo runs both in batch and graphical user interface (GUI) modes. It includes a report generator that can be used to save the results of a linting session as a text or HTML file. The checks can be layered on different levels of severity such as error, warning, and informative. Users can use pragmas that are embedded in the code, to turn the checks ON/OFF or change their severity. They can do this individually or by category, as well as by line range, file, and directory. The linter also allows users to annotate rules and share the notes with the team. The Verissimo linter integrates with the Design and Verification Tools (DVT) integrated development environment (IDE). Users can perform linting and then visualize the results in the DVT GUI, which offers an elegant way to read and understand the error and warning messages. With DVT, the messages can be easily sorted and filtered by category, severity, and source location. In addition, the DVT’s code navigation features such as hyperlinks, allow the users to jump instantly to the problematic source line to fix the issue flagged by the linter. Then, all that remains to do is to run a new linting session to validate the fix.
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VERISSIMO SystemVerilog Testbench Linter - ISS Group · PDF fileAMIQ VERISSIMO SystemVerilog Testbench Linter Overview SystemVerilog is a rich object–oriented programming language

Mar 06, 2018

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Page 1: VERISSIMO SystemVerilog Testbench Linter - ISS Group · PDF fileAMIQ VERISSIMO SystemVerilog Testbench Linter Overview SystemVerilog is a rich object–oriented programming language

AMIQ www.amiq.com

VERISSIMO SystemVerilog Testbench Linter

OverviewSystemVerilog is a rich object–oriented programming language that provides powerful constructs and a high level of programming flexibility. Such capabilities meet the needs of today’s complex design and verification requirements, but at the same time introduce new challenges in code development. For example, the possibility of implementing the same functionality in multiple ways may impact the simulation performance or lead to unexpected behavior.

The SystemVerilog compiler checks whether the source code follows the Language Reference Manual (LRM) rules. Thus, the compiler captures only language specific syntax and semantic errors. Therefore, the absence of compilation errors does not give any indication of code reliability and maintainability, or that the best coding practices have been applied. Nor it implies that compliancy with the recommended methodologies has been met.

The Verissimo SystemVerilog testbench linter is a coding guideline and verification methodology compliance checker that enables engineers to perform an additional audit of their testbenches. With this tool they can check whether the code is free of language pitfalls and semantic or style issues, and compliant with the appropriate methodologies. Verissimo can be customized to check specific corporate coding guidelines to ensure consistency and best practices in code developing at the company level.

Types of ChecksThe Verissimo linter performs a thorough static analysis of the source code. It checks the following areas:

� Suspicious language usage such as non-standard syntax and problematic delta cycle usage or system calls.

� Semantic issues that are not caught by the SystemVerilog compiler; for example, an overridden non-virtual method, which will likely result in an unexpected behavior.

� Improper styling like confusing declaration order and naming conventions.

� Verification methodology violations such as inappropriate object creation, missing calls, and constructs that should be avoided.

Built-in Repository of Generic SystemVerilog and UVM ChecksAMIQ’s Verissimo provides a comprehensive library of generic SystemVerilog and Universal Verification Methodology (UVM) checks. The UVM compliance-checking rules are written in accordance with the verification methodology guidelines from the UVM World (www.uvmworld.org).

Users can create custom rule sets by selecting from the hundreds of built-in checks in the linter’s library, those that correspond to their requirements.

Custom Checks

Users can create new rules according to their requirements, by using a dedicated Java application programming interface (API). The API comes with the linter and allows the user to query the linter’s internal database to find the relevant information.

Visualizing and Analyzing the ResultsVerissimo runs both in batch and graphical user interface (GUI) modes. It includes a report generator that can be used to save the results of a linting session as a text or HTML file.

The checks can be layered on different levels of severity such as error, warning, and informative. Users can use pragmas that are embedded in the code, to turn the checks ON/OFF or change their severity. They can do this individually or by category, as well as by line range, file, and directory. The linter also allows users to annotate rules and share the notes with the team.

The Verissimo linter integrates with the Design and Verification Tools (DVT) integrated development environment (IDE). Users can perform linting and then visualize the results in the DVT GUI, which offers an elegant way to read and understand the error and warning messages. With DVT, the messages can be easily sorted and filtered by category, severity, and source location.

In addition, the DVT’s code navigation features such as hyperlinks, allow the users to jump instantly to the problematic source line to fix the issue flagged by the linter. Then, all that remains to do is to run a new linting session to validate the fix.

Page 2: VERISSIMO SystemVerilog Testbench Linter - ISS Group · PDF fileAMIQ VERISSIMO SystemVerilog Testbench Linter Overview SystemVerilog is a rich object–oriented programming language

Figure 1: The Verissimo Testbench Linter Overview

AMIQ www.amiq.com

About AMIQAMIQ focuses on adding value to the design and verification domains through its EDA proprietary tools and consulting expertise spanning various design and verification projects worldwide. Founded in 2003, AMIQ has today two business lines: design and verification tool development (AMIQ EDA) and ASIC verification consulting services (AMIQ Consulting) . AMIQ serves customers around the world and strives to deliver high quality solutions and customer service responsiveness, while maintaining a friendly and flexible environment.

SummaryThe Verissimo testbench linter signals SystemVerilog improper language, semantics, and styling usage, as well as verification methodology violations. It can be customized to meet the demands of small teams up to larger verification groups and global companies and helps improve testbench code reliability, functionality, and maintainability. Ultimately, Verissimo is a tool that allows companies to implement the best coding practices in verification.

The DVT IDE increases the speed and quality of code development and simplifies the maintenance of reusable libraries and legacy code. The seamless integration between the Verissimo testbench linter as a code analysis tool and the DVT IDE as a code development tool, further improves the verification productivity and quality. It also contributes to decreasing the significant costs associated with code maintenance.

Contact AMIQSupport & Evaluation: [email protected]: [email protected]: www.dvteclipse.com; www.amiq.com

Rule ExamplesSystemVerilog RulesCategory: SystemVerilog Check Rule: Tasks defined outside classes must be explicitly declared automatic or staticSeverity: ERROR

Category: SystemVerilog Semantic CheckDescription: Assignment from 4 State to 2 State Must include X, Z check. Severity: ERROR

Category: SystemVerilog Semantic CheckRule: Declared method default values must exactly match the extern implementation default values. Severity: WARNING

Category: Style CheckDescription: All class member variables must be javadoc style commented with a single line comment.Severity: INFO

UVM RulesCategory: UVM CheckDescription: Verify that all sequencers are properly instantiated in ACTIVE agents. Note: Properly instantiated means that they should be created using class_name::type_id::create() method inside the build() function. Severity: ERROR

Copyright 2012 AMIQ EDA S.R.L. All rights reserved. The information contained herein is subject to change without notice. Verissimo and DVT are trademarks of AMIQ EDA S.R.L. All others are properties of their respective holders.

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