FPCCD Flavor Tagging C. Calancha 1 , A. Dubey 2 , H. Ikeda 3 , A. Ishikawa 2 , S. Ito 2 , E. Kato 2 , A. Miyamoto 1 , T. Mori 4 , H. Sato 5 , T. Suehara 6 , Y. Sugimoto 1 , J. Strube 2 , H. Yamamoto 2 1 High Energy Accelerator Research Organization 2 Tohoku University 3 Institute of Space and Astronautical Science, JAXA 4 University of Tokyo 5 Shinshu University 6 Kyushu University
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FPCCD Flavor Tagging C. Calancha1, A. Dubey2, H. Ikeda3, A. Ishikawa2, S. Ito2 , E. Kato2,
A. Miyamoto1, T. Mori4, H. Sato5, T. Suehara6, Y. Sugimoto1, J. Strube2,
H. Yamamoto2
1High Energy Accelerator Research Organization 2Tohoku University
3Institute of Space and Astronautical Science, JAXA 4University of Tokyo 5Shinshu University 6Kyushu University
Introduction: Vertex detector
ILC beams:
resolution (µm) # BX readout
layer FPCCD CMOS FPCCD CMOS
1 1.4 2.8 1312 90
2 1.4 6.0 1312 18
3 2.8 4.0 1312 180
4 2.8 4.0 1312 180
5 2.8 4.0 1312 180
6 2.8 4.0 1312 180
ILD Vertex Detector:
3 double layers
Introduction: Flavor Tagging
physics requirements
Excellent flavor tagging requirements of b and c jets put a tight constraint on
the spatial resolution and material budget of the vertex detector
Setup
● CMOS + DBD tracking
● CMOS + FPCCD tracking
● FPCCD + FPCCD tracking
2000 Events
Z → bb, cc, uds @ 250 GeV, including
one bunch train of pair background
LCFIPlus trained on 14000 events without
background
layer FPCCD CMOS
1 1312 90
2 1312 18
3 1312 180
4 1312 180
5 1312 180
6 1312 180
# of BX per readout
Digitization
Sensitive layer: 15 µm
Total thickness: 50 µm
Pixel size:
5 µm x 5 µm
10 µm x 10 µm
Digitization of GEANT4 energy depositions based on
track path in material and Landau distribution
Digitization for both signal and background in FPCCD
● FPCCD TrackFinder outperforms current DBD tracking
● Time stamping is an important ingredient in background
suppression
Degradation by pairs
Techology tracking pair
s
b-tag purity @
80%
efficiency
c-tag purity @
60% efficiency
CMOS DBD - 82.8% 56.4%
CMOS DBD + 30.4% 20.0%
CMOS FPCCD TF - 83.0% 58.1%
CMOS FPCCD TF + 40.8% 22.8%
FPCCD FPCCD TF - 85.5% 63.9%
FPCCD FPCCD TF + 21.5% 18.7%
Pt-distribution of tracks in b-jets FPCCD vertex detector, FPCCDTrackFinder
Track requirement: #SIT hit >= 1 || TPC hit >= 10 || |cosθ| > 0.9
→ most tracks from pairs don’t have SIT or TPC hits
→ signal tracks with coverage |cosθ| > 0.9 don’t have those hits, either
red: all tracks
blue: tracks with purity > 0.75
black: tracks with purity ∈ [0, 0.75]
b-tag purity: 85.5%
@ 80% efficiency
b-tag purity: 84.1%
@ 80% efficiency
Pt-distribution of tracks in b-jets
with pair background
red: all tracks
blue: tracks with purity > 0.75
black: tracks with purity ∈ [0, 0.75]
purple: pair background
b-tag purity: 21.5%
@ 80% efficiency
b-tag purity: 67.8%
@ 80% efficiency
Pair background increases number of tracks with low purity
Track requirements reduce pair background, but not these low quality tracks
Performance with pairs after track
selection
FPCCD CMOS
Track requirement recovers largely performance without pair background
CMOS advantage comes from time stamping capability
disclaimer: LCFI+ performance in
forward region not optimized,
background not overlaid in FTD
Flavor Tagging Performance
Summary
Technology Tracking pairs Track
Requirement
b-tag purity
@ 80% effficiency
c-tag purity
@ 60% effficiency
CMOS DBD - - 82.8% 56.4%
CMOS DBD + - 30.4% 20.0%
CMOS FPCCD - - 83.0% 58.1%
CMOS FPCCD - + 82.9% 57.4%
CMOS FPCCD + - 40.8% 22.8%
CMOS FPCCD + + 77.6% 49.4%
FPCCD FPCCD - - 85.5% 63.9%
FPCCD FPCCD - + 84.1% 65.5%
FPCCD FPCCD + - 21.5% 18.7%
FPCCD FPCCD + + 67.8% 41.6%
CPU and Memory use
Tracking Algorithm
CPU time (s)
Memory
Technology pairs Silicon Full (GB / evt)
CMOS DBD - 0.2 1.1 408.7
CMOS DBD + 342.0 6.8 561.5
CMOS FPCCD TF - 7.2 1.0 619.5
CMOS FPCCD TF + 34.0 3.0 709.6
FPCCD FPCCD TF - 5.6 1.0 623.0
FPCCD FPCCD TF + 407.6 27.7 2276.0
Values are mean of 2000 events of Z → bb at 250 GeV
Code Development
● FPCCD code is running in Coverity Code
Analyzer o reports on memory leaks: new without delete o checks for data corruption:int x[3]; int y=x[3]; o http://coverity.cern.ch/ needs CERN account
● FPCCD code is running in Intel VTunes
Suite o reports bottlenecks in CPU, Memory consumption
o https://twiki.cern.ch/twiki/bin/view/Openlab/IntelTools