Outline • Introduction • CMOS devices • CMOS technology • CMOS logic structures • CMOS sequential circuits • CMOS regular structures
Jan 13, 2016
Outline
• Introduction• CMOS devices• CMOS technology• CMOS logic structures• CMOS sequential circuits• CMOS regular structures
CMOS logic structures
• CMOS logic: “0” and “1”• The MOST - a simple switch• The CMOS inverter• The CMOS pass gate• Simple CMOS gates• Complex CMOS gates
CMOS logic: “0” and “1”
• Logic circuits process Boolean variables
• Logic values are associated with voltage levels:– VIN > VIH “0”
– VIN < VIL “0”
• Noise margin:– NMH=VOH-VIH
– NML=VIL-VOL
"1"
VOH
VOL
"0"
VIH
VIL
Undefinedregion
Noise MarginHigh
Noise MarginLow
+V +V
0 0
Output Input
The MOST - a simple switch
S
D
G
p-sw
itch
A
B
Y
A B Y
0 0 bad 0 (source follower)0 1 good 11 0 ? (high Z)1 1 ? (high Z)
p-switch
n-sw
itch
A
B
YA B Y
0 0 ? (high Z)0 1 ? (high Z)1 0 good 01 1 bad 1 (source follower)
n-switch
S
D
G
MOSFET’s in digital design
• Important characteristics:– It is an unipolar device
• NMOS - charge carrier: electrons• PMOS - charge carrier: holes
– It is a symmetrical device• Source = drain
– High input impedance (Ig=0)• Low standby current in CMOS configuration
– Voltage controlled device with high fan-out
The CMOS inverter
VDD
VSS
A Y
p-sw
itch
VDD
n-sw
itch
VSS
A Y
A Y
0 good 1
1 good 0
The CMOS inverter
0 0.5 1 1.5 2 2.5
0
0.5
1
1.5
2
2.5
Inverter DC transfer characteristic
Slope = -1
Slope = -1
Vou
t (V
)
Vin (V)
Vout=Vin
VDD
VSS
A Y
2.5/0.25
/0.25
The CMOS inverter
n+ diffusion metal p+ diffusion
polysiliconn-well
substratecontact (p+) n-well
contact (n+)
The CMOS pass gate
C
C
A Yp-switch
n-switchYA
C
C
C A Y0 0 ?0 1 ?1 0 good 01 1 good 1
The CMOS pass gate
Regions of operation:“0” to “1” transition
• NMOS:– source follower
– Vgs = Vds always:
• Vout < Vdd-VTN saturation
• Vout > Vdd-VTN cutoff
– VTN > VTN0 (bulk effect)
• PMOS:– current source
– Vout < |VTP| saturation
– Vout > VTP linear
Vdd
in
0 V
out
t
in
0
1
t
out
0
1
Pass gate: 0 => 1 transition
Equivalent for 0 = > 1 transition
out
"Currentsource"
"Sourcefollower"
Vdd
Simple CMOS gates
A
Y
B
A B Y0 0 10 1 11 0 11 1 0
NAND
Simple CMOS gates
A
Y
B
C
NAND 3 inputs
Pul
l dow
n <
=>
3 o
nP
ull u
p <
=>
1 o
n
n
n
n
ppp
n/3
p
"Delay equivalent" inverter
Simple CMOS gates
A
Y
B
C
NAND 3 inputs
n
n
n
ppp
Bulk effect
Stray capacitance
Use transistorsclose to the outputfor critical signals
Simple CMOS gates
Minimumdistance
Sharedsource/drain
diffusions
A
B
C
Bad: high straycapacitance andlarge area
Good: minimumstray capacitaceand small area
Simple CMOS gates
A
Y
B
A B Y0 0 10 1 01 0 01 1 0
NOR
Simple CMOS gates
Y
VDD
E
E
A
Tri-state inverter
E Y0 high Z1 A
Complex CMOS gates
A
B
Y
S
SS Y0 A1 B
Multiplexer
Complex CMOS gates
Exclusive OR
A
B
Y
A B Y0 0 00 1 11 0 11 1 0
Complex CMOS gatesAOI
Y
A
A
B
B
C
C
D
D
PM
OS
act
ivat
ed b
y "0
"N
MO
S a
ctiv
ated
by
"1"
Pul
l up
Pul
l dow
n
(A+B)
(C+D)
(A+B)(C+D) (AB)(CD) AB+CD
(AB)
(CD)
AB + CD AB + CD
The NMOS pull-down => inversion
Complex CMOS gates
00 01 11 10
1 1 1 1
1 0 0 0
0 0 0 0
1 1 1 1
Y
00
01
11
01
AB
CD
00 01 11 10
1 1 1 1
1 0 0 0
0 0 0 0
1 1 1 1
Y
00
01
11
01
AB
CD
Compound gate
PM
OS
act
ivat
ed b
y "0
"N
MO
S a
ctiv
ated
by
"1"
Pul
l up
Pul
l dow
n
Y
A B
D
C
D
C
B
A
D + A B C
D (A + B + C)
Y = D (A + B + C)
Complex CMOS gates
• Can a compound gate be arbitrarily complex?– NO, propagation delay is a strong function of fan-
in:
– FO Fan-out, number of loads connected to the gate:
• 2 gate capacitances per FO + interconnect
– FI Fan-in, Number of inputs in the gate:• Quadratic dependency on FI due to:
– Resistance increase
– Capacitance increase
– Avoid large FI gates (Typically FI 4)
t p a FO a FI a FI 0 1 22
Single-Bit Addition
Half Adder Full Adder
A B Cout S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Ak BkCk-1 Ck Sk
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
A B
S
Cout
A B
C
S
Cout
out
S A B
C A B
out ( , , )
S A B C
C MAJ A B C
For the Sum Sk
If Ak=Bk then Sk=Ck-1 else Sk=Ck-1
For the carryIf Ak=Bk then Ck=Ak=Bk else Ck=Ck-1
17: Adders 28
Full Adder Design I
• Brute force implementation from eqns
out ( , , )
S A B C
C MAJ A B C
ABC
S
Cout
MA
J
ABC
A
B BB
A
CS
C
CC
B BB
A A
A B
C
B
A
CBA A B C
Cout
C
A
A
BB
17: Adders 29
Full Adder Design II
• Factor S in terms of Cout
S = ABC + (A + B + C)(~Cout)
• Critical path is usually C to Cout in ripple adder
SS
Cout
A
B
C
Cout
MINORITY
Complex CMOS gates
A B C
C
B
A
A
B
C
A B C
SUM
A B
B
A
A
B
CARRY
C
A
B
C
CARRY = (A+B)C + AB SUM = (A+B+C)CARRY +ABC
Adder