ELEC3221 Digital IC & Sytems Design Iain McNally ≈ 10 lectures Koushik Maharatna ≈ 12 lectures Basel Halak ≈ 12 lectures 1001 Digital IC & Sytems Design • Assessment 10% Coursework L-Edit Gate Design (BIM) 90% Examination • Books Integrated Circuit Design a.k.a. Principles of CMOS VLSI Design - A Circuits and Systems Perspective Neil Weste & David Harris Pearson, 2011 Digital System Design with SystemVerilog Mark Zwolinski Pearson Prentice-Hall, 2010 1002 Digital IC & Sytems Design Iain McNally Integrated Circuit Design • Content – Introduction – Overview of Technologies – Layout – CMOS Processing – Design Rules and Abstraction – Cell Design and Euler Paths – System Design using Standard Cells – Wider View • Notes & Resources https://secure.ecs.soton.ac.uk/notes/bim/notes/icd/ 1003 History 1947 First Transistor John Bardeen, Walter Brattain, and William Shockley (Bell Labs) 1952 Integrated Circuits Proposed Geoffrey Dummer (Royal Radar Establishment) - prototype failed... 1958 First Integrated Circuit Jack Kilby (Texas Instruments) - Co-inventor 1959 First Planar Integrated Circuit Robert Noyce (Fairchild) - Co-inventor 1961 First Commercial ICs Simple logic functions from TI and Fairchild 1965 Moore’s Law Gordon Moore (Fairchild) observes the trends in integration. 1004
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ELEC
3221
Dig
ital
IC&
Syte
ms
Des
ign
Iain
McN
ally
≈10
lect
ures
Kou
shik
Mah
arat
na
≈12
lect
ures
Base
lHal
ak
≈12
lect
ures
1001
Dig
ital
IC&
Syte
ms
Des
ign
•A
sses
smen
t10
%C
ours
ewor
kL-
Edit
Gat
eD
esig
n(B
IM)
90%
Exam
inat
ion
•Bo
oks
Inte
grat
edC
ircu
itD
esig
n
a.k.
a.Pr
inci
ples
ofC
MO
SV
LSID
esig
n-A
Cir
cuit
san
dSy
stem
sPe
rspe
ctiv
e
Nei
lWes
te&
Dav
idH
arri
s
Pear
son,
2011
Dig
ital
Syst
emD
esig
nw
ith
Syst
emV
eril
og
Mar
kZ
wol
insk
i
Pear
son
Pren
tice
-Hal
l,20
10
1002
Dig
ital
IC&
Syte
ms
Des
ign
Iain
McN
ally
Inte
grat
edC
ircu
itD
esig
n•
Con
tent
–In
trod
ucti
on
–O
verv
iew
ofTe
chno
logi
es
–La
yout
–C
MO
SPr
oces
sing
–D
esig
nR
ules
and
Abs
trac
tion
–C
ellD
esig
nan
dEu
ler
Path
s
–Sy
stem
Des
ign
usin
gSt
anda
rdC
ells
–W
ider
Vie
w
•N
otes
&R
esou
rces
https://secure.ecs.soton.ac.uk/notes/bim/notes/icd/
1003
His
tory
1947
Firs
tTra
nsis
tor
John
Bard
een,
Wal
ter
Brat
tain
,and
Will
iam
Shoc
kley
(Bel
lLab
s)
1952
Inte
grat
edC
ircu
its
Prop
osed
Geo
ffre
yD
umm
er(R
oyal
Rad
arEs
tabl
ishm
ent)
-pro
toty
pefa
iled.
..
1958
Firs
tInt
egra
ted
Cir
cuit
Jack
Kilb
y(T
exas
Inst
rum
ents
)-C
o-in
vent
or
1959
Firs
tPla
nar
Inte
grat
edC
ircu
itR
ober
tNoy
ce(F
airc
hild
)-C
o-in
vent
or
1961
Firs
tCom
mer
cial
ICs
Sim
ple
logi
cfu
ncti
ons
from
TIan
dFa
irch
ild
1965
Moo
re’s
Law
Gor
don
Moo
re(F
airc
hild
)obs
erve
sth
etr
ends
inin
tegr
atio
n.
1004
His
tory
Moo
re’s
Law
Pred
icts
expo
nent
ialg
row
thin
the
num
ber
ofco
mpo
nent
spe
rch
ip.
1965
-197
5D
oubl
ing
Ever
yYe
arIn
1965
Gor
don
Moo
reob
serv
edth
atth
enu
mbe
rof
com
pone
nts
per
chip
had
doub
led
ever
yye
arsi
nce
1959
and
pred
icte
dth
atth
etr
end
wou
ldco
ntin
ueth
roug
hto
1975
.
Moo
rede
scri
bes
his
init
ialg
row
thpr
edic
tion
sas
”rid
icul
ousl
ypr
ecis
e”.
1975
-201
?D
oubl
ing
Ever
yTw
oYe
ars
In19
75M
oore
revi
sed
grow
thpr
edic
tion
sto
doub
ling
ever
ytw
oye
ars.
Gro
wth
wou
ldno
wde
pend
only
onpr
oces
sim
prov
emen
tsra
ther
than
onm
ore
effic
ient
pack
ing
ofco
mpo
nent
s.
In20
00he
pred
icte
dth
atth
egr
owth
wou
ldco
ntin
ueat
the
sam
era
tefo
ran
-ot
her
10-1
5ye
ars
befo
resl
owin
gdu
eto
phys
ical
limit
s.
1005
His
tory
Moo
re’s
Law
atIn
tel1
100,0
00
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00
386
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486 D
X
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ore
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hi
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ertN
oyce
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tory
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re’s
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;a
Self
-ful
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ophe
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ew
hole
indu
stry
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Moo
re’s
Law
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eto
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icat
ion
faci
litie
s.
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er-w
aste
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t
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tkee
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hth
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stly
Cos
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entt
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ildIC
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uble
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prox
imat
ely
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ery
4ye
ars.
Moo
re’s
law
isno
tdea
d(a
tlea
stno
tqui
te),
alth
ough
ther
ear
ew
orri
esth
atbe
low
20nm
,cl
ever
proc
essi
ngre
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edfo
rsm
alle
rtr
ansi
stor
sm
eans
that
cost
per
tran
sist
oris
goin
gup
rath
erth
ando
wn.
How
will
you
futu
reen
gine
ers
incr
ease
the
num
ber
oftr
ansi
stor
s?
2 orth
eIn
tels
1007
1947
1961
Poin
t C
onta
ct tr
ansis
tor
Fairchild
Bip
ola
r R
TL R
S F
lip−
Flo
p
(4 T
ran
sis
tors
)
Se
lf−
fulfillin
g
Pro
ph
ecy
Moore
’s L
aw
(1965)
Moore
’s L
aw
(1975)
Nu
mb
er
of
tra
nsis
tor
ha
s d
ou
ble
d e
ve
ry y
ea
r a
nd
will co
ntin
ue
to
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til 1
97
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mb
er
of
tra
nsis
tors
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le e
ve
ry t
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ye
ars
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e: B
ell
Labs
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e: F
airchild
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00
10
,00
0
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ntiu
m I
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X
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ntiu
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ntiu
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ntiu
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I
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00
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ore
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rvie
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Tech
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gies
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pone
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lar
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sist
ors
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n O
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ce
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l
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gies
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rter
and
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te
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Z
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Z
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rvie
wof
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nolo
gies
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tion
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nbe
real
ized
usin
gon
lyth
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aila
ble
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eR
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ily.2
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eth
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rter
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ialc
ase
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ith
only
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t.2 N
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tes
coul
dbe
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inst
ead
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logi
cfa
mili
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hich
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orto
nly
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gate
s.
2003
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rvie
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gies
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logi
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ter
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eral
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ghsp
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er,n
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atur
atin
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chno
logy
.
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mili
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em
ore
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plex
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cve
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own
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rvie
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ircu
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eple
tion
tran
sist
orac
tsas
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adre
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or.
Res
ista
nce
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ease
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enha
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evic
etu
rns
on,t
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redu
cing
pow
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nsum
ptio
n.
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elo
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tio
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2005
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rvie
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repr
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ons
for
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uits
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ital
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ross
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ross
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ays
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nce
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)
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et
andρ
are
fixed
for
apa
ricu
lar
mas
kla
yer,
the
valu
eth
atis
norm
ally
used
isth
esh
eetr
esis
tanc
e:Rs
=( ρ t
) .
w
l
R=Rs
(l w
)
whe
reRs
issh
eetr
esis
tanc
e0.
1Ω/
for
170nm
thic
kco
pper
Rs
=re
sist
ance
ofa
squa
re(i.
e.w
=l)
soth
eun
itsfo
rRs
are
Ω/
(ohm
spe
rsq
uare
).
3006
Com
pone
nts
for
ICD
esig
n
Res
isto
rs
3
1 2
45 6
7 812
34
56
78
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
12
34
10
98
76
5R
= 1
assum
ing R
s =
0.1
ohm
s p
er
square
assum
ing R
s =
200 o
hm
s p
er
square
Exam
ple
s for
Meta
lE
xam
ple
for
Poly
sili
con
R =
R =
R =
•fo
rla
rger
resi
stan
ces
we
need
min
imum
wid
thpo
ly(o
ften
com
bine
dw
ith
ase
rpan
tine
shap
e)to
save
onar
ea
•co
rner
squa
res
coun
tas
half
2sq
uare
s
•fo
rpr
edic
atab
ility
and
mat
chin
gw
em
ayne
edw
ider
trac
ksw
itho
utco
rner
s
2 effe
ctiv
ere
sist
ance
≈0.56R
s
3007
Com
pone
nts
for
ICD
esig
n
Cap
acit
ors
me
tal−
insu
lato
r−m
eta
l ca
pa
cito
rp
oly
−in
su
lato
r−p
oly
ca
pa
cito
r
(sp
ecia
list
an
alo
g p
roce
ss w
ith
2 p
oly
la
ye
rs)
pa
ralle
l tr
acks o
ve
r u
nd
erlyin
g c
on
du
cto
r
(e.g
. b
ulk
sili
co
n)
frin
ge
ca
pa
cito
rB A
A
B
AB
l
ws
•C
apac
itan
ceto
unde
rlyi
ngco
nduc
torC
=Cawl
+2Cfl
•C
oupl
ing
capa
cita
nce
toad
jace
nttr
ackC
=Ccl/s
whe
reCa,C
f,C
car
eco
nsta
nts
for
agi
ven
laye
ran
dpr
oces
s
indi
gita
ldes
igns
our
only
aim
isto
min
imis
epa
rasi
tic
capa
cita
nce
3008
3
1 2
45 6
7 812
34
56
78
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
Dio
de
NP
N T
ransis
tor
NM
OS
Enhancem
ent tr
ansis
tor
NM
OS
Pro
cess
Resis
tor
Capacitors
PNN
PE
BC
NN
P
EB
C
SD
G
SD
SUB
PN
N
B AAB
3000
CM
OS
NM
OS
Tran
sist
or–
wit
hto
psu
bstr
ate
conn
ecti
on
SUB
SD
GD
S
G
SUB
NN
P+
++
P w
ell
N+
im
pla
nt
ma
sk
P+
im
pla
nt
ma
sk
P w
ell
ma
sk
SD
G
SUB
4001
CM
OS
NM
OS
Tran
sist
or–
wit
hto
psu
bstr
ate
conn
ecti
on
Whe
reit
isno
tsu
itab
lefo
rsu
bstr
ate
conn
ecti
ons
tobe
shar
ed,
am
ore
com
plex
proc
ess
isus
ed.
•Fi
vem
asks
mus
tbe
used
tode
fine
the
tran
sist
or:
–P
Wel
l
–A
ctiv
eA
rea
–Po
lysi
licon
–N
+im
plan
t
–P+
impl
ant
•P
Wel
l,fo
ris
olat
ion.
•To
psu
bstr
ate
conn
ecti
on.
•P+
/N+
impl
ants
prod
uce
good
ohm
icco
ntac
ts.
4002
CM
OS
CM
OS
Inve
rter
N−
we
ll
Active
Are
a
N
imp
lan
t
P
imp
lan
t
Po
lysili
co
n
Co
nta
ct
Win
do
w
Me
tal
N
N P
N NP P P
4003
CM
OS
CM
OS
Inve
rter
•Th
epr
oces
sde
scri
bed
here
isan
NW
ellp
roce
sssi
nce
itha
son
lyan
NW
ell.
PW
ella
ndTw
inTu
bpr
oces
ses
also
exis
t.
•N
ote
that
the
P-N
junc
tion
betw
een
chip
subs
trat
ean
dN
Wel
lwill
rem
ain
re-
vers
ebi
ased
.
Thus
the
tran
sist
ors
rem
ain
isol
ated
.
•N
impl
antd
efine
sN
MO
Sso
urce
/dra
inan
dPM
OS
subs
trat
eco
ntac
t.
•P
impl
antd
efine
sPM
OS
sour
ce/d
rain
and
NM
OS
subs
trat
eco
ntac
t.
4004
Proc
essi
ng–
Phot
olit
hogr
aphy
SiO
2
(po
sitiv
e)
Ph
oto
resis
t
Ox
ide
Gro
wth
Ph
oto
res
ist
De
po
sit
ion
Sil
ico
n W
afe
r
Co
nta
ct/
Pro
xim
ity
Ma
sk
Ma
sk P
att
ern
Gla
ss M
ask
Ph
oto
res
ist
Str
ip
Ox
ide
Etc
h
Ph
oto
res
ist
De
ve
lop
me
nt
Ph
oto
res
ist
Ex
po
su
re
UV
Lig
ht
(ch
rom
e)
4005
Proc
essi
ng–
Mas
kM
akin
g
Pa
tte
rn r
ep
rod
uc
ed
on
wa
fer
(or
co
nta
ct/
pro
xim
ity
ma
sk
)
by
ste
p a
nd
re
pe
at
wit
h o
pti
ca
l re
du
cti
on
ele
ctr
on
be
am
Re
tic
le w
ritt
en
by
sc
an
nin
g
Re
ticle
Ma
sk
Le
ns
UV
Lig
ht
•O
ptic
alre
duct
ion
allo
ws
narr
ower
line
wid
ths.
4006
PN
PN
NP
PN
PN
PN
NP
PN
NP
NP
NP
N im
pla
nt
P im
pla
nt
N−
well
Active A
rea
Poly
sili
con
Conta
ct W
indow
Meta
l
defines T
hic
k O
xid
e
defines T
hin
Oxid
e
PN
PN
PN
NP
PN
PP
P
defines T
hic
k O
xid
e
defines T
hin
Oxid
e
alig
ned to A
A a
nd P
oly
alig
ned to A
A a
nd P
oly
4007
CM
OS
In
ve
rte
r
CM
OS
In
ve
rte
r
CM
OS
In
ve
rte
r
Fea
ture
s m
ay b
e d
eter
min
ed b
y a
nu
mb
er o
f m
ask
se.
g.
NM
OS
so
urc
e d
rain
: A
ctiv
eAre
a A
ND
NO
T(N
Wel
l O
R P
oly
OR
PIm
pla
nt)
N−
Wel
l C
MO
S P
roce
sss
(wit
ho
ut
exp
lici
t N
+ i
mp
lan
t m
ask
)
N−
Wel
l C
MO
S P
roce
sss
(wit
h e
xp
lici
t N
+ i
mp
lan
t m
ask
)
Tw
in T
ub
CM
OS
Pro
cess
PM
OS
En
ha
nce
me
nt
tra
nsis
tor
CM
OS
Pro
cess
N W
ell
Active
Are
a
Po
lysili
co
n
P+
Im
pla
nt
N+
Im
pla
ntm
any
ste
ps
for
a si
ng
le m
ask
PN
NP
PN
PN
I
PN
NP
PN
NP
PN
NP
PN
NP
UV
Lig
ht
PP
++
+N
N w
ell
PP
++
N w
ell
N w
ell
N w
ell
N w
ell
N w
ell
P type s
ilicon w
afe
r
P P P P P P P P P
4000
Des
ign
Rul
es
Topr
even
tchi
pfa
ilure
,des
igns
mus
tcon
form
tode
sign
rule
s:
•Si
ngle
laye
rru
les
•M
ulti
-lay
erru
les
5001
Der
ivat
ion
ofD
esig
nR
ules
N
NN
La
tera
l D
iffu
sio
n
Iso
tro
pic
Etc
hin
g
is a
lign
ed
to
is a
lign
ed
to
Op
tic
al
Fo
cu
s o
ve
r 3
D t
err
ain
Re
ticle
Ma
sk
Mis
ali
gn
me
nt
ca
n b
e C
um
ula
tiv
e
NN
Ma
sk
Mis
ali
gn
me
nt 50
02
Des
ign
Rul
es
0.5µm
CM
OS
inve
rter
Active
Are
a
Me
tal
Co
nta
ct
Win
do
w
Po
lysili
co
n
= N
OT
N
im
pla
nt
P im
pla
nt
N−
we
ll
5003
Abs
trac
tion
Leve
lsof
Abs
trac
tion
•M
ask
Leve
lDes
ign
–La
bori
ous
Tech
nolo
gy/P
roce
ssde
pend
ent.
–D
esig
nru
les
may
chan
gedu
ring
ade
sign
!
•Tr
ansi
stor
Leve
lDes
ign
–Pr
oces
sin
depe
nden
t,Te
chno
logy
depe
nden
t.
•G
ate
Leve
lDes
ign
–Pr
oces
s/Te
chno
logy
inde
pend
ent. 50
04
Abs
trac
tion
-Sti
ckD
iagr
ams
Stic
kdi
agra
ms
give
usm
any
ofth
ebe
nefit
sof
abst
ract
ion:
•M
uch
easi
er/f
aste
rth
anfu
llm
ask
spec
ifica
tion
.
•Pr
oces
sin
depe
nden
t(va
lidfo
ran
yC
MO
Spr
oces
s).
•Ea
syto
chan
ge.
whi
leav
oidi
ngso
me
ofth
epr
oble
ms:
•O
ptim
ized
layo
utm
aybe
gene
rate
dm
uch
mor
eea
sily
from
ast
ick
diag
ram
than
from
tran
sist
oror
gate
leve
ldes
igns
.1
1 note
that
allI
Cde
sign
sm
uste
ndat
the
mas
kle
vel.
5005
Dig
ital
CM
OS
Des
ign St
ick
Dia
gram
s
& t
ap
Co
mb
ine
d c
on
tact
Co
nta
ct
P+
N+
Po
lysili
co
n
Me
tal
Ta
p
5006
Dig
ital
CM
OS
Des
ign St
ick
Dia
gram
s
5007
Dig
ital
CM
OS
Des
ign St
ick
Dia
gram
s
•Ex
plor
eyo
urD
esig
nSp
ace.
–Im
plic
atio
nsof
cros
sove
rs.
–N
umbe
rof
cont
acts
.
–A
rran
gem
ento
fdev
ices
and
conn
ecti
ons.
•Pr
oces
sin
depe
nden
tlay
out.
•Ea
syto
expa
ndto
afu
llla
yout
for
apa
rtic
ular
proc
ess.
5008
Stic
ksan
dC
AD
-Sym
bolic
Cap
ture
W=1.1
L=0.5
L=0.5
W=2.2
•Tr
ansi
stor
sar
epl
aced
and
expl
icit
lysi
zed.
-com
pone
nts
are
join
edw
ith
zero
wid
thw
ires
.-c
onta
cts
are
auto
mat
ical
lyse
lect
edas
requ
ired
.
•A
sem
i-au
tom
atic
com
pact
ion
proc
ess
will
crea
teD
RC
corr
ectl
ayou
t.
5009
Stic
ksan
dC
AD
-Mag
ic
•Lo
gst
yle
desi
gn(s
tick
sw
ith
wid
th)-
DR
Cer
rors
are
flagg
edim
med
iate
ly.
-aga
inco
ntac
tsar
eau
tom
atic
ally
sele
cted
asre
quir
ed.
•O
n-lin
eD
RC
lead
sto
rapi
dge
nera
tion
ofco
rrec
tdes
igns
.-s
ymbo
licca
ptur
est
yle
com
pact
ion
isav
aila
ble
ifde
sire
d.
5010
Op
tim
ise
d M
ask L
ayo
ut
Eq
uiv
ale
nt
Stick D
iag
ram
De
sig
n R
ule
s −
wid
th,
se
pa
ratio
n,
ove
rla
p
& t
ap
Co
mb
ine
d c
on
tact
Co
nta
ct
P+
N+
Po
lysili
co
nM
eta
l
Ta
p
5000
Dig
ital
CM
OS
Des
ign
Alo
gica
lapp
roac
hto
gate
layo
ut.
•A
llco
mpl
emen
tary
gate
sm
aybe
desi
gned
usin
ga
sing
lero
wof
n-tr
ansi
stor
sab
ove
orbe
low
asi
ngle
row
ofp-
tran
sist
ors,
alig
ned
atco
mm
onga
teco
nnec
tions
.
6001
Dig
ital
CM
OS
Des
ign
Eule
rPa
th
•Fo
rth
em
ajor
ity
ofth
ese
gate
sw
eca
nfin
dan
arra
ngem
ento
ftra
nsis
tors
such
that
we
can
butt
adjo
inin
gtr
ansi
stor
s.
–C
aref
ulse
lect
ion
oftr
ansi
stor
orde
ring
.
–C
aref
ulor
ient
atio
nof
tran
sist
orso
urce
and
drai
n.
•R
efer
red
toas
line
ofdi
ffusi
on.
6002
Dig
ital
CM
OS
Des
ign
Find
ing
anEu
ler
Path
Com
pute
rA
lgor
ithm
s
•It
isre
lati
vely
easy
for
aco
mpu
ter
toco
nsid
eral
lpo
ssib
lear
rang
emen
tsof
tran
sist
ors
inse
arch
ofa
suit
able
Eule
rpa
th.
This
isno
tso
easy
for
the
hum
ande
sign
er.
One
Hum
anA
lgor
ithm
•Fi
nda
path
whi
chpa
sses
thro
ugh
alln
-tra
nsis
tors
exac
tly
once
.
•Ex
pres
sth
epa
thin
term
sof
the
gate
conn
ecti
ons.
•Is
itpo
ssib
leto
follo
wa
sim
ilarl
yla
belle
dpa
thth
roug
hth
ep-
tran
sist
ors?
–Ye
s–
you’
vesu
ccee
ded.
–N
o–
try
agai
n(y
oum
aylik
eto
try
ap
path
first
this
tim
e).
6003
Dig
ital
CM
OS
Des
ign
Find
ing
anEu
ler
Path
Z
A C B
Her
eth
ere
are
four
poss
ible
Eule
rpa
ths. 60
04
Dig
ital
CM
OS
Des
ign
Find
ing
anEu
ler
Path
6005
Dig
ital
CM
OS
Des
ign
Eule
rPa
thEx
ampl
e
12
34
5
12
34
5
1.Fi
ndEu
ler
path
3.R
oute
pow
erno
des
5.R
oute
rem
aini
ngno
des
2.La
belp
oly
colu
mns
4.R
oute
outp
utno
de6.
Add
taps
1fo
rPM
OS
and
NM
OS
Aco
mbi
ned
cont
acta
ndta
p,,m
aybe
used
only
whe
rea
pow
erco
ntac
texi
sts
atth
een
dof
alin
eof
diffu
sion
.Whe
reth
isis
nott
heca
sea
sim
ple
tap,
,sho
uld
beus
ed.
1 1ta
pis
good
for
abou
t6tr
ansi
stor
s–
insu
ffici
entt
aps
may
leav
ea
chip
vuln
erab
leto
latc
h-up
6006
Dig
ital
CM
OS
Des
ign
Find
ing
anEu
ler
Path
OD
D
OD
D
OD
D
OD
D
PD
N T
op
olg
y:
Z
A B C D E F
No
poss
ible
path
thro
ugh
n-tr
ansi
stor
s!
6007
Dig
ital
CM
OS
Des
ign
Find
ing
anEu
ler
Path
6008
Dig
ital
CM
OS
Des
ign
Find
ing
anEu
ler
Path E
VE
N
EV
EN
OD
DO
DD
OD
D
PU
N T
op
olg
y:
Z
A D E B F G C H I
•N
opo
ssib
lepa
thth
roug
hp-
tran
sist
ors.
•N
ore
-arr
ange
men
twill
crea
tea
solu
tion
!
6009
Dig
ital
CM
OS
Des
ign
Philo
soph
ers
vs.E
ngin
eers
Z
A D E B F G C H I
•Th
eph
iloso
pher
isha
ppy
topr
ove
that
ther
eis
noEu
ler
path
tobe
foun
d.
•Th
een
gine
erw
illus
epa
rtia
lEul
erpa
ths
tore
ach
the
best
solu
tion
.
6010
Inve
stig
atio
n o
f E
ule
r p
ath
s le
ad
s t
o m
ore
eff
icie
nt
layo
ut*
*not all
gate
s w
ill s
upport
a c
om
mon E
ule
r path
for
both
PM
OS
and N
MO
S
EV
EN
EV
EN
EV
EN
OD
D
OD
D
OD
D
OD
D
OD
D
EV
EN
EV
EN
OD
D
OD
D
OD
D 12
45
67
3
12
45
67
3
12
45
67
3
12
45
67
3
12
45
67
3
12
45
67
3
51 2 3
6
7
6
57 4
2
13
4
6000
Dig
ital
CM
OS
Des
ign M
ulti
ple
gate
s
SA
BY
SA
BY
A B
S
Y1 0
A BY
S
7001
Dig
ital
CM
OS
Des
ign M
ulti
ple
gate
s
•G
ates
shou
ldal
lbe
ofsa
me
heig
ht.
–Po
wer
and
grou
ndra
ilsw
illth
enlin
eup
whe
nbu
tted
.
•A
llga
tein
puts
and
outp
uts
are
avai
labl
eat
top
and
bott
om.
–A
llro
utin
gis
exte
rnal
toce
lls.
–Pr
eser
ves
the
bene
fits
ofhi
erar
chy.
•In
terc
onne
ctis
via
two
cond
ucto
rro
utin
g.–
Inth
isca
sePo
lysi
licon
vert
ical
lyan
dM
etal
hori
zont
ally
.
7002
Dig
ital
CM
OS
Des
ign Tw
o-la
yer
Met
al
LA
YE
R
1 M
ET
AL
2 M
ET
AL
LA
YE
RS
Mos
tmod
ern
VLS
Ipro
cess
essu
ppor
ttw
oor
mor
em
etal
laye
rs.
The
norm
isto
use
only
met
alfo
rin
ter-
cell
rout
ing.
usua
llyM
etal
1fo
rho
rizo
ntal
inte
r-ce
llro
utin
g(a
ndfo
rpo
wer
rails
)M
etal
2ve
rtic
al(a
ndfo
rce
llin
puts
and
outp
uts)
.
7003
Stan
dard
Cel
lDes
ign
Man
yIC
sar
ede
sign
edus
ing
the
stan
dard
cell
met
hod.
•C
ellL
ibra
ryC
reat
ion
Ace
lllib
rary
,con
tain
ing
com
mon
lyus
edlo
gic
gate
s1is
crea
ted
for
apr
oces
s.Th
isis
ofte
nca
rrie
dou
tby
oron
beha
lfof
the
foun
dry.
•A
SIC
2D
esig
nTh
eA
SIC
desi
gner
mus
tde
sign
aci
rcui
tus
ing
the
logi
cga
tes
avai
labl
ein
the
libra
ry.
The
ASI
Cde
sign
erus
ually
has
noac
cess
toth
efu
llla
yout
ofth
est
anda
rdce
llsan
ddo
esn’
tcre
ate
any
new
cells
for
the
libra
ry.
Layo
utw
ork
perf
orm
edby
the
ASI
Cde
sign
eris
divi
ded
into
two
stag
es:
–Pl
acem
ent
–R
outi
ng
1 note
that
ast
anda
rdce
llm
ayin
clud
etr
ansi
stor
sfr
omm
ore
than
one
basi
cfu
ncti
on(e
.g.N
AN
D+
inve
rter
togi
veA
ND
)but
will
norm
ally
bede
sign
edfla
ti.e
.wit
hout
layo
uthi
erar
chy.
2 App
licat
ion
Spec
ific
Inte
grat
edC
ircu
it
7004
Stan
dard
Cel
lDes
ign
Cho
osin
ga
seto
fcel
lsfo
ra
cell
libra
ry•
Ther
eis
nose
tsiz
efo
ra
cell
libra
ry.
•Th
eore
tica
llyju
ston
ece
ll(
)or
one
type
ofce
ll(
,,
,...)
issu
ffici
entf
ora
cell
libra
ry.
•Th
eus
eof
mor
eco
mpl
exce
llsal
low
sfo
rde
sign
sop
tim
ised
for
area
and/
orpe
rfor
man
ce:
A B
S
Y1 0
A BY
S
Multip
lexer
sta
ndard
cell
(sin
gle
ce
ll −
no
hie
rarc
hy)
SA
BY
•W
hich
basi
cga
tes;
whi
chco
mpo
und
gate
s;w
hich
sequ
enti
alga
tes?
•D
ow
epr
ovid
edi
ffer
entv
ersi
ons
ofth
esa
me
gate
(e.g
.sm
alla
rea
vers
ion,
high
driv
eve
rsio
n)?
Ifso
,how
man
ydi
ffer
entv
ersi
ons?
7005
Stan
dard
Cel
lDes
ign
Layo
utan
dA
bstr
actV
iew
sof
aSt
anda
rdC
ell
GND!
GND!
Vdd!
Vdd!
AB
Y YB
A
GND!
GND!
Vdd!
Vdd!
AB
Y YB
A
LAYOUT
ABSTRACT
The
part
ialc
elll
ayou
tusu
ally
give
nto
the
ASI
Cde
sign
eris
know
nas
abl
ack
box
orab
stra
ctvi
ew.T
heab
stra
ct:
•m
usti
nclu
dece
llpo
rts
and
ace
llbo
unda
ry
•m
ayin
clud
eso
me
oral
loft
hem
etal
mas
kin
form
atio
n
7006
Plac
emen
t&R
outi
ng
Plac
emen
t
Cel
lsar
epl
aced
inon
eor
seve
rale
qual
leng
thlin
esw
ith
inte
r-di
gita
ted
pow
eran
dgr
ound
rails
.
7007
Plac
emen
t&R
outi
ng
Rou
ting
Inth
ero
utin
gch
anne
lsbe
twee
nth
ece
llsw
ero
ute
met
al1
hori
zont
ally
and
met
al2
vert
ical
ly.
7008
Plac
emen
t&R
outi
ng
Two
cond
ucto
rro
utin
g
•C
ondu
ctor
Afo
rho
rizo
ntal
inte
r-ce
llro
utin
gC
ondu
ctor
Bve
rtic
al3
•Th
islo
gica
lapp
roac
hm
eans
that
we
shou
ldne
ver
have
tow
orry
abou
tsig
nals
cros
sing
.
This
mak
eslif
eco
nsid
erab
lyea
sier
for
aco
mpu
ter
(or
even
ahu
man
)to
com
-pl
ete
the
rout
ing.
•W
em
ust
only
ensu
reth
attw
osi
gnal
sw
illno
tm
eet
inth
esa
me
hori
zont
alor
vert
ical
chan
nel.
•C
ompu
ter
algo
rith
ms
can
beus
edto
ensu
repl
acem
ento
fcel
lssu
chth
atw
ires
are
shor
t.4
•Fu
rthe
rco
mpu
ter
algo
rith
ms
can
beus
edto
opti
miz
eth
ero
utin
git
self
.
3 Inth
etw
o-m
etal
exam
ple
Con
duct
orA
isM
etal
1an
dC
ondu
ctor
Bis
Met
al2
4 InV
LSIc
ircu
its
we
ofte
nfin
dth
atin
ter-
cell
wir
ing
occu
pies
mor
ear
eath
anth
ece
llsth
emse
lves
.
7009
Stan
dard
Cel
lDes
ign M
ore
Met
alLa
yers
Wit
hth
ree
orm
ore
met
alla
yers
itis
poss
ible
tota
kea
diff
eren
tapp
roac
h.Th
esi
mpl
este
xam
ple
uses
thre
em
etal
laye
rs.
•St
anda
rdC
ells
Use
only
met
al1
exce
ptfo
rI/
Ow
hich
isin
met
al2
•Tw
oC
ondu
ctor
Rou
ting
Use
sm
etal
2an
dm
etal
3
Vdd!
GND!
AB
YA
BY
Vdd!
GND!
AB
Y
LAYOUT
ABSTRACT
ROUTING
7010
Stan
dard
Cel
lDes
ign M
ore
Met
alLa
yers
Wit
hth
isap
proa
chw
eca
nro
ute
safe
lyov
erth
ece
llto
the
spec
ified
pins
lead
ing
tom
uch
smal
ler
gaps
betw
een
cell
row
s. 7011
Stan
dard
Cel
lDes
ign
Alt
erna
tive
Plac
emen
tSty
le
Vdd!
Vdd!
Vdd!
Vdd!
Vdd!
Vdd!
Vdd!
Vdd!
Vdd!
Vdd!
GND!
GND!
GND!
GND!
GND!
GND!
GND!
GND!
GND!
Vdd!
GND!
GND!
Vdd!
Vdd!
GND!
Vdd!
GND!
GND!
GND!
GND!
GND!
Vdd!
Vdd!
Vdd!
Vdd!
GND!
Byfli
ppin
gev
ery
seco
ndro
wit
may
bepo
ssib
leto
elim
inat
ega
psbe
twee
nro
ws.
N-w
ells
are
mer
ged
and
pow
eror
grou
ndra
ilsar
esh
ared
.Th
isap
proa
chis
norm
ally
asso
ciat
edw
ith
spar
sero
ws
and
non
chan
nel
base
dro
utin
gal
gori
thm
s.
7012
Vdd!
Vdd!
YB
AAB
Y
GN
D!
GN
D!
NA
ND
2
GN
D!
YB
A
Vdd!
Vdd!
GN
D!
YB
A
NA
ND
2
AB
Y
Vdd!
GN
D!
NA
ND
2
GN
D!
AB
Y
AB
YV
dd!
NA
ND
2
YG
ND
!B
A
YV
dd!
BA
NA
ND
2
AB
Y
Vdd!
GN
D!
NA
ND
2
GN
D!
AB
Y
AB
YV
dd!
NA
ND
2
YG
ND
!B
A
YV
dd!
BA
NA
ND
2
3 M
ET
AL
LA
YE
RS
2 M
ET
AL
LA
YE
RS
LA
YE
R
1 M
ET
AL
LA
YO
UT
AB
ST
RA
CT
RO
UT
ING
Vdd!
Vdd!
GN
D!
GN
D!
AB
Y
NA
ND
2
7000
Syst
emD
esig
nC
hoic
es
•Pr
ogra
mm
able
Logi
c
–PL
De.
g.La
ttic
eis
pGA
L22V
10,A
tmel
ATF
1502
CPL
D
–Fi
eld
Prog
ram
mab
leG
ate
Arr
ay(F
PGA
)e.
g.In
telC
yclo
neV,
Xili
nxA
rtix
-7/Z
ync-
7000
•Se
mi-
Cus
tom
Des
ign
–M
ask
Prog
ram
mab
leG
ate
Arr
aye.
g.EC
SC
MO
SG
ate
Arr
ayIn
telH
ardC
opy
IIst
ruct
ured
ASI
Cs
–St
anda
rdC
ellD
esig
ne.
g.A
MS
CO
REL
IB0.
35µm
cell
libra
ry
•Fu
llC
usto
mD
esig
n
8001
Syst
emD
esig
nC
hoic
es
•Pr
ogra
mm
able
Logi
cST
AR
TH
ERE
–Be
stpo
ssib
lede
sign
turn
arou
ndti
me
–C
heap
estf
orpr
otot
ypin
g
–Be
stti
me
tom
arke
t
–M
inim
umsk
illre
quir
ed
•Se
mi-
Cus
tom
Des
ign
•Fu
llC
usto
mD
esig
n
–C
heap
estf
orm
ass
prod
ucti
on
–Fa
stes
t
–Lo
wes
tPow
er
–H
ighe
stD
ensi
ty1
–M
osts
kill
requ
ired
1 opti
miz
atio
nlim
ited
bysp
eed/
pow
er/a
rea
trad
eof
f
8002
Prog
ram
mab
leLo
gic
ICT
PEEL
22C
V10
Sour
ce:I
CT
•O
neti
me
use
-Fus
epr
ogra
mm
able
.
•R
epro
gram
mab
le-U
V/E
lect
rica
llyEr
asab
le.
8003
Fiel
dPr
ogra
mm
able
Gat
eA
rray
–X
ilinx
XC
4000
CL
B
Pro
gra
mm
ab
leIn
terc
on
ne
ctio
nP
oin
t
Vertical Routing Channel
Ho
rizo
nta
l R
ou
tin
g C
ha
nn
el
I/O Buffers
I/O
Bu
ffe
rs
I/O
Bu
ffe
rs
I/O Buffers
CL
B
CL
BC
LB
CL
B
Sw
itch
ing
Ma
trix
•C
onfig
urab
leLo
gic
Bloc
ks(C
LBs)
&I/
OBl
ocks
2
•Pr
ogra
mm
able
Inte
rcon
nect
2 Xili
nxX
C40
13ha
s57
6(2
4×
24)C
LBs
and
upto
192
(4×
48)u
ser
I/O
pins
.
8004
Fiel
dPr
ogra
mm
able
Gat
eA
rray
–X
ilinx
XC
4000
CLB
R
XC40
00E
and
XC40
00X
Serie
s Fi
eld
Prog
ram
mab
le G
ate
Arr
ays
6-10
May
14,
199
9 (V
ersi
on 1
.6)
Flip
-Flo
psTh
eC
LBca
npa
ssth
eco
mbi
nato
rialo
utpu
t(s)t
oth
ein
ter-
conn
ect
netw
ork,
but
can
also
stor
eth
eco
mbi
nato
rial
resu
ltsor
othe
rinc
omin
gda
tain
one
ortw
ofli
p-flo
ps,a
ndco
nnec
t the
ir ou
tput
s to
the
inte
rcon
nect
net
work
as
well.
The
two
edge
-trig
gere
dD
-type
flip-
flops
have
com
mon
cloc
k(K
)and
cloc
ken
able
(EC
)inp
uts.
Eith
eror
both
cloc
kin
puts
can
also
bepe
rman
ently
enab
led.
Stor
age
elem
ent
func
tiona
lity
is d
escr
ibed
inTa
ble
2.
Latc
hes
(XC4
000X
onl
y)Th
eC
LBst
orag
eel
emen
tsca
nal
sobe
confi
gure
das
latc
hes.
The
two
latc
hes
have
com
mon
cloc
k(K
)and
cloc
ken
able
(EC
)in
puts
.St
orag
eel
emen
tfu
nctio
nalit
yis
desc
ribed
inTa
ble
2.
Cloc
k In
put
Each
flip-
flop
can
betri
gger
edon
eith
erth
eris
ing
orfa
lling
cloc
ked
ge.T
hecl
ock
pin
issh
ared
bybo
thst
orag
eel
e-m
ents
.How
ever
,the
cloc
kis
indi
vidu
ally
inve
rtibl
efo
reac
hst
orag
eel
emen
t.An
yin
verte
rpla
ced
onth
ecl
ock
inpu
tis
auto
mat
ical
ly a
bsor
bed
into
the
CLB
.
Cloc
k En
able
The
cloc
ken
able
sign
al(E
C)i
sac
tive
Hig
h.Th
eEC
pin
issh
ared
bybo
thst
orag
eel
emen
ts.I
flef
tunc
onne
cted
for
eith
er,t
hecl
ock
enab
lefo
rtha
tsto
rage
elem
entd
efau
ltsto
the
activ
e st
ate.
EC
is n
ot in
verti
ble
with
in th
e C
LB.
LOG
IC
FUN
CTI
ON
O
F G
1-G
4
G4
G3
G2
G1
G'
LOG
IC
FUN
CTI
ON
O
F F1
-F4
F 4 F 3 F 2 F 1
F'
LOG
IC
FUN
CTI
ON
O
F F'
, G',
AND
H
1
H'
DIN
F'
G
' H
' DIN
F'
G
' H
'
G'
H'
H'
F'
S/R
C
ON
TRO
L
D ECR
D
Bypa
ss
Bypa
ss
SDYQ XQ
Q
S/R
C
ON
TRO
L
D ECR
D
SDQ
11
K (CLO
CK)
Mul
tiple
xer C
ontro
lled
by C
onfig
urat
ion
Prog
ram
Y X
DIN
/H2
H1
SR
/H0
EC
X669
2
C1
• • •
C4
4
Figu
re 1
: S
impl
ified
Blo
ck D
iagr
am o
f XC
4000
Ser
ies
CLB
(RA
M a
nd C
arry
Log
ic fu
nctio
ns n
ot s
how
n)
Tabl
e 2:
CLB
Sto
rage
Ele
men
t Fun
ctio
nalit
y(a
ctiv
e ris
ing
edge
is s
how
n)
Mod
e K
EC
SR
D
QPo
wer
-Up
orG
SRX
XX
XSR
Flip
-Flo
pX
X1
XSR
__/
1*0*
DD
0X
0*X
Q
Latc
h1
1*0*
XQ
01*
0*D
DBo
thX
00*
XQ
Lege
nd: X __/
SR 0* 1*
Don
’t ca
reR
isin
g ed
geSe
t or R
eset
val
ue. R
eset
is d
efau
lt.In
put i
s Lo
w o
r unc
onne
cted
(def
ault
valu
e)In
put i
s H
igh
or u
ncon
nect
ed (d
efau
lt va
lue)
Prod
uct O
bsol
ete
or U
nder
Obs
oles
cenc
e
Sour
ce:X
ilinx
8005
7S
erie
s FP
GA
s C
LB U
ser
Gui
dew
ww
.xili
nx.c
om19
UG
474
(v1.
7) N
ovem
ber
17, 2
014
Slic
e D
escr
iptio
n
X-R
ef T
arge
t - F
igur
e 2-
3
Fig
ure
2-3:
Dia
gram
of S
LIC
EM
A6:
A1
D
CO
UT
D
DX C
CX B
BX A
AX
O6
DI2
O5
DI1
MC
31W
EN
CK
DI1
MC
31W
EN
CK
DI1
MC
31W
EN
CK
DI1
MC
31W
EN
CK
UG
474_
c2_0
2_11
0510
DX
DM
UX
D DQ
C CQ
CM
UX
B BQ
BM
UX
A AQ
AM
UX
Res
et T
ype
D
FF
/LAT
INIT
1IN
IT0
SR
HI
SR
LO
SR
CE
CK
FF
/LAT
INIT
1IN
IT0
SR
HI
SR
LO
FF
/LAT
INIT
1IN
IT0
SR
HI
SR
LO
FF
/LAT
INIT
1IN
IT0
SR
HI
SR
LO
D
SR
CE
CK
D
SR
CE
CK
D
SR
Q
CE
CK
CIN
0/1
WE
NW
E
CK
Syn
c/A
sync
FF
/LAT
A6:
A1
O6
O5
C6:
1
CX
D6:
1 DI
A6:
A1
O6
O5
B6:
1
BX
A6:
A1
W6:
W1
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