Spring 07, Apr 10, 12 Spring 07, Apr 10, 12 ELEC 7770: Advanced VLSI Design (Ag ELEC 7770: Advanced VLSI Design (Ag rawal) rawal) 1 ELEC 7770 ELEC 7770 Advanced VLSI Design Advanced VLSI Design Spring 2007 Spring 2007 Constraint Graph and Constraint Graph and Performance Optimization Performance Optimization Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor ECE Department, Auburn University ECE Department, Auburn University Auburn, AL 36849 Auburn, AL 36849 [email protected][email protected]http://www.eng.auburn.edu/~vagrawal/COURSE/E77 http://www.eng.auburn.edu/~vagrawal/COURSE/E77 70_Spr07 70_Spr07
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ELEC 7770 Advanced VLSI Design Spring 2007 Constraint Graph and Performance Optimization
ELEC 7770 Advanced VLSI Design Spring 2007 Constraint Graph and Performance Optimization. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr07. Retiming Theorem. - PowerPoint PPT Presentation
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Retiming TheoremRetiming Theorem Given a network G(V, E, W) and a cycle time T, Given a network G(V, E, W) and a cycle time T,
(r1, . . . ) is a feasible retiming if and only if:(r1, . . . ) is a feasible retiming if and only if: ri – rj ri – rj ≤ wij≤ wij for all edges (vi,vj) for all edges (vi,vj) εε E E ri – rj ≤ W(vi,vj) – 1 ri – rj ≤ W(vi,vj) – 1 for all node-pairs vi, vj such thatfor all node-pairs vi, vj such that
D(vi,vj) D(vi,vj) > T> T
Where,Where,
W(vi,vj) is the minimum weight path between vi and vjW(vi,vj) is the minimum weight path between vi and vj
D(vi,vj) is the maximum delay among all minimum D(vi,vj) is the maximum delay among all minimum weight paths between vi and vjweight paths between vi and vj
Find the clock period (T) by path analysis.Find the clock period (T) by path analysis. Set clock period to T/2 and find a feasible Set clock period to T/2 and find a feasible
retiming.retiming. If feasible, further reduce the clock period to If feasible, further reduce the clock period to
half.half. If not feasible, increase clock period.If not feasible, increase clock period. Do a binary search for optimum clock period.Do a binary search for optimum clock period. Retime the circuit.Retime the circuit.
A set of values for variables can be found if and A set of values for variables can be found if and only if the constraint graph has no positive only if the constraint graph has no positive cycles.cycles.
This is also the condition for the solvability of the This is also the condition for the solvability of the longest path problem, which provides a solution longest path problem, which provides a solution to the set of constraints.to the set of constraints.
Find the shortest (or longest) path in a graph Find the shortest (or longest) path in a graph from a source vertex to any other vertex.from a source vertex to any other vertex.
Graph has vertices and directed edges:Graph has vertices and directed edges: Edge weights can be positive or negativeEdge weights can be positive or negative Graph can be cyclicGraph can be cyclic Single source vertex – a vertex with 0 in-degreeSingle source vertex – a vertex with 0 in-degree
Inconsistent problemInconsistent problem Negative cycles for shortest pathNegative cycles for shortest path Positive cycles for longest pathPositive cycles for longest path
A. Aho, J. Hopcroft and J. Ullman, A. Aho, J. Hopcroft and J. Ullman, Data Structures and Data Structures and AlgorithmsAlgorithms, Reading, Massachusetts: Addison-Wesley, 1983., Reading, Massachusetts: Addison-Wesley, 1983.
T. Cormen, C. Leiserson and R. Rivest, T. Cormen, C. Leiserson and R. Rivest, Introduction to Introduction to AlgorithmsAlgorithms, New York: McGraw-Hill, 1990., New York: McGraw-Hill, 1990.
ri – rj ≤ wij edges i → jRetiming should not cause negative edge weights.
rh – ra ≤ 0ra – rb ≤ 0rb – rc ≤ 1rc – rh ≤ 1
Observation: Constraint graph has the same structure as the original retiming graph, with signs of weights reversed. Vertex labels are the retiming integer variables.