Spring 08, Mar 4, 6 Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Ag ELEC 7770: Advanced VLSI Design (Ag rawal) rawal) 1 ELEC 7770 ELEC 7770 Advanced VLSI Design Advanced VLSI Design Spring 2008 Spring 2008 Constraint Graph and Constraint Graph and Performance Optimization Performance Optimization Vishwani D. Agrawal Vishwani D. Agrawal James J. Danaher Professor James J. Danaher Professor ECE Department, Auburn University ECE Department, Auburn University Auburn, AL 36849 Auburn, AL 36849 [email protected][email protected]http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/ http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/ course.html course.html
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ELEC 7770 Advanced VLSI Design Spring 2008 Constraint Graph and Performance Optimization
ELEC 7770 Advanced VLSI Design Spring 2008 Constraint Graph and Performance Optimization. Vishwani D. Agrawal James J. Danaher Professor ECE Department, Auburn University Auburn, AL 36849 [email protected] http://www.eng.auburn.edu/~vagrawal/COURSE/E7770_Spr08/course.html. - PowerPoint PPT Presentation
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Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 11
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 22
Retiming TheoremRetiming Theorem Given a network G(V, E, W) and a cycle time T, Given a network G(V, E, W) and a cycle time T,
(r1, . . . ) is a feasible retiming if and only if:(r1, . . . ) is a feasible retiming if and only if: ri – rj ri – rj ≤ wij≤ wij for all edges (vi,vj) for all edges (vi,vj) εε E E ri – rj ≤ W(vi,vj) – 1 ri – rj ≤ W(vi,vj) – 1 for all node-pairs vi, vj such thatfor all node-pairs vi, vj such that
D(vi,vj) D(vi,vj) > T> T
Where,Where,
W(vi,vj) is the minimum weight path between vi and vjW(vi,vj) is the minimum weight path between vi and vj
D(vi,vj) is the maximum delay among all minimum D(vi,vj) is the maximum delay among all minimum weight paths between vi and vjweight paths between vi and vj
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 33
Timing OptimizationTiming Optimization
Find the clock period (T) by path analysis.Find the clock period (T) by path analysis. Set clock period to T/2 and find a feasible Set clock period to T/2 and find a feasible
retiming.retiming. If feasible, further reduce the clock period to If feasible, further reduce the clock period to
half.half. If not feasible, increase clock period.If not feasible, increase clock period. Do a binary search for optimum clock period.Do a binary search for optimum clock period. Retime the circuit.Retime the circuit.
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 44
Representing a ConstraintRepresenting a Constraint
ri – rj ≤ wij or rj ≥ ri – wij
rj ri– wij
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 55
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 66
Feasibility ConditionFeasibility Condition
A set of values for variables can be found if and A set of values for variables can be found if and only if the constraint graph has no positive only if the constraint graph has no positive cycles.cycles.
This is also the condition for the solvability of the This is also the condition for the solvability of the longest path problem, which provides a solution longest path problem, which provides a solution to the set of constraints.to the set of constraints.
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 77
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 99
The General Path ProblemThe General Path Problem Find the shortest (or longest) path in a graph Find the shortest (or longest) path in a graph
from a source vertex to all other vertices.from a source vertex to all other vertices. Graph has vertices and directed edges:Graph has vertices and directed edges:
Edge weights can be positive or negativeEdge weights can be positive or negative Graph can be cyclicGraph can be cyclic Single source vertex – a vertex with 0 in-degree (not a Single source vertex – a vertex with 0 in-degree (not a
necessary condition)necessary condition)
Inconsistent problemsInconsistent problems Negative weight cycles for shortest pathNegative weight cycles for shortest path Positive weight cycles for longest pathPositive weight cycles for longest path
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1010
A. Aho, J. Hopcroft and J. Ullman, A. Aho, J. Hopcroft and J. Ullman, Data Structures and Data Structures and AlgorithmsAlgorithms, Reading, Massachusetts: Addison-Wesley, 1983., Reading, Massachusetts: Addison-Wesley, 1983.
T. Cormen, C. Leiserson and R. Rivest, T. Cormen, C. Leiserson and R. Rivest, Introduction to Introduction to AlgorithmsAlgorithms, New York: McGraw-Hill, 1990., New York: McGraw-Hill, 1990.
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 1111
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2222
Bellman-Ford for Cycles, Neg. WeightsBellman-Ford for Cycles, Neg. Weights
v0
v2
v3
v1w01=15 3
5
2 4source
si = path weight (v0, vi)
Alg. stepsAlg. steps s0s0 s1s1 s2s2 s3s3
InitiallyInitially 00 1515 22
Iteration 1Iteration 1 00 77 22 66
Iteration 2Iteration 2 00 77 22 55
Iteration 3Iteration 3 00 77 22 55
-2 n = 3 (shortest path)
This was incorrect with Dijkstra’s shortest path algorithm
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2323
Bellman-Ford for Negative CycleBellman-Ford for Negative Cycle
v0
v2
v3
v1w01=15 -3
5
2 4source
si = path weight (v0, vi)
Alg. stepsAlg. steps s0s0 s1s1 s2s2 s3s3
InitiallyInitially 00 1515 22
Iteration 1Iteration 1 00 77 22 66
Iteration 2Iteration 2 00 33 22 66
Iteration 3Iteration 3 00 33 22 55
2
Values not stabilized after n iterations.Inconsistent problem: negative cycle.
n = 3 (shortest path)
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2424
Retiming ExampleRetiming Example
FF10 5 5
Delay
a b c
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2525
Retiming GraphRetiming Graph
FF10 5 5a b c
h0
a10
b5
c5
0 0 1
1
Critical path = 15It is the longest path consisting only of zero weight edges.
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2626
Feasibility ConstraintsFeasibility Constraints
FF10 5 5a b c
h0
a10
b5
c5
0 0 1
1
ri – rj ≤ wij edges i → jRetiming should not cause negative edge weights.
rh – ra ≤ 0ra – rb ≤ 0rb – rc ≤ 1rc – rh ≤ 1
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2727
Constraint GraphConstraint Graph
FF10 5 5a b c
rh0
ra10
rb5
rc5
0 0 -1
-1
ri – rj ≤ wij edges i → jRetiming should not cause negative edge weights.
rh – ra ≤ 0ra – rb ≤ 0rb – rc ≤ 1rc – rh ≤ 1
Observation: Constraint graph has the same structure as the original retiming graph, with signs of weights reversed. Vertex labels are the retiming integer variables.
Spring 08, Mar 4, 6Spring 08, Mar 4, 6 ELEC 7770: Advanced VLSI Design (Agrawal)ELEC 7770: Advanced VLSI Design (Agrawal) 2828
Max Delay for Min Weight PathsMax Delay for Min Weight Paths