ELCT 1003: High Speed Electronic Circuit Lecture 13: Power Distribution Network in High Speed Integrated Circuit Dr. Mohamed Abd El Ghany, Department of Electronics and Electrical Engineering [email protected]
ELCT 1003:High Speed Electronic Circuit
Lecture 13: Power Distribution Network in High Speed Integrated Circuit
Dr. Mohamed Abd El Ghany, Department of Electronics and Electrical Engineering
Moore’s Law
2Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
http://www.intel.com/technology/mooreslaw/
Trends in Propagation Delay
3Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Block to block distances are increasing
– Delay of the global wiring is increasing dramatically
*National Technology Roadmap for Semiconductors: Semiconductor Industry Association, 2007
Process Technology Node (nm)
250 32456590130180
100
0.1
10
1
Gate Delay
Local
Global with Repeaters
Global without Repeaters
Relative
Delay
Global
Semi-
Global
Local
Substrate
Power Dissipation of Intel
Microprocessors
4Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
S. Borkar, “Obying Moore’s Law beyond 0.18 Micron,” Proceedings of the IEEE International ASIC/SOC Conference, pp.
26-31 September 2000
At 90 nm technology and below, leakage power management is essential in the ASIC design process.
501001301802500
50
100
150
200
250
Device dimension (nm)
Pow
er (
w)
Leakage
Dynamic
Example of Communication
Structures in System on Chip
5Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Networks are preferred over buses:
• Higher bandwidth
• Scalability
High Speed Interconnect Modeling,
Simulation, and Optimization
6Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Interconnect design has become a dominant issue in high-speed
integrated circuits (ICs).
With the decreased feature size of CMOS circuits, on-chip interconnect
now dominates both circuit delay and power dissipation.
The minimum delay for a
signal to propagate along
an RLC line decreases
while the power dissipation
increases for wider
interconnect
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38
(2004) 205–225
Repeater Insertion Process
7Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
The primary objective of a uniform repeater insertion system is to
minimize the time for a signal to propagate through a long interconnect.
Uniform repeater insertion techniques divide the interconnect into
equal sections and employ equal size repeaters to drive each section.
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38 (2004) 205–225
Interconnect sizing within a repeater
system
8Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38 (2004) 205–225
Wire sizing within a
repeater insertion system
affect two design
parameters.
The number
of repeaters
The optimum
size of each
repeater
Propagation delay
9Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Expressions for the optimum number of repeaters Nopt–RLC and the optimum
repeater size kopt–RLC are
where
* Y.I. Ismail, E.G. Friedman, Effects of Inductance on the propagation delay and repeater insertion in VLSI circuits,
IEEE Trans. Very Large Scale Integration Systems 8 (2) (2000) 195–206.
C0 and R0 are the input capacitance and output resistance of a
minimum size repeater, respectively.
Rint(Wint), Cint(Wint), and Lint(Wint) are the interconnect line resistance,
capacitance, and inductance as functions of the interconnect width.
Propagation delay
10Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Expressions for the optimum number of repeaters Nopt–RLC and the optimum
repeater size kopt–RLC are
where
The interconnect resistance decreases with increasing line width,
increasing Lint/Rint the ratio between the line inductance and resistance.
An increase in Lint/Rint decreases the number of inserted repeaters to
achieve the minimum propagation delay.
For an RLC line, the minimum signal propagation delay decreases with
wider wires until no repeaters should be used.
* Y.I. Ismail, E.G. Friedman, Effects of Inductance on the propagation delay and repeater insertion in VLSI circuits,
IEEE Trans. Very Large Scale Integration Systems 8 (2) (2000) 195–206.
Propagation delay
11Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
For a copper interconnect line, low k dielectric material, R0=2kΩ, and C0=1fF, Nopt-
RLC is determined for minimum propagation delay for different line widths.
For an RLC line, the optimum number of repeaters which minimizes the signal
propagation delay decreases with an increase in the line width for all line lengths.
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38 (2004) 205–225
Propagation delay
12Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
For an inductive interconnect line, the total signal
propagation delay is:
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38 (2004) 205–225
where tpd-section(Wint) is the signal
delay of each RLC section as a
function of the interconnect
width.
The lower limit in the propagation
delay decreases with increasing line width
until the number of repeaters is zero.
Power Dissipation
13Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Short-circuit power dissipation
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38 (2004) 205–225
Short-circuit current flows when both transistors within an inverting
repeater are simultaneously on.
Thin lines cause less dynamic power and higher short-circuit power to be
dissipated.
For thin resistive lines, the number of repeaters can be large. The short-
circuit power dissipation in all repeaters along a line is considered.
Short-circuit power depends on both the input signal transition time and
the load characteristics.
A simple and accurate expression for the short-circuit power
dissipation of a repeater driving an RC load is
where Ipeak is the peak current that flows from Vdd to ground,
tbase is the time period during which both transistors are on
The total short-circuit power of a repeater system is
Power Dissipation
14Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Dynamic power dissipation
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38 (2004) 205–225
The dynamic power is the power required to charge and discharge the
various device and interconnect capacitances.
The total dynamic power is the summation of the CV2f power from the
line capacitance and the repeaters.
where
Power Dissipation
15Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Total power dissipation
* M.A. El-Moursy, E.G. Friedman / INTEGRATION, the VLSI journal 38 (2004) 205–225
Global Interconnect Width and
Spacing Optimization
16Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Cross section of global interconnects
W is the interconnect
width,
S is the interconnect
spacing,
T is the interconnect
thickness
Tox is the dielectric height
Global Interconnect Width and
Spacing Optimization
17Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
It is shown that the optimized delay per unit length increases as the
line inductance increases.
However, even if the line inductance is considered, there will be less
than 8% improvement in the accuracy of the delay per unit length.
Besides, if the line inductance is less than a critical inductance lcrit ,
the response will be overdamped, which is very similar to the Elmore
delay response *
It is validated that the overdamped criterion (l < lcrit )is being satisfied
for a bigger range of line inductance and the effect of inductance on
interconnect performance is reduced as the technology scales.
Therefore, inductance effects are not considered in the global
interconnect model in this section
* W. C. Elmore, “The transient response of damped linear network with particular regard to wide-band amplifiers,”
J. Appl. Phys., vol. 19, pp. 55–63, 1948
Effects of Width and Spacing on
Global Interconnect Performance
18Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
Where Echip is the chip width for global interconnects and L is the
interconnect length. The global interconnect pitch is W+S.
Assuming all of global interconnects have the same line width
and line spacing, then the number of global interconnects N is :
SW
EN
chip
int
Effects of Width and Spacing on
Global Interconnect Performance
19Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
The time constant of the segment is:
Where the interconnect capacitance per unit
length is given by
where
ca represents the fringing capacitance,
cb represents the parallel plate capacitance to the top and bottom layers of
metal and is proportional to interconnect width,
cc represents the coupling capacitance between the neighboring
interconnects and is inversely proportional to interconnect spacing.•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
Effects of Width and Spacing on
Global Interconnect Performance
20Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
The time constant of the segment is:
The total delay D of global interconnects is
proportional to the delay per unit length ,
Therefore, the optimal repeater size Kopt and the optimal inter-buffer
segment line length hopt is given by
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
Effects of Width and Spacing on
Global Interconnect Performance
21Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
The optimal delay per unit length is :
where a is a constant and cannot be changed for a given technology
The delay of one segment of length hopt is
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
Effects of Width and Spacing on
Global Interconnect Performance
22Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
The bandwidth B of global interconnects with the
optimal buffer insertion is given by:
which is proportional to the number of global interconnects N and inversely
proportional to the delay of global interconnects D.
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
Effects of Width and Spacing on
Global Interconnect Performance
23Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
The bandwidth B is maximal when :
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
The total repeater area of global interconnects with optimal
buffer insertion is given by
which is proportional to the number of global
interconnects and the size of the repeater,
and inversely proportional to inter-buffer
interconnect length
Effects of Width and Spacing on
Global Interconnect Performance
24Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
The energy dissipation consumed by each
interbuffer line in a clock period can be
approximated by:
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
Then the total power consumption is given by:
Increasing width and spacing
decreases both total repeater area
and power consumption.
Width and Spacing Optimization for
the Maximal Figure of Merit
25Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
The aim of global interconnect design is to get large bandwidth, small
delay per unit length, small repeater area, and low power consumption
simultaneously.
Unfortunately, large bandwidth requires small global interconnect
width and spacing, but small delay , small repeater area , and low power
consumption all require large global interconnect width and spacing.
Therefore, the figure of merit should be considered for simultaneous
short latency and large bandwidth, which is defined by
D
BF
Width and Spacing Optimization for
the Maximal Figure of Merit
26Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279
D
BF
The figure of merit for global interconnects with buffer insertion has
the following property:
Setting the derivative of F with respect to W and S to be zero
yield
Optimal Global Interconnect Parameters
for different Technology Nodes
27Dr. Mohamed Abd el Ghany
Department of Electronics and Electrical Engineering
ELCT 1003: High Speed
Electronic Circuits
•Li, X.-C., Mao, J.-F., Huang, H.-F., and Liu, Y.: ‘Global interconnect width and spacing optimization for latency, bandwidth and power dissipation’,
IEEE Transactions on Electron Devices, vol. 52, no. 10, October 2005, pp. 2272–2279