EE241 1 UC Berkeley EE241 B. Nikolic EE241 - Spring 2002 Advanced Digital Integrated Circuits Tu-Th 11 – 12:30pm 203 McLaughlin UC Berkeley EE241 B. Nikolic Practical Information l Instructor: Borivoje Nikolic 570 Cory Hall , 3-9297, [email protected]Office hours: M 11am-12pm, Tu 12:30-1:30pm l Reader: TBA l Admin: Lea Barker 558 Cory Hall, 3-6683, leab@eecs l Class Web page http://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s02
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EE241
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UC Berkeley EE241 B. Nikolic
EE241 - Spring 2002Advanced Digital Integrated Circuits
570 Cory Hall , 3-9297, [email protected] hours: M 11am-12pm, Tu 12:30-1:30pm
l Reader: TBA
l Admin: Lea Barker558 Cory Hall, 3-6683, leab@eecs
l Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s02
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UC Berkeley EE241 B. Nikolic
Class Organizationl +/- 5 assignmentsl 1 term-long design project
» Phase 1: Proposal (by week 3)» Phase 2: Study (report by week 7)» Phase 3: Design (presentation and report
by final week)» Report and presentations last week of
classes
l Final exam
UC Berkeley EE241 B. Nikolic
Class Material
l Textbook: “Design of High-Performance Microprocessor Circuits,” edited by A.Chandrakasan, W. Bowhill, F. Fox
l Must be familiar with “Digital Integrated Circuits - A Design Perspective”, 2nd ed. by J. M. Rabaey, A. Chandrakasan, B. Nikolic
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UC Berkeley EE241 B. Nikolic
Other Booksl Other reference books:
» “High-Speed CMOS Design Styles, by K. Bernstein, et al.
» “Digital Systems Engineering” by W. Dally» “High-Performance System Design: Circuits and
Logic,” by V.G. Oklobdžija» “Low-Power CMOS Design,” by Chandrakasan
and Brodersen» “High-Speed Digital System Design,” by S.H. Hall,
G.W. Hall, J. A. McCall» “Logical Effort: Designing Fast CMOS Circuits,” by
I. Sutherland, B. Sproull, D. Harris
UC Berkeley EE241 B. Nikolic
Class Materiall List of background material available on
web-sitel Selected papers will be made available
on web-site» Protected area, or linked from Inspec
l Papers on http://www.melvyl.ucop.edul Class-notes on web-site
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UC Berkeley EE241 B. Nikolic
Sourcesl IEEE Journal of Solid-State Circuits
(JSSC)l IEEE International Solid-State Circuits
Conference (ISSCC)l Symposium on VLSI Circuits (VLSI)l Other conferences and journals
UC Berkeley EE241 B. Nikolic
Lecture Videosl Lectures are videotapedl Use the microphones when you ask
questions
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UC Berkeley EE241 B. Nikolic
Class Topicsl This course aims to convey a knowledge of advanced concepts of
circuit design for digital LSI and VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, and optimization of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, communications, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.
l SPECIAL FOCUS in SPRING 2002:» Low-power and ‘lower-power’ design» high-performance logic» interconnect» timing» arithmetic circuits» memory
UC Berkeley EE241 B. Nikolic
Class Topics
l Fundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks)
l Design for deep-submicron CMOS - HIGH SPEED (2.5 weeks)» Static CMOS, transistor sizing, buffer design, high-speed CMOS design styles,
dynamic logic
l Design techniques for LOW POWER (2.5 weeks) » analysis of power consumption sources » power minimization at the technology, circuit, and architecture level
l Arithmetic circuits – adders, multipliers (2 weeks) l Driving interconnect, high-speed signaling (2 weeks) l Timing (2 weeks)
High supply currents at low voltage:Challenges: IR drop and L(di/dt) noiseHigh supply currents at low voltage:
Challenges: IR drop and L(di/dt) noise
S. Borkar
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UC Berkeley EE241 B. Nikolic
20nm Power Densityl With Vdd ~1.2V, 20nm devices are quite fast. FO4
delay is <5psl If we continue with today’s architectures, we could
run digital circuits at 30GHz
l But - we will end up with 20kW/cm2 power density.
l Lower supply – to 0.6V, we are down to 5kW/cm2.
l Speeds will be a bit lower, too, FO4 = 10ps, lowering the frequencies to ~10GHz [Tang, ISSCC’01], and lowering power
l Assume that a high performance DG or bulk FET can be designed with 1kW/cm2, with FO4 = 10ps [Frank, Proc IEEE, 3/01]
UC Berkeley EE241 B. Nikolic
Power is a Limiting Factorl If we have 2cm x 2cm die in a high-performance
microprocessor, we will end up with 4kW power dissipation.
l If our power has to be limited to 180W, we can afford to have only 4.5% of these devices with 0.6V supply on the die, given that nothing else dissipates power.
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UC Berkeley EE241 B. Nikolic
Possible Scenariol Example: 0.5 % of devices will be of highest
performancel 35% is leakage (assume: 20% drain, 10% gate, 5%
drain-to-body)l 65% is active power, if just 0.5% of these CV2 = 13W,
leakage 7Wl How would other 99.5% devices that populate the
2cmx2cm die look like?
UC Berkeley EE241 B. Nikolic
Do not increase the die size
0
5
10
15
2025
30
35
40
45
2000 2002 2004 2006 2008Year
Die
Siz
e (m
m)
Will be...
Reduce die size
Restrict die size to ~ 20 mmRestrict die size to ~ 20 mm
S. Borkar
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UC Berkeley EE241 B. Nikolic
Restrict transistor leakage
7 GHz5.5 GHz
4 GHz2.5 Ghz
P6Pentium® proc
48638610
100
1000
10000
1985 1990 1995 2000 2005 2010Year
Fre
qu
ency
(M
hz)
Reduce leakage _ Frequency will not double every 2 yearsReduce leakage _ Frequency will not double every 2 years
S. Borkar
UC Berkeley EE241 B. Nikolic
MicroprocessorsToday → 20nm
µPCore
2GHz
Cache
µPCore
Cache
DedicatedLogic
7-10 GHz
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UC Berkeley EE241 B. Nikolic
Microprocessor Designl Core datapath will be running at 7 - 10GHzl Requires fast devices, low thresholds with 0.5-0.6V
suppliesl Lowest NMOS VTh ~ -0.1V to get swing in CMOS. l Assume threshold of 0 – 0.1V. The devices will be
very leaky, will use second threshold to control leakage power.
l With second threshold set to have 10x less leakage, 90% of devices off critical paths can be made high-threshold.
l Power limits the size of the µP core to 5-10% die (today’s transistor count, just shrunk), 30-50% of total power budget.
UC Berkeley EE241 B. Nikolic
Add Dedicated Datapath
l Will run at 10x lower frequency, at 0.5-0.7 of the processor VDD= 0.25 - 0.35V
l Thresholds for critical paths VTh = 150mVl Need leakage power management – another threshold or
Transistor Requirementsl Will need different kinds of transistors:
» Datapaths (speed, leakage)» Dedicated DSP (power, leakage)» Memory (density is main concern)» Analog (?)
l Power and leakage determine the size ratios between these blocks
l Number of different transistors types is determined by parameter spread
l Less devices could solve the problem, but, need control of the threshold (4th terminal), with strong transfer function.
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UC Berkeley EE241 B. Nikolic
Other design challenges
P6Pentium® proc
486386
28680868085
80808008
40040.001
0.01
0.1
1
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100
1000
10000
1970 1980 1990 2000 2010Year
Lo
gic
Tra
nsi
sto
rs (
MT
)
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25
2000 2002 2004 2006 2008Year
Die
Siz
e (m
m) But core will reduce even further...
Die size will reduce...
l Modest increase in Logic transistors
l “Logic Core” size will decrease
l Tools/methodology for memories
l Interconnect RC may not be that big an issue
UC Berkeley EE241 B. Nikolic
Digital Cellular Market(Phones Shipped)
1996 1997 1998 1999 2000
Units 48M 86M 162M 260M 435M Analog Baseband
Digital Baseband
(DSP + MCU)
PowerManagement
Small Signal RF
PowerRF
(data from Texas Instruments)(data from Texas Instruments)
How about low power devices?
CellPhone
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UC Berkeley EE241 B. Nikolic
Shannon Beats Moore’s Law
1
10
100
1000
10000
100000
1000000
10000000
1980
1984
1988
1992
1996
2000
2004
2008
2012
2016
2020
Algorithmic Complexity(Shannon’s Law)
Battery Capacity
Source: Data compiled from multiple sources
1G
2G
3G Processor Performance (~Moore’s Law)
UC Berkeley EE241 B. Nikolic
A Note on Device Variationsl Threshold separation has to be at least ~70mV (assuming S =
70mV/dec) to be effective in leakage suppressionl If separated too much (>150mV) cannot be used efficiently
(percentage of low VTh devices grows)l High temperature dependencyl Threshold control is criticall Note that dedicated signal processing will be operating under
very low overdrives = large delay dependency on Vth variationl Besides using process, will need to use feedback (substrate
biasing) to controll Hard to do in SOI (Need to have control feature in SOI)
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Device variationsl Random dopant fluctuationsl Feature size, oxide thickness variationsl Measurements of first silicons in 130nm show delay
variations of 5-10% in two identical neighboring paths.
l Variations on a small scale will limit the designsl On larger blocks can use feedback.