1 EE241 - Spring 2013 Advanced Digital Integrated Circuits Lecture 10: SRAM Design Dynamic Margins 2 Announcements Homework 2 due next week Quiz #1 today
1
EE241 - Spring 2013Advanced Digital Integrated Circuits
Lecture 10: SRAM DesignDynamic Margins
2
Announcements
Homework 2 due next week
Quiz #1 today
2
3
Outline
Last lectureSRAM operation, static margins
This lectureFinish static margins,
Dynamic margins
Start assist techniques
SRAM
C. Static Read/Write Margins(continued)
3
5
Write Stability – Write Noise Margin (WNM)
• Writeability is becoming harder with scaling
• Optimizing read stability and writeability at the same time is difficult
AXR
NR
PR
VL VR
VDD
A. Bhavnagarwala, IEDM 2005
6
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0.00E+00 2.00E-08 4.00E-08 6.00E-08 8.00E-08 1.00E-07
Time (s)
Vo
lta
ge
(V
)
WM
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0.00E+00 2.00E-08 4.00E-08 6.00E-08 8.00E-08 1.00E-07
Time (s)
Vo
ltag
e (V
) WM
Highest BL voltage under which write is possible when BLC is kept precharged
BLWL
Write Stability – BL/WL Write Margins
Difference between VDD and lowest WL voltage under which write is possible when both bit-lines are precharged
4
7
Write Stability – Write Current (N-Curve)
C. Wann et al, IEEE VLSI-TSA 2005
Minimum current into the storage node
8H. Pilo, IEDM 2006
5
9
6-T SRAM Static/Dynamic Stability
Read MarginSNM: pessimistic
Write MarginWNM: optimistic
Introduction to dynamic margins
SRAM
D. Dynamic Margins
6
11
Dynamic Write Stability
TA < Twrite < TB
Twrite=dynamic write stability
Static margins are optimistic
Khalil, TVLSI‘08
12
Dynamic Read Stability
TA < Tread < TB
Tread = dynamic read stability
Static margins are pessimistic
Khalil, TVLSI ‘08
7
13
Dynamic Read Access
Khalil, TVLSI ‘08
TA < Taccess < TB
PD1 and PG1 are critical
Slide 13
14
VTh Window
Assuming global spread
0.1
0.2
0.3
0.4
0.5
0.6
0.7
pMO
S V th
(V)
Read limit
1.0 V
Read limit
Write limit65 nm
ss
ff sf
fs
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.1 0.2 0.3 0.4 0.5 0.6 0.7
130 nm
nMOS Vth (V) nMOS Vth (V)
Write limit
ss
ff sf
fs
0.8 V
Yamaoka, ISSCC’05
8
SRAM
E. Assist Techniques
16
Peripheral Circuits to Help SRAM
Write assist techniques
Read assist techniques
Redundancy
ECC
9
17
Multi-Voltage SRAM
Read Write Retention
Periphery Vmin Vmin Vmin
BL Precharge
Vmin (H) Vmin (L) Vmin
WL Vmin Vmax N/A
Cell VDD Vmax Vmin Vmin
WL
BL
AXL‘1’ ‘0’
AXR
NRNL
PRPL
BL
VDD
18
Array Adjustments
S. Mukhopadhyay, VLSI 2006
Array back bias, to compensate for systematic variations
May be useful in technologies with strong body effect
10
19
Dynamic VDD Implementation
VCC selection is along column direction to decouple the read & write
VCC_lo
cell cell cell cell cellWL
cell cell cell cell cellWL
MUX (8:1)
W R R R
cellcell cellcell cellcell cellcell cellcellWL
cellcell cellcell cellcell cellcell
VCC_hiMUX MUX MUX MUX MUX
BI MUX
VCC MUX
Zhang, ISSCC’05
20
Floating VDD Technique
W/o second supply
Vdd
Memory cell
“H” “L”
Memory cell
“H” “L”
WL
Switch (off)“L” “H” Vddm Vddm
Switch (on)
Yamaoka, ISSCC’04
11
21
Collapsing VDD Technique
E. Karl, ISSCC’12
22
Collapsing VDD Technique
E. Karl, ISSCC’12
12
23
Negative BL
Nii, VLSI’08
0V0V
Negative bias gen Din
24
Negative BL
Arsovski, ISSCC’11
13
25
BL Stability Assist
Arsovski, ISSCC’11
26
WL Underdrive
Sensing appropriate WL voltage
Carlson, CICC’08Nho, ISSCC’10
14
27
Capacitive Write Assist
S. Ohbayashi, VLSI 2006
28
Write/Read Assist
H.Pilo, VLSI 2006
15
29
Pulsed WL/BL
M.Khellah, VLSI 2006
30
Next Lecture
Continue with SRAM