1 EE241 - Spring 2005 Advanced Digital Integrated Circuits Lecture 6: Optimization for Performance 2 Admin Project proposals due by Fr 5pm (by e-mail to Huifang and myself) Title Short abstract of 10-15 lines describing the problem you are trying to address Special office hours today right after class (3:30- 4:30pm) Some feedback on ISSCC? What did catch your eye?
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EE241 - Spring 2005Advanced Digital Integrated Circuits
Lecture 6:Optimization for Performance
2
Admin
Project proposals due by Fr 5pm (by e-mail to Huifangand myself)
Title
Short abstract of 10-15 lines describing the problem you are trying to address
Special office hours today right after class (3:30-4:30pm)
Some feedback on ISSCC? What did catch your eye?
2
3
Today’s lecture
Using the models we have created so far to do create an environment for optimization
Reading:ICCAD paper by Stojanovic et al.
Chapters 2 and 3 in the text by K. Bernstein (High Speed CMOS Design Styles)
Background material from Rabaey, 2nd ed, Chapters 5, 6.
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Static Timing Analysis
Computing critical (longest) path delayLongest path algorithm on DAG [Kirkpatrick, IBM Jo. R&D, 1966]
Used in most ASIC designs today
LimitationsFalse paths
Simultaneous arrival times
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5
Signal Arrival Times
NAND gate:
1
6
Signal Arrival Times
NAND gate:
1
4
7
Simultaneous Arrival Times
NAND gate:
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Impact of Arrival Times
A
B
Delay
0 tA - tB
A arrives early B arrives early
Up to 25%
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9
Optimization for Performance
Performance critical blocks
Start with a synthesized designEasier to explore architectures
Frequently, input capacitance of a logic path is constrainedLogic has to drive some capacitanceExample: ALU load in an Intel’s microprocessor is > 0.5pFHow do we size the ALU datapath to achieve maximum speed?Review the method of logical effort
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15
Inverter Chain
CL
If CL and CIn are given:- How many stages are needed to minimize the delay?- How to size the inverters?
Normalize everything to an inverter:ginv =1, pinv = 1
Divide everything by τinv
(everything is measured in unit delays τinv)Assume γ = 1.
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Delay in a Logic Gate
Gate delay:
d = h + p
effort delay intrinsic delay
Effort delay:
h = g f
logical effort effective fanout = Cout/Cin
Logical effort is a function of topology, independent of sizingEffective fanout (electrical effort) is a function of load/gate size
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Logical Effort
Inverter has the smallest logical effort and intrinsic delay of all static CMOS gatesLogical effort of a gate presents the ratio of its input capacitance to the inverter capacitance when sized to deliver the same current
Logical effort increases with the gate complexity
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Logical Effort
Logical effort is the ratio of input capacitance of a gate to the inputcapacitance of an inverter with the same output current
g = 1 g = g =
Size factor:1.8Size factor:1.5
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Logical Effort of Gates
Fan-out (f)
Nor
mal
ized
del
ay (
d)
t
1 2 3 4 5 6 7
pINV
t pNAND
F(Fan-in)
g=p=d=
g=p=d=
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Logical Effort of Gates
Fan-out (f)
Nor
mal
ized
del
ay (
d)t
1 2 3 4 5 6 7
pINVtpNAND
F(Fan-in)
g=1p=1d=f+1
g=3.5/3p=5.5/3d=(3.5/3)f+1.8
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Add Branching Effort
Branching effort:
pathon
pathoffpathon
C
CCb
−
−− +=
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Multistage Networks
Stage effort: hi = gifi
Path electrical effort: F = Cout/Cin
Path logical effort: G = g1g2…gN
Branching effort: B = b1b2…bN
Path effort: H = GFB
Path delay D = Σdi = Σpi + Σhi
( )∑=
⋅+=N
iiii fgpDelay
1
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Optimum Effort per Stage
HhN =
When each stage bears the same effort:
N Hh =
( ) PNHpfgD Niii +=+=∑ /1ˆ
Minimum path delay
Effective fanout of each stage: ii ghf =
Stage efforts: g1f1 = g2f2 = … = gNfN
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Optimal Number of Stages
For a given load, and given input capacitance of the first gateFind optimal number of stages and optimal sizing
PNHD N += /1
( ) 0ln /1/1/1 =++−=∂∂
PHHHND NNN
NHhˆ/1=Substitute ‘best stage effort’
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Logical Effort Optimization Methodology
For smaller problems, easy to translate into set of analytical expressions
Feed them into Matlab optimizerWith some careful manipulations, can be turned into a convex optimization problem (Stojanovic)