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EE241
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UC Berkeley EE241 B. Nikolić
EE241 - Spring 2001Advanced Digital Integrated Circuits
� Class Web pagehttp://bwrc.eecs.berkeley.edu/classes/icdesign/ee241_s01
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UC Berkeley EE241 B. Nikolić
Class Organization� +/- 5 assignments� 1 term-long design project
» Phase 1: Proposal (by week 3)» Phase 2: Study (report by week 7)» Phase 3: Design (presentation and report
by final week)» Report and presentations last week of
classes� Final exam
UC Berkeley EE241 B. Nikolić
Class Material
� Textbook: “Design of High-Performance Microprocessor Circuits,” by A.Chandrakasan, W. Bowhill, F. Fox
� Must be familiar with “Digital Integrated Circuits - A Design Perspective”, by J. M.Rabaey
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UC Berkeley EE241 B. Nikolić
Other Books� Other reference books:
» “High-Speed CMOS Design Styles, by K. Bernstein, et al.
» “Digital Systems Engineering” by W. Dally» “High-Performance System Design: Circuits and
Logic,” by V.G. Oklobdžija» “Low-Power CMOS Design,” by Chandrakasan
and Brodersen» “High-Speed Digital System Design,” by S.H. Hall,
G.W. Hall, J. A. McCall» “Logical Effort: Designing Fast CMOS Circuits,” by
I. Sutherland, B. Sproull, D. Harris
UC Berkeley EE241 B. Nikolić
Class Material� List of background material available on
web-site� Selected papers will be made available
on web-site» Protected area, or linked from Inspec
� Papers on http://www.melvyl.ucop.edu� Class-notes on web-site
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UC Berkeley EE241 B. Nikolić
Sources� IEEE Journal of Solid-State Circuits
(JSSC)� IEEE International Solid-State Circuits
Conference (ISSCC)� Symposium on VLSI Circuits (VLSI)� Other conferences and journals
UC Berkeley EE241 B. Nikolić
Lectures online� The class is webcasted:
» http://bmrc.berkeley.edu/bibs/� It is also videotaped� So use the microphones when you ask
questions
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UC Berkeley EE241 B. Nikolić
Class Topics� This course aims to convey a knowledge of advanced concepts of
circuit design for digital LSI and VLSI components in state of the art MOS technologies. Emphasis is on the circuit design, optimization, and layout of either very high speed, high density or low power circuits for use in applications such as micro-processors, signal and multimedia processors, memory and periphery. Special attention will devoted to the most important challenges facing digital circuit designers today and in the coming decade, being the impact of scaling, deep sub-micron effects, interconnect, signal integrity, power distribution and consumption, and timing.
� SPECIAL FOCUS in SPRING 2001:» high-performance low-power logic (as needed for digital radio)» interconnect» timing» arithmetic circuits» memory
UC Berkeley EE241 B. Nikolić
Class Topics
� Fundamentals - Technology and modeling – Scaling and limits of scaling (1.5 weeks)
� Design for deep-submicron CMOS - HIGH SPEED (3 weeks)» Static CMOS, transistor sizing, buffer design, high-speed CMOS design styles,
dynamic logic � Design techniques for LOW POWER (2 weeks)
» analysis of power consumption sources » power minimization at the technology, circuit, and architecture level
Use > 50% die area in memoryUse > 50% die area in memory
S. Borkar
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UC Berkeley EE241 B. Nikolić
Total memory meets trend
2.5M
5.5M
12M
24M
16168
0
1M
1
10
100
1000
10000
100000
1980 1990 2000 2010Year
Mem
ory
(KB
)
S. Borkar
UC Berkeley EE241 B. Nikolić
Power density is reduced
400480088080
8085
8086
286 386486
Pentium ® procP6
1
10
100
1000
10000
1970 1980 1990 2000 2010Year
Pow
er D
ensi
ty (W
/cm
2)
Hot Plate
NuclearReactor
RocketNozzle
Full chip power density is reducedBut local power density will be highFull chip power density is reducedBut local power density will be high
S. Borkar
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UC Berkeley EE241 B. Nikolić
Still obey Moore’s Law!
Year
10
100
1,000
10,000
2000 2002 2004 2006 2008
Tran
sist
ors
(MT) Moore's Law.
Actual
Total transistors meet Moore’s LawTotal transistors meet Moore’s Law
S. Borkar
UC Berkeley EE241 B. Nikolić
Too good to be true...� Reduced transistor leakage� Reduced frequency� Decreased die size� Increased memory, but reduced logic� Does it deliver expected performance?
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UC Berkeley EE241 B. Nikolić
Reduced die size causes “Performance gap”
0%
35%
47%53%
59%
0%
10%
20%
30%
40%
50%
60%
70%
2000 2002 2004 2006 2008Year
Perf
orm
ance
Gap
30-60% performance loss even after meeting Moore’s Law30-60% performance loss even after meeting Moore’s Law
S. Borkar
UC Berkeley EE241 B. Nikolić
0
200
400
600
800
Pentiumproc
PentiumPro Proc
PentiumIII proc
Inst
ruct
ion
Cos
t External Mem Latency
Large caches could improve performance
1
10
100
1000
L0 L1 L2 External Mem
Cac
he L
aten
cy (C
lock
s)
0
1
10
100
L0 L1 L2
Rel
ativ
e B
andw
idth
Source: Glenn Hinton, 99
Large on die caches provide:1. Increased Data Bandwidth2. Reduced Latency