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EE1411
F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
ECE 224a ECE 224a Process and Design RulesProcess and Design Rules
F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
A Modern CMOS ProcessA Modern CMOS Process
p-well n-well
p+
p-epi
SiO2
AlCu
poly
n+
SiO2
p+
gate-oxide
Tungsten
TiSi2
Dual-Well Trench-Isolated CMOS ProcessDual-Well Trench-Isolated CMOS Process
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
The Manufacturing ProcessThe Manufacturing Process
Photo-Lithography Mask to Resist Resist to Pattern Layer Process (Implant/Etch/Oxide/Nitride/…) Cleanup (Clean/Planarization/Anneal) Setup next Layer for Processing
For a great reference source:http://www.reed-electronics.com/semiconductor
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
oxidation
opticalmask
processstep
photoresist coatingphotoresistremoval (ashing)
spin, rinse, dryacid etch
photoresist
stepper exposure
development
Typical operations in a single photolithographic cycle (from [Fullman]).
Photo-Lithographic ProcessPhoto-Lithographic Process
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
Patterning of SiO2Patterning of SiO2
Si-substrate
Si-substrate Si-substrate
(a) Silicon base material
(b) After oxidation and depositionof negative photoresist
(c) Stepper exposure
PhotoresistSiO2
UV-light
Patternedoptical mask
Exposed resist
SiO2
Si-substrate
Si-substrate
Si-substrate
SiO2
SiO2
(d) After development and etching of resist,chemical or plasma etch of SiO2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Hardened resist
Chemical or plasmaetch
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
CMOS Process Walk-ThroughCMOS Process Walk-Through
p+
p-epi (a) Base material: p+ substrate with p-epi layer
p+
(c) After plasma etch of insulatingtrenches using the inverse of the active area mask
p+
p-epiSiO2
3SiN
4
(b) After deposition of gate-oxide andsacrificial nitride (acts as abuffer layer)
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
CMOS Process Walk-ThroughCMOS Process Walk-ThroughSiO2
(d) After trench filling, CMP planarization, and removal of sacrificial nitride
(e) After n-well and VTp adjust implants
n
(f) After p-well andVTn adjust implants
p
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
CMOS Process Walk-ThroughCMOS Process Walk-Through
(g) After polysilicon depositionand etch
poly(silicon)
(h) After n+ source/drain andp+ source/drain implants. These
p+n+
steps also dope the polysilicon.
(i) After deposition of SiO2insulator and contact hole etch.
SiO2
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
CMOS Process Walk-ThroughCMOS Process Walk-Through
(j) After deposition and patterning of first Al layer.
Al
(k) After deposition of SiO2insulator, etching of via’s,
deposition and patterning ofsecond layer of Al.
AlSiO2
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
Package TypesPackage Types
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
Package ParametersPackage Parameters
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
Multi-Chip ModulesMulti-Chip Modules
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F. Brewer, adapted from MOSIS Data, Digital Integrated Circuits2nd Manufacturing
Lecture Problems 2Lecture Problems 21. Why is there a spacing rule between via’s and contacts and/or vias
and other vias? How is it eliminated in deeper (smaller) processes?2. Draw a schematic and stick layout for a 3-input 2-output adder cell
(output is sum and carry). Design as two cells: a cell producing ~Cout and another cell producing Sout(a,b,c,~Cout). Design Sue schematics and Max Layout for the two cells with minimum size transistors and turn in check plots.
3. Guard Rings consist of n and p contact regions with continuous metal connections. They are often used to surround and isolate sensitive devices. How do they work?
4. Very wide metal (any layer) in most technologies needs to have slots cut in it. Why?
5. Explain the relation between CMP planarization and metal/poly density rules.
6. Draw schematics and stick layouts for a 2 of 4 majority gate (true if two or more of its inputs are False). Do two designs, one to minimize transistors, and one where the inputs arrive in order:a,b,c,d last ti minimize the critical path.