EE 5900 Advanced EE 5900 Advanced Algorithms for Robust Algorithms for Robust VLSI CAD, Spring 2009 VLSI CAD, Spring 2009 Static Timing Analysis and Static Timing Analysis and Gate Sizing Gate Sizing
Jan 12, 2016
EE 5900 Advanced EE 5900 Advanced Algorithms for Robust Algorithms for Robust VLSI CAD, Spring 2009VLSI CAD, Spring 2009
Static Timing Analysis and Gate Static Timing Analysis and Gate SizingSizing
2023.04.21 PJF- 2Circuit Delay
Delay EvaluationDelay Evaluation
1. 1. Gate delayGate delay 2. Interconnect delay2. Interconnect delay
2023.04.21 PJF- 3Circuit Delay
1. 1. Problem DescriptionProblem Description
Given a pair of pins, compute pin-to-Given a pair of pins, compute pin-to-pin delay and possibly output pin delay and possibly output waveformwaveform
Cell Cell
Delay
Interconnect
Cell…
2023.04.21 PJF- 4Circuit Delay
Circuit ModelCircuit Model
For an inverterFor an inverter
Csink
Csink
…
…
2023.04.21 PJF- 5Circuit Delay
Sink CapacitanceSink Capacitance
Gate capacitance, input Gate capacitance, input capacitancecapacitance
Given for standard cellsGiven for standard cells Can be found using SPICECan be found using SPICE
Apply an AC voltage and Apply an AC voltage and measure currentmeasure current
Average over a range of Average over a range of frequencyfrequency
I
2023.04.21 PJF- 6Circuit Delay
Capacitance ModelCapacitance Model
CtotalRdRd
RC
2023.04.21 PJF- 7Circuit Delay
Interconnect Delay: Elmore Interconnect Delay: Elmore DelayDelay
Elmore is used as the delay on Elmore is used as the delay on interconnectinterconnect
Easy to computeEasy to compute
2023.04.21 PJF- 8Circuit Delay
ExampleExample
1
1 1
1
1
1
1
1
42 31
m1_1= –4, m1_2= –7, m1_3= –8, m1_4= –8
2023.04.21 PJF- 9Circuit Delay
Application of Elmore DelayApplication of Elmore Delay
GoodGood Closed form expression, easy to Closed form expression, easy to
computecompute Useful in circuit design such as gate Useful in circuit design such as gate
sizing and buffering.sizing and buffering. BadBad
InaccurateInaccurate Not useful for timing verificationNot useful for timing verification
2023.04.21 PJF- 10Circuit Delay
Circuit Delay Evaluation - Circuit Delay Evaluation - Two ComponentsTwo Components
Cell delay + interconnect delayCell delay + interconnect delay Cell delay is computed using RC or K-Cell delay is computed using RC or K-
factorfactor Interconnect delay is computed Interconnect delay is computed
using Elmore delayusing Elmore delay
Cell CellInterconnect
2023.04.21 PJF- 11Circuit Delay
Static vs. Dynamic Timing Static vs. Dynamic Timing AnalysisAnalysis
Static timing analysisStatic timing analysis FastFast Consider all pathsConsider all paths Pessimism by Pessimism by
considering false paths considering false paths which are never which are never exercisedexercised
Dynamic timing analysis Dynamic timing analysis ( simulation ) ( simulation ) Depends on input Depends on input
stimulus vectorsstimulus vectors Do not report timing on Do not report timing on
false pathsfalse paths With large number of With large number of
testing vectorstesting vectors AccurateAccurate SlowSlow
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Wire and Gate ModelsWire and Gate Models
l
hB
r l
h0
rB
c h l( )
2c h l( )
2
CB
Step by StepStep by Step
2023.04.21 PJF- 13Circuit Delay
Model combinational circuit using the Model combinational circuit using the previous slideprevious slide
Starting from primary input gates, Starting from primary input gates, compute the arrival time (AT) at each compute the arrival time (AT) at each gate, i.e., compute gate delay and gate, i.e., compute gate delay and interconnect delayinterconnect delay
In order to compute the AT at a gate, the In order to compute the AT at a gate, the ATs of all its input gates need to be ATs of all its input gates need to be computedcomputed
Repeat the above process until the ATs at Repeat the above process until the ATs at all primary output gates are computedall primary output gates are computed
2023.04.21 PJF- 14Circuit Delay
Example of Static Timing Example of Static Timing AnalysisAnalysis
Arrival time (AT): input -> output, take maxArrival time (AT): input -> output, take max
C=1,R=1
C=5,R=2
C=5,R=2
C=4,R=2 C=10,R=5
unit wire resistance=1unit wire capacitance=1
10
2
2
12
2AT=0
AT=267AT=75
AT=145
AT=22
AT=31
AT=0
AT=121
AT=21
AT=167
AT=267
AT=12Take the
MaxAT=31
1
3
2
4
5
2023.04.21 PJF- 15Circuit Delay
Timing OptimizationTiming Optimization
Arrival time (AT): input -> output, take maxArrival time (AT): input -> output, take max
Should we size up this gate to improve timing?
C=1,R=1
C=5,R=2
C=5,R=2
C=4,R=2 C=10,R=5
unit wire resistance=1unit wire capacitance=1
10
2
2
12
2AT=0
AT=267AT=75
AT=145
AT=22
AT=31
AT=0
AT=121
AT=21
AT=167
AT=267
AT=12Take the
MaxAT=31
2023.04.21 PJF- 16Circuit Delay
Timing Optimization- IITiming Optimization- II Suppose that we have a gate (with Suppose that we have a gate (with
same gate type) doubling its width. We same gate type) doubling its width. We roughly have C=10, R=1.roughly have C=10, R=1.
If we change the gate with this new one, If we change the gate with this new one, what is the new delay? Does not changewhat is the new delay? Does not change
C=1,R=1
C=10,R=1
C=5,R=2
C=4,R=2 C=10,R=5
unit wire resistance=1unit wire capacitance=1
10
2
2
12
2AT=0
AT=267AT=75
AT=145
AT=16
AT=31
AT=0
AT=121
AT=21
AT=167
AT=267
AT=6Take the
MaxAT=31
2023.04.21 PJF- 17Circuit Delay
Timing Optimization- IIITiming Optimization- III Suppose that we have a gate (with Suppose that we have a gate (with
same gate type) doubling its width. We same gate type) doubling its width. We roughly have C=8, R=1.roughly have C=8, R=1.
If we change the gate with this new one, If we change the gate with this new one, what is the new delay?what is the new delay?C=1,R=1
C=5,R=2
C=5,R=2
C=8,R=1 C=10,R=5
unit wire resistance=1unit wire capacitance=1
10
2
2
12
2AT=0
AT=257AT=65
AT=149
AT=38
AT=43
AT=0
AT=125
AT=25
AT=171
AT=257
AT=20Take the
MaxAT=43
2023.04.21 PJF- 18Circuit Delay
Timing Optimization- IVTiming Optimization- IV This optimization is called gate sizing. This optimization is called gate sizing.
Change the gate size (width) in Change the gate size (width) in optimization.optimization.
1. Given multiple choices 1. Given multiple choices (implementations) per gate type, find a (implementations) per gate type, find a gate implementation at each gate such gate implementation at each gate such that the circuit timing is minimized.that the circuit timing is minimized.
2. Given multiple choices per gate type, 2. Given multiple choices per gate type, find a gate implementation at each gate find a gate implementation at each gate such that the circuit timing satisfies the such that the circuit timing satisfies the target and the total gate area/power is target and the total gate area/power is minimizedminimized
Problem Definition of Gate Problem Definition of Gate SizingSizing
Given a timing (delay) target, use Given a timing (delay) target, use smallest power/area gates to meet smallest power/area gates to meet the timing targetthe timing target
In general, smaller power -> larger In general, smaller power -> larger timing, smaller timing -> larger timing, smaller timing -> larger power.power.
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Delay due to Gate SizingDelay due to Gate Sizing
Suppose that unit width gate capacitance Suppose that unit width gate capacitance is c and unit width gate resistance is r. is c and unit width gate resistance is r. Given gate size wGiven gate size wi,i,
Gate size wGate size wii: R : R r/w r/wii, C , C cw cwii
Delay is a function of RCDelay is a function of RC Delay Delay R RiiCCjj w wii/w/wjj
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Wire and Gate ModelsWire and Gate Models
l
hB
r l
h0
rB
c h l( )
2c h l( )
2
CB
22
Combinatorial Circuit ModelCombinatorial Circuit Model
Gate size variables xGate size variables x11, x, x22, x, x33
Delay on each gate depends on xDelay on each gate depends on x
Drivers Loads
x2x3
x1 a3
a4a5
a1
a2
D1
D3
D2D5
D4
D7
D6
D9D8D10
a6
a7
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Path DelayPath Delay
Express path delay in Express path delay in terms of component terms of component delaydelay
A component can be A component can be a gate or a wirea gate or a wire
Delay D for each Delay D for each componentcomponent
Arrival time aArrival time a for for some componentssome components
7105
5984
5973
663
4532
3422
3411
aDa
aDDa
aDDa
aDa
aDDa
aDDa
aDDa
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Gate SizingGate Sizing Power/area minimization under delay constraints:Power/area minimization under delay constraints:
This can be solved efficiently using gpsolveThis can be solved efficiently using gpsolve
gateeach on sizelargest andsmallest
)( and
target timing theis output,primary Subject to
Minimize1
iUxL
iinputjiaDa
AjAa
x
iii
iij
maxmaxj
n
i ii
Gate Sizing using GPSOLVEGate Sizing using GPSOLVE
Follow the steps in gatesizing.mFollow the steps in gatesizing.m
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