CPE/EE 421 Microcomputers - UAH - Engineering ...milenka/cpe421-04S/lectures/cpe421-s20p4...Alexander Milenkovich 1 CPE/EE 421/521 Microcomputers 1 U A H CPE/EE 421 Microcomputers

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CPE/EE 421Microcomputers

THE 68000 CPU HARDWARE MODEL

Instructor: Dr Aleksandar MilenkovicLecture Notes

(S20)

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THE 68000 CPU HARDWARE MODELChapter 4

Ø 68000 interface

Ø Timing diagram

Ø Minimal configuration using the 68000

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HTiming Example

Ø 68000 clock 8 MHz tCYC = 125 ns

Ø 68000 CPU tCLAV = 70 ns

Ø 68000 CPU tDICL = 15 ns

Ø What is the minimum tacc?

Ø 3 tCYC = tCLAV + tacc + tDICL

Ø 375 = 70 + tacc + 15

Ø tacc = 290 ns

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Figure 4.14

A 68000 Read Cycle

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HFigure 4.15

Extended Read Cycle

DTACK* did not go low at least 20ns before the falling edge of state S4

v Designer has to provide logic to control DTACK*

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Figure 4.18

Memory Timing Diagram

Ø The 6116 static memory componentv 2K x 8bit memory – byte -oriented!

v Two 6116’s configured in parallel to allow word accesses

v Eleven address inputs

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Figure 4.17

Ø Assumptions:v R/W* is high for the duration of the read cyclev OE* is low

Memory Timing Diagram, cont’d

(min 200ns – address stable)

(max 200ns)

(max 15ns)

Data is floating

(max 50ns)

(usually derived from UDS*/LDS*)

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HD00

D07

D08

D15

A12

A23

A01

A11

A01

A11

A01

A11

Figure 4.19

Connect

ing T

he 6

116 R

AM

to a

68000 C

PU

No operation111100Lower byte read010100Upper byte read101000

Word read000000No operation11XX1XNo operation11XXX1OperationCS2*CS1*LDS*UDS*RAMCS*AS*

OutputsInputs

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Figure 4.20

Connect

ing T

he 6

116 R

AM

to a

68000 C

PU

Tim

ing D

iagra

m

Turnoff time70+10+60 =

140ns

70ns

10ns

60ns

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HTiming Example

Ø 68000 clock 8 MHz tCYC = 125 nsv 68000 CPU tCLAV = 70 ns

v 68000 CPU tDICL = 15 nsv What is the minimum tacc?

v 3 × t CYC > tCLAV + tacc + tDICL

v 375 > 70 + tacc + 15v tacc < 290 ns (or t AA from the timing diagram, access time)

Ø For the 12.5MHz version of 68000 tCYC = 80 nsv 68000 CPU tCLAV = 55 ns

v 68000 CPU tDICL = 10 ns

v 3×80 > 55 + tacc + 10v tacc < 175 ns

Ø Remember, maximum tAA for the 6116 RAM was 200 ns

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68000 Write Cycle

Ø 68000 transmits a byte or a word to memory or a peripheral

Ø Essential differences:v The CPU provides data at the beginning of a write cycle

v One of the bus slaves (see later) reads the data

Ø In a read cycle DS* and AS* were asserted concurrentlyThis will be not a case here!

Ø Reason for that: 68000 asserts DS* only when the contents of data bus have stabilizedv Therefore, memory can use UDS*/LDS* to latch data from

the CPU

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HSimplified write cycle timing diagram

In a write cycle: UDS*/LDS* is asserted

one cycle after AS*

Figure 4.22

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HFigure 4.23

Ø Follow this sequence of events in a write cycle:v Address

stablev AS* asserted

v R/W* brought low

v Data validv DS* asserted

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Figure 4.24

Write Cycle Timing Diagram of a 6116 RAM

Address setup time(min 20ns)

Address valid to end of write(min 120ns)

Write pulse width(min 90ns)

Write recovery time(min 10ns)

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HWrite Cycle Timing Diagram of a 6116 RAM, cont’d

Ø Write cycle ends with either CS* or WE* being negated (CS* and WE* internally combined)

Ø An address must be valid for at least tAS nanoseconds before WE* is asserted

Ø Must remain valid for at least tWR nanoseconds after WE* is negated

Ø Data from the CPU must be valid for at least tDW nanoseconds before WE* is negated

Ø Must remain valid for at least tDH nanoseconds after the end of the cycle

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HDesigning a Memory Subsystem, an example

Ø Design a M68000 memory subsystem usingv Two 32K × 8 RAM chips residing at address $ 00 8000

v Two 8K × 8 RAM chips residing in the consecutive window

v LS 138 (3 to 8 decoder) and basic logic gates

Ø Solutionv 32K is 4 × 8K

=> Let’s split the address space into 8K modulesv In total, we have five (4+1) 8K windows

v To address each line in 8K window => 13 bits (23*210 = 213 = 8K)

v To address five modules we need 3 bitsv Don’t forget that there is no A0, we will use LDS/UDS

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HDesigning a Memory Subsystem, an example

A Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

B

C

LS138

E1

E2

E3

A14

A16

A15

AS*

LDS*

A17

A23

...

R1CSL*

RAM2*Vcc

RAM1*

UDS*

R2CSL*

R1CSU*

R2CSU*

A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A09 A08 A07 A06 A05 A04 A03 A02 A01 A00

address within 8K module module address

UDS LDS

0 0 8 0 0 0

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HDesigning a Memory Subsystem, an example

RAM32Kx8

A 0

A14

...

CE*

OE*

D0

D7

D6

D5

D4

D3

D2

D1

RAM32Kx8

A 0

A14

...

CE*

OE*

D0

D7

D6

D5

D4

D3

D2

D1

RAM8Kx8

A 0

A12

...

CE*

OE*

D0

D7

D6

D5

D4

D3

D2

D1

WE*

A13

A1

A15

A1

D7

D6D5

D4D3

D2D1

D0

A1..A23

A15

A1

D0..D15

R/W*

R1CSL* R1CSLU*

R2CSL* R2CSLU*

RAM8Kx8

A0

A12

...

CE*

OE*

D0

D7

D6

D5

D4

D3

D2

D1

WE*

A13

A 1

R/W*

WE*R/W* WE*R/W*

D7

D6

D5D4

D3D2

D1D0

D15

D14D13

D12D11

D10D9

D8

D15D14

D13

D12D11

D10

D9D8

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Figure 4.9

Interrupt Control Interface (details later)

priority

low

high

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Data bus

Address bus

Control bus

Arbitration bus

Slave module

Memory

Master module

Local memory

CPU

I/O

Master module

Local memory

CPU

I/O

Bus Arbitration ControlØ When 68000 controls the address and data buses, we call it the

bus master

Ø The 68000 may allow another 68000 or DMA controller to take control over buses

Ø In the system with only one bus master, 68000 would have permanent control of the address and data buses

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HBus Arbitration Control, cont’d

Ø 68000 must respond to BR* request (it cannot be masked)

Ø Assertion of BG* indicates that the bus will be given up at the end of present bus cycle

Ø Requesting device waits until AS*, DTACK*, and BGACK* have been negated, and only then asserts its own BGACK* output

Ø Old master negates its BG*, and BR* can be asserted by another potential master

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Figure 4.27a

Data Bus Contention in Microcomputers

Ø Situation where more than one device attempts to drive the bus simultaneously

Ø Example: Two memory modules, M1 selected during read cycle 1, M2 selected during read cycle 2

Ø Assumption: v M1 has data bus drivers with relatively long turn-off timesv M2 has data bus drivers with relatively short turn-on times

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Long turn -off time

Data Bus Contention in Microcomputers, cont’d

Short turn-on time

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HBus Contention and Data Bus Transceivers

Ø Data bus transceiver – consists of a transmitter (driver) and a receiver

Ø Driver – tristate output, can be driven high, low, or internally disconnected form the rest of the circuit

Ø Two control inputs: Enable (active low) and DIR (direction)

Ø Dynamic data bus contention