www.flextiles.eu FlexTiles D a t e / R e f e r e n c e Dynamically Reconfigurable Embedded FPGA System 2 1 / 5 / 2 0 1 3 2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS’14) FlexTiles Workshop - July 18 th 2014 Antoine COURTAY , Olivier SENTIEYS ★ , Christophe HURIAUX University of Rennes 1 ★ Inria
Conference on Adaptive Hardware and Systems (AHS'14) - The FlexTiles Embedded FPGA
Jun 19, 2015
The FP7 FlexTiles Project will provide tools for building a 3D SoC chip. This chip has an FPGA embedded and these slides will explain the ideas and how we will make it a re-configurable fabric like never seen before
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www.flextiles.eu
FlexTiles
Da
te /R
efe
renc
e
Dynamically Reconfigurable Embedded FPGA System
21/5
/201
3
2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS’14)
FlexTiles Workshop - July 18th 2014
Antoine COURTAY, Olivier SENTIEYS★, Christophe HURIAUX
University of Rennes 1★ Inria
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Outline
eFPGA Reconfigurable Fabric General architecture overview
Expected features
Task migration in FPGA vs. task migration in eFPGA
Efficient hardware task swapping
eFPGA architecture
Virtual Bit-Stream
What about heterogeneous blocks ?
Development flow
Results & conclusion
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General Architecture Overview
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Expected Features
Main expected features
Low reconfiguration time (and power) overhead Low complexity reconfiguration control Resource sharing/distribution easiness, simplified task migration
No predefined configuration domains
Smaller bit-stream size in configuration memory Virtual Bit-Stream (VBS)
In contrast to state-of-the-art FPGA
No predefined reconfigurable regions Bit-stream independent from task location
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Task Allocation & Migration in FPGA
Predefined reconfigurable regions
Bit-stream depends on task location
I/O I/O I/O I/O I/O I/O I/O
I/O I/O I/O I/O I/O I/O I/O
I/OI/O
I/OI/O
I/OI/O
I/OI/O
I/OI/O
I/OI/O
I/OI/O
I/OI/O
I/O
I/O
HW Accelerator #1
BS #1
HW Accelerator #1
BS #2
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Task Migration in eFPGA
3D NI3D NI
3D NI3D NI
RAM RAM RAM RAM
RAM RAM RAM RAM
3D NI3D NI
3D NI
3D NI
3D NI
3D NI
3D NI
3D NI
3D NI
3D NI
3D NI
HW Accelerator #2
BS #2
HW Accelerator #1
BS #1
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Efficient Hardware Task Swapping
Hiding reconfiguration time with computing
Single-context memory
Double-context memory
eFPGA will use double-context memory
Gain in dynamic reconfiguration efficiency
At the cost of ~50% overhead
Task 1 Task 2time
Cfg. 2Cfg. 1
Task 1 Task 2time
Cfg. 2Cfg. 1
CB
FF
ConfClk Latch
ConfEn
CB
CB: one configuration bit
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eFPGA Architecture
Logic Block
Switch Block
LUTCLBIN
ScanIn
FF
mux
CB
ScanOut
CLBOUT
clk,rstbCB
CB
CBC
B
C B
CB C
B
CB
NORTH(i)
SOUTH(i)
EAST(i)WEST(i)
ScanIn
ScanOut
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eFPGA Architecture
Interconnection Block
CLBIN[1]
CLBIN[2]
CLBIN[3] CLBOUT
CLBIN[0]
NORTH0 1 2 3
0 1 2 3SOUTH
0 1 2 3W
EST
EAST0 1 2 3
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eFPGA Architecture
eFPGA macroCHANY
(i,j+1)
SB
(i-1,j)
CHANX
(i+1,j)
CLB
(i+1,j)
SB
(i,j-1)
SB(i,j)
CLB
(i,j+1)
CLB
(i,j)
CLBIN[1]
CLBIN[2]CLBIN[0]
CLBIN[3] CLBOUT
CHANX(i,j)
CHANY(i,j)
CLBIN[3] CLBOUT
CLBIN[0]
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Outline
eFPGA Reconfigurable Fabric
Virtual Bit-Stream Virtual Bit-Stream overview
Interconnection architecture
Routing details abstraction
Results
What about heterogeneous blocks ?
Development flow
Results & conclusion
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eFPGA Architecture using VBS
Reconfiguration controller finalizes VBS
Reconfigurationcontroller
Externalmemory
VBS1
VBS2
VBS3
VBSN
… Buffermemory
data
control
1
2
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Interconnection Architecture
Hiding routing details
Full BS is 129 bits Could be reduced by giving
less details
CLBIN[1]
CLBIN[2]
CLBIN[3] CLBOUT
CLBIN[0]
4 5 6 7
12 13 14 15
0 1 2 3
8 9 10 11
16
17
18
19 20
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Virtual Bit Stream
Hiding routing details
List of I/O and connections 20 8
1 9
5 18
4 5 6 7
12 13 14 15
0 1 2 3
8 9 10 1116
17
18
19 20
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Results
VBS is independent of task location
VBS has a smaller size than BS
Compression ratio between 25% and 50% More efficient on large bit-streams Still improving…
Work on reducing coding of connections
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University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Outline
eFPGA Reconfigurable Fabric
Virtual Bit-Stream
What about heterogeneous blocks ? Task placement in a homogeneous context
Heterogeneous case
Development flow
Results & conclusion
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Task placement in a homogeneous context
Homogeneous case
This is the easiest case: No constraint on task placement
Regular routing architecture
Low impact on the reconfigurable architecture
Task
Configured LE
Logic Element (LE)
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eFPGA : Complex blocks handling
Heterogeneous case
Main goal: Place tasks on the logic fabric with as much flexibility as possible
Introduce RAM blocks, DSP, 3DNI+AI
Why not sticking to the classic task placer (i.e. homogeneous) ? It doesn’t work ! Flexibility is greatly reduced.
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eFPGA : Complex blocks handling
Proposal
Heterogeneous blocks routing is abstracted from logic routing Long lines allow a trade-off between placement flexibility and
routing complexity A two-level routing is performed at runtime:
Logic routing, as in the homogeneous case
Heterogeneous block routing through long lines
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at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
oth
erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
eFPGA : Complex blocks handling
Advantages
We can handle complex blocks The logic can be slided around a complex block because of the
connections to long lines
21 /
16-1
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1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
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chm
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are
the
pro
pert
y of
Fle
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nsor
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. Y
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at a
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atio
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istr
ibut
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co
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erw
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use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
eFPGA : Complex blocks handling
Constraints
Delay can only be estimated offline (but the online placer could be constrained)
Flexibility limited to one axis. On the other axis tasks have to be moved on heterogeneous block thresholds
Connections to complex blocks (long lines) should be constrained on specific lines
22 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
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erw
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use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Outline
eFPGA Reconfigurable Fabric
Virtual Bit-Stream
What about heterogeneous blocks ?
Development flow
Results & conclusion
23 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
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erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Development Flow
Custom development flow from C to Virtual Bit-Stream
Integrated within the FlexTiles development flow
Generates VBS from a C description or a HDL description
24 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
oth
erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Development Flow
Custom development flow from C to Virtual Bit-Stream
Relies on Catapult C from Calypto Design Systems
High-level synthesis from C to VHDL
25 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
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erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Development Flow
Custom development flow from C to Virtual Bit-Stream
Use the Verilog To Routing (VTR) academic tool flow to generate netlist and routing data from Verilog
26 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
oth
erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Development Flow
Custom development flow from C to Virtual Bit-Stream
A custom back-end generate the VBS from the data generated by VTR
The VBS can be loaded on the FlexTiles platform
27 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
oth
erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Outline
eFPGA Reconfigurable Fabric
Virtual Bit-Stream
What about heterogeneous blocks ?
Development flow
Results & conclusion
28 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
oth
erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Results
Overall results and achievements
3-D stacked embedded FPGA coupled to a processor layer Flexible resource allocation/sharing
Seamless task migration VBS also reduce the bitstream size
29 /
16-1
7/1
2/20
1 3
The
info
rmat
ion
cont
aine
d in
thi
s do
cum
ent
and
any
atta
chm
ents
are
the
pro
pert
y of
Fle
xTile
s co
nsor
tium
. Y
ou a
re h
ereb
y no
tifie
d th
at a
ny r
evie
w,
diss
emin
atio
n, d
istr
ibut
ion,
co
pyin
g or
oth
erw
ise
use
of t
his
docu
men
t m
ust
be d
one
in a
ccor
danc
e w
ith t
he C
A o
f th
e pr
ojec
t (T
RT
/DJ/
6244
1278
5.20
11).
Tem
plat
e ve
rsio
n 1
.0
University of Rennes 1 – AHS’14 FlexTiles Workshop 29
Results
Thank you for your attention.
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