Conference on Adaptive Hardware and Systems (AHS'14) - Why FlexTiles uses OVP for Simulation

www.flextiles.eu

FlexTiles

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FlexTiles Simulating Environment based on Open Virtual Platforms

(OVP)Stephan Werner (KIT)

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Outline

Outline Why using OVP? Introduction to FlexTiles Platform Implementation in OVP WebGUI Integration in toolchain

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Why using OVP

Why using OVP: Very complex software

OS Management services Ressource Managers User applications in Virtual Platforms

Hardware not fully integrated Making a cycle-accurate model is not possible Possible: modeling the expected behavior (register set, protocols, etc.

Our focus: Rapid Prototyping of complex software Simulation should run as fast as possible

OVP: binary translation of cross-compiled code by morphing

Cycle accuracy is not needed

OVP is right choice for our application

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Introduction to the FlexTiles Platform

Introduction to the FlexTiles Platform: Hardware GPPs

MicroBlazes executing CompOSe One Monitoring Core

DSP Icyflex 4

eFPGA Accelerator Interface

Virtualizing DSPs and accelerators

Network Interfaces Abstraction for different NoCs

NoC View in HW: DMAs View in SW: FIFOs

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Introduction to the FlexTiles Platform: Hardware

Homogeneous GPP nodes

Heterogeneous acceleratorsnodes

GPP Node

AI

DSPNode

NI

GPP Node

NI

NoC

NI NI NI

AI AI

NI

Config. Ctrl.

DDR Ctrl.

NI

GPP Node

NI

I/O

NI

Generic Interfaces

eFPGA Domain (Reconfigurable HW acc.)

Dedicated Accelerator

Node

Dedicated Accelerator

Node

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Introduction to the FlexTiles Platform

Introduction to the FlexTiles Platform: Software CompOSe

Real-time OS Guaranteed real-time

FIFOs Software view to NoC

Cyclo-static dataflow Programming model

ELF-bundles Contains information about the different configurations of the CSDF model Contains all executables

Virtualization Layer Manages task migration and (re-)distribution Runs as priviledged service

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Introduction to the FlexTiles Platform: Software

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Programming Model: CSDF

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Programming Model: CSDF

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Implementation in OVP

Implementation in OVP: Outline GPPs running the OS The Monitoring Core DMA-support as used for FIFOs Accelerator Interface

After implementation: WebGUI Integration in toolflow

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Implementation in OVP: GPP MicroBlaze-model in OVP available

Same (cross-compiled) code is executed

Timer has to be adapted CompOSe executed Virtualization layer

Test environment

Can be connected to GDB

NI

NoC

GPP CoreInstruction

CacheLocal

Data Memory

Peripherals

IT / event

iNoC

Control Sync

Instruction

DMA

Supervisor

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Implementation in OVP: GPP// FOR ALL CORESfor (index=0; index<CORES; index++){

...

////////////////////// BUSES////////////////////

bus[index] = icmNewBus( busName, 32);

////////////////////// PROCESSORS////////////////////cpu[index] = icmNewProcessor(

cpuName, // CPU name"microblaze", // CPU type0, // CPU cpuId0, // CPU model flags32, // address bitsmicroblazeModel, // model file"modelAttrs", // morpher attributesSIM_ATTRS, // attributescpu_attr, // user-defined attributesmicroblazeSemihost, // semi-hosting file"modelAttrs" // semi-hosting attributes

);

icmConnectProcessorBusses(cpu[index], bus[index], bus[index]);

…

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...

////////////////////// MEMORY////////////////////

localMem[index] = icmNewMemory(memName, 0x7, MICRO_SIZE);

icmConnectMemoryToBus( bus[index], "mp1", localMem[index], MICRO_BASE);icmConnectMemoryToBus( bus[index], memportName, shared, SHARE_BASE);

if(!icmLoadProcessorMemory(cpu[index], application[index], False, False, True))return -1;

////////////////////// TIMERS AND INTS////////////////////

timer[index] = icmNewPSE( timerName, // name //timer_path, // model"../Peripherals/Timer/pse.pse",timer_attr, // attrlist 0, // semihost file 0 // semihost symbol

);

icmConnectPSEBus( timer[index], bus[index], "plb", 0, TIMER_BASE, (TIMER_BASE+TIMER_SIZE-1));

…

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...

irq[index] = icmNewNet(irqName);icmConnectProcessorNet( cpu[index], irq[index], "Interrupt", ICM_INPUT);icmConnectPSENet( timer[index], irq[index], "Interrupt", ICM_OUTPUT);

////////////////////// UART////////////////////

uartAttr[index] = icmNewAttrList();icmAddStringAttr(uartAttr[index], "outfile", uartAttrName);

uart[index] = icmNewPSE(uartName, // nameuart_path, // modeluartAttr[index], // attrlistNULL, // semihost fileNULL // semihost symbol

);

icmConnectPSEBus(uart[index], bus[index], "plb", 0, UART_BASE, (UART_BASE+UART_SIZE-1));

...}

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...#ifdef DEBUG

if(index==DEBUG_CORE){cpu[index] = icmNewProcessor(

cpuName, // CPU name"microblaze", // CPU type0, // CPU cpuId0, // CPU model flags32, // address bitsmicroblazeModel, // model file"modelAttrs", // morpher attributesICM_ATTR_DEBUG, // attributescpu_attr, // user-defined attributesmicroblazeSemihost, // semi-hosting file"modelAttrs" // semi-hosting attributes

);}else{

#endif...

}

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Implementation in OVP: Monitoring Core

Not every GPP can have an UART Hardware limited

Monitoring Core gathers the output Only GPP with I/O Connected via FSL to other GPPs On OVP: UART On board: Ethernet to PC Same operations run in OVP and on board

getfsl, putfsl

CompOSe CompOSe

MonitoringCore

CompOSe

UART(OVP)

(Board)

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Implementation in OVP: Monitoring Core// FOR ALL CORESfor (index=0; index<CORES; index++){

...//connections to central monitoring core; limitation: 16FSL links//Monitor core is last core created, its link is defined by FSL_MONITOR, tile fsl connect to this id and putfsl sends to it//FSL_MONITOR needs to be set to the # of the last core, which equals CORESif(index!=FSL_MONITOR){

char monitorPort[64];

tfsl[index] = icmNewFifo(fsl_ToMonitor_Name, 64, 128);sprintf(monitorPort, "MFSL%d", FSL_MONITOR);icmConnectProcessorConn(cpu[index], tfsl[index], monitorPort, ICM_OUTPUT);

ffsl[index] = icmNewFifo(fsl_FromMonitor_Name, 64, 128);sprintf(monitorPort, "SFSL%d", FSL_MONITOR);icmConnectProcessorConn(cpu[index], ffsl[index], monitorPort, ICM_INPUT);

}if(CORES==index+1){

char tilePort[64];for(i=0;i<CORES;i++){

if(i!=FSL_MONITOR){sprintf(tilePort, "SFSL%d", i);icmConnectProcessorConn(cpu[FSL_MONITOR], tfsl[i], tilePort,

ICM_INPUT);

sprintf(tilePort, "MFSL%d", i);icmConnectProcessorConn(cpu[FSL_MONITOR], ffsl[i], tilePort,

ICM_OUTPUT);}

}}...

}

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Implementation in OVP: DMA-support

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Implementation in OVP: DMA-support Per DMA this is needed:

One CMI: input memory One CMO: output memory Adress table:

Local addresses Remote addresses

GPP local memory

CMI

CMO

DMA

/////////////////////////////// // DMA Peripheral ///////////////////////////////

// instantiate the peripheral icmAttrListP config = icmNewAttrList(); icmAddUns64Attr(config, "id", 1); icmPseP dma = icmNewPSE("dma", "../Peripherals/DMA/dma.pse", config, 0, 0);

icmConnectPSEBus(dma, bus[2], "slave1", False, mb0_dma0_BASEADDR, mb0_dma0_BASEADDR+7); icmConnectPSEBus(dma, bus[2], "master1", True, 0x00000000, 0xFFFFFFFF);

icmConnectPSEBus(dma, bus[0], "slave0", False, mb1_dma0_BASEADDR, mb1_dma0_BASEADDR+7); icmConnectPSEBus(dma, bus[0], "master0", True, 0x00000000, 0xFFFFFFFF);

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Da

te /R

efe

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The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

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ents

are

the

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pert

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Fle

xTile

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nsor

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. Y

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ith t

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t (T

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6244

1278

5.20

11).

Tem

plat

e ve

rsio

n 1

.0


Implementation in OVP: Accelerator Interface

NINoC

OutputData

DMA

DMAdataoutreq

FIFO

InputData

DMA

DMAdata

inreq

FIFO

da

ta rd

ctrl w

r

AcceleratorOutput Ch.Input Ch.

da

ta w

r

ctrl w

r

InputConfig

DMA

DMAcfgreq

FIFO

Config.Ch.

co

nfig

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co

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wr

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rd

ctrl w

r

Workreq

FIFO

ctrl w

rc

trl rd

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/ sta

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Synchronization /Notification

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rite n

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Control / Status Channel

me

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me

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DebugCh.

write

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21 /

Da

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renc

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The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

pert

y of

Fle

xTile

s co

nsor

tium

. Y

ou a

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y no

tifie

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atio

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istr

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ion,

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use

of t

his

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men

t m

ust

be d

one

in a

ccor

danc

e w

ith t

he C

A o

f th

e pr

ojec

t (T

RT

/DJ/

6244

1278

5.20

11).

Tem

plat

e ve

rsio

n 1

.0


Implementation in OVP: Accelerator Interface

EXPLANATION IN COMBINATION WITH LIVE-PRESENTATION OF CODE

22 /

Da

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efe

renc

e

The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

pert

y of

Fle

xTile

s co

nsor

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atio

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istr

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ion,

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ise

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of t

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men

t m

ust

be d

one

in a

ccor

danc

e w

ith t

he C

A o

f th

e pr

ojec

t (T

RT

/DJ/

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5.20

11).

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plat

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.0


Implementation in OVP: Accelerator Interface AI implemented as peripheral in OVP

Runs seperately from GPP simulation

Algorithm of accelerator is executed on host natively Fast simulation

Can be used as template for accelerators Insert algorithm in function start_calc()

23 /

Da

te /R

efe

renc

e

The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

pert

y of

Fle

xTile

s co

nsor

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. Y

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y no

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at a

ny r

evie

w,

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istr

ibut

ion,

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ise

use

of t

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men

t m

ust

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one

in a

ccor

danc

e w

ith t

he C

A o

f th

e pr

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t (T

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6244

1278

5.20

11).

Tem

plat

e ve

rsio

n 1

.0

Usability

WebGUI Generation of Hardware-Architecture

24 /

Da

te /R

efe

renc

e

The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

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y of

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ith t

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A o

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t (T

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6244

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5.20

11).

Tem

plat

e ve

rsio

n 1

.0

Usability

WebGUI Application-Binding

25 /

Da

te /R

efe

renc

e

The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

pert

y of

Fle

xTile

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A o

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t (T

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6244

1278

5.20

11).

Tem

plat

e ve

rsio

n 1

.0

Usability

WebGUI Simulation in WebGUI

26 /

Da

te /R

efe

renc

e

The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

pert

y of

Fle

xTile

s co

nsor

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. Y

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one

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ccor

danc

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ith t

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A o

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t (T

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/DJ/

6244

1278

5.20

11).

Tem

plat

e ve

rsio

n 1

.0

Integration in toolchain


27 /

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efe

renc

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The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

pert

y of

Fle

xTile

s co

nsor

tium

. Y

ou a

re h

ereb

y no

tifie

d th

at a

ny r

evie

w,

diss

emin

atio

n, d

istr

ibut

ion,

co

pyin

g or

oth

erw

ise

use

of t

his

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men

t m

ust

be d

one

in a

ccor

danc

e w

ith t

he C

A o

f th

e pr

ojec

t (T

RT

/DJ/

6244

1278

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11).

Tem

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e ve

rsio

n 1

.0



28 /

Da

te /R

efe

renc

e

The

info

rmat

ion

cont

aine

d in

thi

s do

cum

ent

and

any

atta

chm

ents

are

the

pro

pert

y of

Fle

xTile

s co

nsor

tium

. Y

ou a

re h

ereb

y no

tifie

d th

at a

ny r

evie

w,

diss

emin

atio

n, d

istr

ibut

ion,

co

pyin

g or

oth

erw

ise

use

of t

his

docu

men

t m

ust

be d

one

in a

ccor

danc

e w

ith t

he C

A o

f th

e pr

ojec

t (T

RT

/DJ/

6244

1278

5.20

11).

Tem

plat

e ve

rsio

n 1

.0


Thank you for your attention

Questions ?

Conference on Adaptive Hardware and Systems (AHS'14) - Why FlexTiles uses OVP for Simulation

Engineering