www.flextiles.eu FlexTiles 1 8 . 0 7 . 2 0 1 4 / A H S Benedikt Janßen Ruhr-University Bochum (RUB) FlexTiles Workshop at AHS 2014 FPGA-Based Emulation of the FlexTiles Platform
Conference on Adaptive Hardware and Systems (AHS'14) - FlexTiles FPGA Emulation
Jun 19, 2015
The FP7 FlexTiles Project will provide a tool-chain that allows DSPs, CPUs and a FPGA to be implemented on the FlexTiles Development Platform. This slide gives some details about the dynamic re-configurable of the FPGA by the CPU
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www.flextiles.eu
FlexTiles
18.0
7.20
14/A
HS
Benedikt JanßenRuhr-University Bochum (RUB)
FlexTiles Workshop at AHS 2014
FPGA-Based Emulation of the FlexTiles Platform
2 /
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14
The
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ion
cont
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Global View
GPP Node
AI
DSP FPGA Fabric
NI
GPP Node
NI
Network-on-Chip (NoC)
NI NI NI
AI AI
NI
Reconfig. Control
DDR Node
NI
Tile TileGPP Node
NI
I/O
NI
HW Acc. HW Acc.
Tile
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ion
cont
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t (T
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Development Platform
Software Emulator
Based on Open Virtual Platform
Enable Software prototyping
Hardware Emulator
Sundance SMT166 Based on 2 Virtex-6 FPGAs
24-pin ATX connector
Based on the TU/e platform
Enable Hw/Sw prototyping
4 /
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cont
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any
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/DJ/
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Development Platform
System Components
GPP Node MicroBlaze soft-core processors
Network on Chip Nodes connected via Network Interfaces
Network Interface Device Transport Layer (DTL) protocol
Accelerator Interface Newly developed within this project
Accelerators Micro-programmed
Data-flow
GPP Node
AI
Accelerator
NI
NoC
NI
5 /
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cont
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d in
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any
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/DJ/
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Network on Chip
Network on Chip
AElite NoC
Network Interface
Main Task Data into packets NoC
NoC data out of packets
Device Transport Layer Master / Slave
Data flow Load / Store
Stream
GPP Node
AI
Accelerator
NI
NoC
NI
6 /
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cont
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Accelerator Interface
Main Tasks
Control accelerators
Provide a unique interface
Components
Accelerator control
Protocol parser
GPP Node
AI
Accelerator
NI
NoC
NI
AC
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cont
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t (T
RT
/DJ/
6244
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5.20
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AI : DTL-To-AI
Device Transaction Layer (DTL)
Command (dtl_cmd)
Write (dtl_wr)
Read (dtl_rd)
DTL-To-AI Structure
GPP Node
AI
Accelerator
NI
NoC
NI
DTL2AIAC
8 /
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cont
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RT
/DJ/
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AI : Accelerator Control
Accelerator Control Structure GPP Node
AI
Accelerator
NI
NoC
NI
DTL2AIAC
in
out
9 /
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cont
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Tem
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Accelerators
Accelerator Types
Micro-programmed: FlexTiles DSP
Data-flow: Accelerators on eFPGA
Lite Accelerator
Example/Test Application
Implements 2 register banks
3 FIFOs
Adding two sequential values
GPP Node
AI
Accelerator
NI
NoC
NI
10 /
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Software Functions
Accelerator Software Functions
send_rqst (int acc_number, int size, int ch_id, int addr, char type)
send_data (int acc_number, int size, int ch_id, int addr, int* array)
read_data (int acc_number, int size, int addr, int* array)
write_register (int acc_number, int ch_id, int addr, int value)
read_register (int acc_number, char regis)
GPP Node
AI
Accelerator
NI
NoC
NI
11 /
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rmat
ion
cont
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d in
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t (T
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6244
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5.20
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Development Platform Configuration
Xilinx Platform Studio Project
TUe Platform configured via XML file
Xilinx Microprocessor Project file (XMP)
Platform Configuration
User Constraint File (UCF)
Microprocessor Hardware Specification (MHS)
Microprocessor Software Specification (MSS)
12 /
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cont
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Adding Accelerators
Accelerator Integration
Peripheral Core (PCORE)
Add Accelerator files to pcore directory
Add Accelerator entry to MHS
Configuration Files
Black Box Definition file (BBD)
Peripheral Analyze Order file (PAO)
Microprocessor Peripheral Definition (MPD)
13 /
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cont
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Implementation
XPS Command Line Mode
xps -nw -scr system.tcl system.xmp
Simple Design:
GPP
AI+ Acc
DebugMonitor
NoC
14 /
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cont
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Implementation Results
Results
Standalone platform Occupied Slices: 5%
IOB: 1%
RAMB36E1: 13%
RAMB18E1: 0%
BUFG: 9%
Platform with lite accelerator Occupied Slices: 7%
IOB: 1%
RAMB36E1: 13%
RAMB18E1: 1%
BUFG: 12%
GPP Node
NI
NoC
Monitor Node
GPP Node
AI
Lite Accelerator
NI
NoC
NI
Monitor Node
15 /
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The
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rmat
ion
cont
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d in
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ent
and
any
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Implementation Results
Results
Platform with DSP Occupied Slices: 62%
IOB: 1%
RAMB36E1: 15%
RAMB18E1: 1%
BUFG: 9%
GPP Node
AI
DSP
NI
NoC
NI
Monitor Node
16 /
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info
rmat
ion
cont
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cum
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and
any
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Challenges
Platform with DSP
Unroutable Signals (Rats Nests)
Colors
Monitor: yellow
GPP: cyan
NoC: purple
AI: green
DSP: red
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cont
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d in
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Summary
Emulator Goal
Run demo application like optical flow
NoC
GPP Node
NI
NI
GPP Node
GPP Node
NI
NI
GPP Node
NI
NI
NI
NI
AI
Acc
AI
Acc
Acc
AI
Acc
AI
NoC
AURORA
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cont
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and
any
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f th
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6244
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11).
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Many Thanks for Your Attention!
www.flextiles.eu
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