Conference on Adaptive Hardware and Systems (AHS'14) - The 3D FlexTiles Concept

www.flextiles.eu

FlexTiles3-D Stacked Chip Technology and Strategies for

Optimal Usage of Through Silicon Vias (TSV)

Romain LEMAIRE, CEA-LETI

2014 NASA/ESA Conference on Adaptive Hardware and Systems (AHS-2014)

FlexTiles Workshop – July 18th, 2014

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© CEA. All rights reserved – R. LEMAIRE – AHS-2014

Introduction: FlexTiles Architecture

FlexTiles: an innovative manycore architecture based on reconfigurable

devices (FPGAs), DSPs and GPPs

FlexTiles combines advantages:

� Programmability from General-Purpose Processors (GP P)

� Power efficiency from DSP and hardware accelerator mapped on FPGA

� Flexibility from reconfigurable logic

Concept of tiles supported by a software virtualization layer

� Accelerator Interfaces to provide homogeneousaccess to DSP and hardware accelerators

� Flexibility to connect GPP nodes to severalaccelerators

How to organize the architecture

at physical level?

GPP Node

AI

DSP FPGA Fabric

NI

GPP Node

NI

NoC

NI NI NI

AI AI

NI

Reconfig. Ctrl.

DDR Node

NI

Tile Tile

GPP Node

NI

I/O

NI

HW Acc. HW Acc.AIAccelerator Interface

Interpret requests from GPP

NINetwork Interface

Interfaces a node with NoC

3 / 27

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Introduction: Motivation for 3D Integration

Which floorplanning strategy for FlexTiles architecture?

� Pattern mixing GPP, DSP and FPGA nodes?� Strong constraints on topology

� Fixed hardware accelerator granularity

� FPGA fabric adjacent to a manycore area� Non-uniform access, long wires

� Possible congestion due to limited bisection bandwidth

FlexTiles proposition

� 3D-stacking approach� Shorter access and flexibility to associate GPP with

hardware accelerators (resource sharing)

� Different technologies on separate dies

What can we expect from 3D technologies?

How to refine the 3D-stacking design?

GPP

DSP

FPGA GPP

FPGA GPP

DSP

FPGA

GPP

GPP

FPGA

GPP

GPP

DSP

GPP

GPP FPGA

GPP

DSP

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Outline

3D technologies available for FlexTiles

Architecture partitioning for 3D integration

FlexTiles 3D-stacked IC Definition

3D integration evaluation and results

Conclusion and future works

5 / 27

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3D IC: Some Definitions

3D-IC chip stacking:

� Adding a new vertical interconnect chain in CMOS :Through Silicon Via ( TSV) + microbump

(Backside micro-bump)

(bump)BEOL: Back-End-Of-LineFEOL: Front-End-Of-Line

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TSV Technologies

� Via First TSV (Polysilicon filled)AR 20, 5x100µmProcessed before CMOS front-end steps

Pitch: ~10µmDensity: 10000 TSV/mm²SOI substrate, High-voltage

AR 7,2 x 15µm

� Via Middle TSV (Copper filled)

AR 10, 10x100µm

Processed after CMOS front-end stepsPitch: 40µm to 50µmDensity: 500 TSV/mm²Best flexibility in layout and designHigher density of I/Os

� Via Last TSV (Copper liner)

AR 1, 80x80µm

AR 2, 60x120µm

AR 3, 40x120µm

Processed after metallizationPitch: ~100µmDensity: 100 TSV/mm²Minimal impact on circuit layout

3 families of TSV’s with different characteristics

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Die Connection Technologies

Pitch

Classic Flip chip (Ball or stud bump)

> 100 µm

TSV last

Cu pillars(microbump)

100-30 µm range

TSV middle

Cu-Cu Direct bonding

Si

Si

Cu

SiO2

Si

Si

Cu

SiO2

Need very flat surfaceCleaning

Down to 5 µm30-10 µm range

TSV first

Top chip

Bottom chip

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3D IC: Stacking Strategies

Source: Patrick Leduc; D43D 2011

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3D-IC: Stacking Options

Face-to-Face:

� Inter-die connection:

� TSV are not required

� Package connection:

� TSV are required to propagate the I/Os

Face-to-Back:

� Inter-die connection:

� TSV are required

� Package connection:

� Flip-chip

BULK

METAL LAYERS

PACKAGE

PACKAGE

BULK

METAL LAYERS

BULK

METAL LAYERS

TSVs

TSVs

Micro-bumps

Bumps

Bumps

BULK

METAL LAYERSMicro-bumps

10 / 27

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3D Technologies for FlexTiles

Summary of technology selection for FlexTiles

� Via-middle TSV

� Technology more mature in manufacturing process

� Valuable trade-off concerning density of integration compared to technological complexity

� Copper pillar (microbump) for binding

� Aligned with via-middle TSV technology

� Wafer to wafer assembly if same die size

� Stacking Face-to-face or Face-to-back to be decided base on design exploration results

11 / 27

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Outline






12 / 27

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3D Partitioning Options

How to partition the architecture over the different layers?

� Coarse-grained : placing large functional blocks (IP cores) on different layers in the 3D stack. Interactions/Comm unications between IPs define their relative position in the 3 D stack.

� Medium -grained : placing the functional units of an IP core on different layers to take advantage of shorter 3D co nnections.

� Fine-grained : placing the gates composing the same functional unit on different layers.

Solution for FlexTiles : coarse-grained

� IP cores can be reused

� Impact of 3D technologies is restricted to inter-di e communications

� Integration of different technologies (Manycore / F PGA)

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FlexTiles Partitioned Architecture

The FPGA fabric is not fractioned

Resources connected to the NoC by Network Interfaces

Die-to-die connection are supported by 3D NoC links

NoC

NIDDR Node I/ONINI

GPPnode

DSPnode

NI

AI

AI AI

DSPnode

NI

AI

NI

GPPnode

NI

GPPnode

Reconfig. Ctrl.

ManycoreLayer

ReconfigurableLayer

TO

PB

OT

TO

M

NI

NINI

FPGA FabricHW acc. HW acc.

3D link

eFPGA

3D link

NI

3D link

14 / 27

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Solving Partitioning Issues

GALS approach for synchronization

� Clock synchronization is a critical problem (propag ation delays balancing)

� Globally Asynchronous Locally Synchronous (GALS) ap proach

� Several domains with independent clock signals

� Possibility of dynamic frequency scaling

� Advantages for FlexTiles architecture

� Avoid to merge clock domains between manycoreand reconfigurable layers

� No need for multi-techno, multi-die clock treesynthesis tools (not currently well-mature)

3D NoC infrastructure for communication

� NoC proposed in FlexTiles as communication infrastructure for scalability and flexibility reas ons

� NoC also well-adapted for 3D GALS system

� 3D NoC built as a regular 3D-mesh

� 7-port NoC router decomposed into 5-port (intra-die) and 4-port (vertical) routers

15 / 27

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Outline






16 / 27

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FlexTiles architecture organization based on 3D-stacked

layers:

� Manycore structure layer (GPP and/or DSP nodes)

� Reconfigurable layer (FPGA fabric)

3 products are targeted

1. Homogeneous manycore layer (GPP nodes) coupled with reconfigurable layer.

2. Homogeneous manycore layer (GPP nodes) coupled with a full DSP node layer.

3. Heterogeneous manycore layer with both GPP and DSP nodes coupled with a reconfigurable layer.

In this presentation, case study oriented on option 3.

17 / 27

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Refined Architecture Definition

GPP NODE

5x5

5x5

GALSIF

GALSIF

NI

Slave

Master

clock generator

GPP CORE 3x3

3x3

3D3D

DTL

DSP NODE

DSP CORE GALSIF

GALSIF

NI

clock generator

AIAI IF

BOTTOM LAYER

2D NOC

R3DNODE R3DNODE R3DNODE

TOP LAYER

FPGA CORE = eFPGA

GALSIF

GALSIF

3DNI

GALSIF

GALSIF

NI

AI

3DNI

GALSIF

GALSIF

NI

AINI

Slave Master

Logic density (kG/mm²) 1900

Memory density (kb/mm²) 1000

RAM Size (kb) Logic Area RAM Area Area mm² (28nm)

DSP node + 32kB (data+instr)

256 0,158 0,256 0,414

GPP node + 32kB (data) + 16kB (I$)

384 0,020 0,384 0,404

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FlexTiles Layer Definition

Manycore layer:• 20 GPP, 8 DSP nodes• 2 DDR interfaces

Reconfigurable layer:• 8 hardware accelerator

interface• 1 reconfiguration

controllerI/O

I/O

DDR

DDR

2D

2D

DSP

2D3D

NI GALS

GPP

2D

NI GALS

GPP

2D

NI GALS

GPP

2D

NI GALS

GPP

2D3D

NI GALS

DSP_S

NI GALS

2D3D

NI GALS

GPP

2D

NI GALS

GPP

2D3D

NI GALS

GPP

2D

NI GALS

GPP

2D3D

NI GALS

2D

GPP

2D

NI GALS

GPP

2D

NI GALS

GPP

2D

NI GALS

GPP

2D

NI GALS

NI GALS

DSP

2D3D

NI GALS

GPP

2D

NI GALS

GPP

2D3D

NI GALS

GPP

2D

NI GALS

GPP

2D3D

NI GALS

DSP_S

NI GALS

GPP_N

NIGALS

DSP_E

NIGALS

GALS

DSP_E

NIGALS

GPP_E

NIGALS

GPP

NI GALS

DSP

2D

NI GALS

2D

2D

DSP

NI GALS

GPP_S

NI GALS

3D GALS

ReconfigurationController

3D

3D 3D

3D

3D

3D

3D

3D

3D

ReconfigurationRAM

3DNI 3DNI3DNI

3DNI 3DNI

3DNI 3DNI3DNI

SoC characteristics2x27mm² in techno 28nm

3D NoC characteristics• 2D-mesh NoC on

bottom layer• 3D router every 4 nodes

for vertical connectivity• 2 external NoC

interfaces

19 / 27

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Outline






20 / 27

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t and

any

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chm

ents

are

the

prop

erty

of F

lexT

iles

cons

ortiu

m. Y

ou a

re h

ereb

y no

tifie

d th

at a

ny r

evie

w, d

isse

min

atio

n, d

istr

ibut

ion,

co

pyin

g or

oth

erw

ise

use

of th

is d

ocum

ent m

ust b

e do

ne in

acc

orda

nce

with

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CA

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TSV Cost Evaluation

I/O Pads µbuffers

µbuffers

I/O Pads

µbuffers

µbuffersF2B

F2F

Face-to-Face Face-to-Back

Nb of TSV Area (%) Nb of TSV Area (%)

Bottom die power 648 0.47% 0 0.00%

Top die power 432 0.31% 432 0.31%

Package I/O power 46 0.03% 0 0.00%

Package I/O 305 0.22% 0 0.00%

3D I/O power 721 0.52% 360 0.26%

3D I/O 0 0.00% 3603 2.62%

TOTAL POWER1847 (~×2)

1.34% 792 0.57%

TOTAL I/O 305 0.22% 3603 2.62%

TOTAL 2152 1.56%4395 (~×2)

3.19%

Package I/O

3D I/O power

3D I/O

Bottom die power

Top die power

Package I/O power

Face-to-Face stacking option:• High number of power TSV• Half total TSV compared to Face-to-

Back alternative

21 / 27

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at a

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FlexTiles 3D-IC Floorplanning (1/2)

Floorplan validation using Spyglass® Physical (Atrenta)

� Early prototyping tool for 3D designexploration

� Comparison of Face-to-Face and Face-to-Back3D-stacking options

Definition of microbump/TSV areas

� 400 connections to be placedper NoC link

� 40µm pitch

� 6µm TSV diameter

� 4µm keep-out-zone

22 / 27

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FlexTiles 3D-IC Floorplanning (2/2)

Detailed floorplan snapshots

Manycore layer Reconfigurable layer

5500µm

4900

µm

23 / 27

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Floorplanning Results

Wire length distribution and congestion analysis

10

02

45

1

62

43

17

2 2 0 0 0 1

10

02

64

0

60

47

24

2 2 0 0 1 036

03

0 0 0 0 0 0 0 0

0

200000

400000

600000

800000

1000000

1200000

0% - 50% 50% - 100% 100% - 150% 150% - 200% 200% - 250% 250% - 300% 300% - 350% 350% - 400% 400% - 450%

Nu

mb

er

of

ne

ts

Nets F2F frontside

Nets F2B frontside

Nets F2B backside

% of Manhattan length

24 / 27

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Outline






25 / 27

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t and

any

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prop

erty

of F

lexT

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cons

ortiu

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ou a

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at a

ny r

evie

w, d

isse

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istr

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Conclusions

Case study to validate to silicon implementation feasibility

of FlexTiles architecture

� TSV Analytical estimation

� Floorplan exploration with early prototyping tools

Face-to-Face approach is confirmed to be the best

candidate since it reduces the number of TSVs.

� Floorplanning results show the possibility to place TSVs and microbumps in well-defined area in order to optimize the wirelength constraint.

� Alignment between the manycore components and the 3 DNI in the reconfigurable layer is challenging

26 / 27

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evie

w, d

isse

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istr

ibut

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Perspectives

Extended FlexTiles architecture with 3D interposer

� Flexibility on computation power thanksto manycore chiplets

� Specialized chiplets forhigh-constrainedapplication

System Architecture• Scale-out architecture

• Coherent island with

remote communications

Chiplet• Small chips• Advanced technology

node• Generic

• High volume

• Low cost

Interposer• Passive or active

• Mature technology node

• Application specific

• Medium volume

• Cost effective assembly

• European fabs

27 / 27

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THANK YOU FOR YOU ATTENTION

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Conference on Adaptive Hardware and Systems (AHS'14) - The 3D FlexTiles Concept

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