Top Banner

of 32

Chapter5 Virtuoso

Apr 03, 2018

Download

Documents

mdzakir_hussain
Welcome message from author
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
  • 7/28/2019 Chapter5 Virtuoso

    1/32

    Chapter 5Virtuoso Layout Editor

  • 7/28/2019 Chapter5 Virtuoso

    2/32

    68 CHAPTER 5: Virtuoso Layout Editor

    Figure 5.1: Inverter schematic

    Figure 5.2: Inverter symbol

  • 7/28/2019 Chapter5 Virtuoso

    3/32

    69

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.3: Dialog for creating a Layout View of the inverter cell

    Figure 5.4: Initial nactive rectangle

  • 7/28/2019 Chapter5 Virtuoso

    4/32

    70 CHAPTER 5: Virtuoso Layout Editor

    Figure 5.5: nactive rectangle with measurement rulers

  • 7/28/2019 Chapter5 Virtuoso

    5/32

    71

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.6: Create contact dialog box

  • 7/28/2019 Chapter5 Virtuoso

    6/32

    72 CHAPTER 5: Virtuoso Layout Editor

    Figure 5.7: nactive showing source and drain connections

    Figure 5.8: Nmos transistor 3 wide and 0.6 long

  • 7/28/2019 Chapter5 Virtuoso

    7/32

    73

    Figure 5.9: A pmos transistor 6 wide and 0.6 long

  • 7/28/2019 Chapter5 Virtuoso

    8/32

    74 CHAPTER 5: Virtuoso Layout Editor

    Figure 5.10: A pmos transistor inside of an NWELL region

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.11: Extra features dialog box in move mode

  • 7/28/2019 Chapter5 Virtuoso

    9/32

    75

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.12: Dialog box for the path command

  • 7/28/2019 Chapter5 Virtuoso

    10/32

    76 CHAPTER 5: Virtuoso Layout Editor

    Figure 5.13: Inverter layout with input and output connections made

  • 7/28/2019 Chapter5 Virtuoso

    11/32

    77

    Figure 5.14: Inverter layout with power supply connections

  • 7/28/2019 Chapter5 Virtuoso

    12/32

    78 CHAPTER 5: Virtuoso Layout Editor

    Figure 5.15: Inverter layout with well and substrate connections

  • 7/28/2019 Chapter5 Virtuoso

    13/32

    79

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.16: Shape pin dialog box

  • 7/28/2019 Chapter5 Virtuoso

    14/32

    80 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.17: Final inverter layout

  • 7/28/2019 Chapter5 Virtuoso

    15/32

    81

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.18: Layout with four inverter instances

  • 7/28/2019 Chapter5 Virtuoso

    16/32

    82 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.19: Layout with four inverter instances expanded to see all levels of layout

  • 7/28/2019 Chapter5 Virtuoso

    17/32

    83

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.20: Submit Plot dialog box

  • 7/28/2019 Chapter5 Virtuoso

    18/32

    84 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.21: Plot Options dialog box

    Figure 5.22: Nmos transistor layout (with DRC errors)

  • 7/28/2019 Chapter5 Virtuoso

    19/32

    85

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.23: DIVA DRC control window

  • 7/28/2019 Chapter5 Virtuoso

    20/32

    86 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.24: Results from the DRC in the CIW window

    Figure 5.25: Nmos transistor layout (with DRC errors flagged)

  • 7/28/2019 Chapter5 Virtuoso

    21/32

    87

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.26: Explanation of DRC violation

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.27: Finding all DRC violations

  • 7/28/2019 Chapter5 Virtuoso

    22/32

    88 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.28: DIVA extraction control window

  • 7/28/2019 Chapter5 Virtuoso

    23/32

    89

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.29: DIVA extraction special switches

  • 7/28/2019 Chapter5 Virtuoso

    24/32

    90 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.30: DIVA extraction result in the CIW

  • 7/28/2019 Chapter5 Virtuoso

    25/32

    91

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.31: Extracted view of the inverter

  • 7/28/2019 Chapter5 Virtuoso

    26/32

    92 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.32: DIVA LVS control window

  • 7/28/2019 Chapter5 Virtuoso

    27/32

    93

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.33: DIVA LVS Control Form

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.34: NCSU form to modify LVS rules

  • 7/28/2019 Chapter5 Virtuoso

    28/32

    94 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.35: DIVA LVS completion indication

  • 7/28/2019 Chapter5 Virtuoso

    29/32

    95

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.36: DIVA LVS output

  • 7/28/2019 Chapter5 Virtuoso

    30/32

    96 CHAPTER 5: Virtuoso Layout Editor

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.37: DIVA LVS output (scrolled)

  • 7/28/2019 Chapter5 Virtuoso

    31/32

    97

    (Copyright c2005, 2010, Cadence Design Systems, Inc. All rights reserved worldwide. Reprinted with permission.)

    Figure 5.38: DIVA LVS Run Information window

  • 7/28/2019 Chapter5 Virtuoso

    32/32

    98 CHAPTER 5: Virtuoso Layout Editor