Chap16-Analog Integrated Circuits

7/27/2019 Chap16-Analog Integrated Circuits

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Jaeger/Blalock7/1/03

Microelectronic Circuit DesignMcGraw-Hill

Chapter 16

Analog Integrated Circuits

Microelectronic Circuit Design

Richard C. Jaeger

Travis N. Blalock

Chap 16 - 1


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Chapter Goals

Understand bipolar and MOS current mirror operation and mirror ratio errors.

Explore high output resistance current sources including cascode and Wilson

current sources.

Design current sources for both discrete and integrated applications.

Study reference current circuits such as VBE-based reference, bandgapreference and Widlar current source.

Use current mirrors as active loads in differential amplifiers to increase

voltage gain of single-stage amplifiers.

Study effects of device mismatch on amplifier performance.

Analyze design of classic mA741 op amp.

Study realization of four-quadrant analog multipliers with large input signal

range.

Increase understanding of SPICE simulation techniques.

Chap 16 - 2


3/55



MOS Current Mirrors: DC Analysis

MOSFETsM1 andM2 are

assumed to have identical VTN,

Kn, l, and W/L ratios.

IREFprovides operating bias to

mirror.

VDS1 = VGS1= VGS2 =VGS

)1(1 DS1

Vn

KREF

2I

TNV

GS1V

l

DS2V

TNV

GS2Vn

K

D2I

OI l1

2

2

REFI

DS1VDS2

V

REFIOI

l

l

1

1

However, due to mismatches, VDS1 is

not equal to VDS2 and there is slightmismatch between output and

reference currents. Mirror ratio is:

DS1V

DS2V

REFI

OI

l

l

1

1MR

Chap 16 - 3


4/55



MOS Current Mirror (Example)

Problem:Calculate output current for given current mirror.

Given data:IREF= 150 mA, VSS = 10 V, VTN= 1 V, Kn = 250 mA/V2, l=

0.0133 V-1

Analysis: (1+ lVDS1) term is neglected to simplify dc bias calculation.

V10.2

2V

A250

)A150(2V1211

nK

REFITN

VGS

VDS

V

A165

V)10.2(V

0133.01

V)10(V

0133.01

)A150(

OI

Actual currents are found to be mismatched by approximately 10%.

Chap 16 - 4


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MOS Current Mirrors: Changing Mirror

Ratio

Mirror ratio can be changed bymodifying W/L ratios of the two

transistors forming the mirror.

11

LW'nKn

K22

LW'nKn

K

DS1V

L

W

DS2V

LW

REFI

DS1V

n1K

DS2V

n2K

REFI

OI

l

l

l

l

11

12

1

1

DS1V

L

W

DS2V

L

W

l

l

11

1

2MR

In given current mirror,Io =5IREF. Again

mismatch in VDScauses error in MR.

Chap 16 - 5


6/55



Bipolar Current Mirrors: DC Analysis

BJTs Q1 and Q2 are assumed to

have identicalIS, VA,bFO, and

W/L ratios.

Io =IC2, IREF=IC1 +IB1 +

IB2

VBE1= VBE2 =VBE

FOAV

CE2V

AV

CE2V

REFI

OI

b

21

)/(1

Finite current gain of BJT causes slight

mismatch betweenIo andIREF.

)/2(11MRFOREF

IOI

b

AVCE

V

TVBE

V

SI

CI 11exp1

AV

CEV

TVBE

V

SI

CI 21exp2

AVCE

V

FOF11

1bb

AVCE

V

FOF21

2bb

TVBEV

FO

SI

BI exp1 b

T

VBEV

FO

SIBI exp1 b

Chap 16 - 6


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Current Mirror (Example)

Problem:Calculate and compare mirror ratios for BJT and MOS current

mirror.

Given data:IREF= 150 mA, VGS = 2 V, VDS2 = VCE2 = 10 V, l= 0.02 V-1

VA = 50 V,bFO = 100, VSS = 10 V,M1 =M2, Q1 = Q2.

Analysis:

15.1

1

1

MOSMR

DS1V

DS2V

l

l

16.1

21

)/(1

BJT

MR

FOAVCE2V

AV

CE2V

b

Chap 16 - 7


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Bipolar Current Mirrors: Changing Mirror

Ratio

Mirror ratio can be changed by

modifying the emitter area of the

transistor.

A

EA

SOI

SI

Emitter area scaling changes thetransport equations using which,

Ideally, MR= n, but for finite gain,

FO

n

AV

CE2V

AV

CE2V

REFnI

OI

b

11

)/(1

E1A

E2A

n

FO

n1

n

b

MR

Chap 16 - 8


9/55



Multiple Current Sources

Reference current enters diode-

connected transistorM1 establishing

gate-source voltage to biasM2 through

M5, each with different W/L ratio.

Absence of current gain defect permitslarge number of MOSFETs to be

driven by one reference transistor.

Similar multiple bipolar sources can

be built from one reference BJT.

As base current error term worsenswhen more BJTs are added, umber of

outputs of basic bipolar mirror are

limited.

Chap 16 - 9


10/55



Buffered Bipolar Current Mirror

When large mirror ratio is used or

if many source currents are

generated from one reference BJT,

current gain defect worsens.

Current gain ofQ3 is used to

reduce base current that is

subtracted from reference current.

Assuming infinite Early voltage for simplicity,

FO3FO1

CI

n

REFI

B3I

REFI

C1I

b

b

1

1)1(

)1(

)1(1

1

FO3FO1

nREFnI

C1In

OI

bb

Thus error term in denominator is

reduced.

Chap 16 - 10


11/55



Output Resistance of Current Mirrors

For diode connected BJT, from

small-signal model,

mgR

gogmg

1

i

v

v)(i

...Ifboand mF>>1

This simplifies the ac model of

the current mirror. Similar

analysis applies to MOSFET

current mirror except that the

current gain is infinite. Thus

orA2V

CSV

or

outR

2

2CS

Vl

1

Chap 16 - 11


12/55



Two-port Model for Current Mirror

Since current mirror has acurrent input and current

output, we use h-parameters.

2

v

221

i

212

i2

v121

i111

v

hh

hh

n

mgm

g

rm

g

rm

gh

mgg

mg

h

1

2

211

22

02v1

i2i

21

1

1

21

1

02

v1i1v

11

For MOS current mirrors,

00

1i2

v1v

12

h

2

1

01i2

v2i

22

or

h

1

111

m

gh 0

12h

n

mgm

gh

1

221

2

122

or

h

Chap 16 - 12


13/55



Bipolar Widlar Current Source

R in Widlar source allows

adjustment of mirror ratio.

1

ln

1

1ln

1 SI

REFI

T

V

SI

REFI

T

V

BE

V

2

ln

2

1ln2

SIO

I

TV

SIO

I

TV

BEV

Current throughR is given by:

If transistors are matched,

Typically 1


14/55



PTAT Voltage

Voltage developed acrossR in Widlar current source is directly

proportional to absolute temperature.

Example: T= 300 K,IC1

=IC2

andAE2

= 10AE1

. Then =59.6 mV with

temperature coefficient of slightly< +0.2 mV/K

PTAT voltage combined with A-D converter is the core of electronic

thermometers.

T

V

EAE

A

CIC

I

qk

T

V

EAE

A

CIC

I

qkT

EAE

A

CIC

I

TV

BEV

BEVV

PTAT

1

2

2

1lnPTAT

1

2

2

1ln

1

2

2

1ln21PTAT

Chap 16 - 14


15/55



MOS Widlar Current Source

IfIO is known,IREFcan be directly

calculated. IfIREF,R and W/L ratios are

known, we can write a quadratic

equation in terms of

Small-signal model for MOS Widlar

source represents a C-S stage with

resistorR in its source.

Current throughR is given by:

2)/(1)/(

1

1

21

2

2

1

2

21

LW

LW

REFI

OI

nKREF

I

R

R

nK

OI

nKREF

I

R

GSV

GSV

O

I

2)/(1)/(

11

21LW

LW

REFI

OI

nK

REFIR

REFI

OI

Rm

gor

outR

21

2

REFI

OI /

Chap 16 - 15


16/55



MOS Wilson Current Source

During operation, all

transistors are in active

region.ID2 =IREF, ID3 =ID1

= IO, VGS3 = VGS1=VGS

GS

V

GSV

DI

D2I

l

l

1

21

1 GS

V

GSV

REFI

OI

l

l

1

21

1

2

nKREFI

TNV

GSV

where

1v3gsv3xi

1v

3vxv

ormg

From small-signal model,

322

1223xi

xv

orffforoutR mmm

)1v

2(

1

xi

1v

2vgsv f

mg

m

3

2

l

mf

CSV

Chap 16 - 16


17/55



Bipolar Wilson Current Source

During operation, all transistors are

in active region. But some current is

lost at base ofQ3 and current gain

error is formed by Q1 and Q2.

IREF= IC2 +IB3

VCE1 = VBE VCE2 = 2VBE2

33 or

oout

Rb

2A

VoCS

Vb

AVBE

2V

FOFO

AV

BEV

REFI

OI

)2(

21

)/(1

bb

Addition of extra BJT can balance thecircuit and reduce errors due to mismatch.

VCE2 = VBE+VBE3 -VBE4

= VBE

Chap 16 - 17


18/55



MOS Cascode Current Source

ID1 =ID3 =IREF AlsoIO =ID4 =ID2. So currentmirror forces output current to be approximately

equal to the reference current. If all transistors are

matched with equal W/L ratios,

VDS2 = VGS1+ VGS3 -VGS4 = VGS= VDS1

From the small-signal model,

24241

4 or

for

mg

or

outR m

4

4

2

4l

m

l

mff

CSV

Chap 16 - 18


19/55



Bipolar Cascode Current Source

IC1 =IC3 =IREF AlsoIO =IC4 =IC2. So current

mirror forces output current to be approximately

equal to the reference current. If all transistors are

matched,

VCE2 = VBE1+ VBE3 -VBE4 = VGS= VCE1

From the small-signal model,

244 oro

outRb

2

44 AVoCS

Vb

Chap 16 - 19


20/55



Electronic Current Source Design

ExampleProblem: Design IC current source to meet given specifications.

Given data:IREF= 25 mA, VSS = 20 V, l= 0.02 V-1,VTN = 0.75 V,Kn= 50

mA/V2,VA = 50 V,bFO = 100,ISO = 0.5 fA

Analysis: MR


21/55



Reference Current Generation

Reference current is required by all current mirrors. When resistor is used, sources output current is directly

proportional to VEE.

Gate-source voltages of MOSFETs can be large andseveral MOS devices can be connected in series between

supplies to eliminate large resistors.

VDD + VSS= VSG4+ VGS3 + VGS1 and ID3 =ID1= I4

Change in supply directly alters gate-source voltage of

MOSFETs and the reference current. BJTs cant similarly be connected in series due to small

fixed voltage developed across each diode and

exponential relation between voltage and current.

RBE

VEE

V

REFI

Chap 16 - 21


22/55



Supply-Independent Biasing: JFET

Constant Reference Current Source P-channel JFETs can be used to set a

fixed reference current.

JFET is operating with VSG=0 and thus

ID=IDSS, assuming that VSD is large

enough to pinch-off the JFET.

Depletion-mode MOSFETs can be used

in similar manner.

Since both these methods require special

IC processes, other methods are

preferred.

Chap 16 - 22


23/55



Supply-Independent Biasing: VBE-based

Reference and Widlar Current Source

Output current is determined by

base-emitter voltage ofQ1 . For

high current gain,

1

V4.1

1

211 R

EEV

RBE

VBE

VEE

V

CI

11

V4.1ln

2

2

V7.0

2

11

2

1222

RS

IEEV

RT

V

OI

RRBEV

BI

RBEV

FEI

FOI

Output current is now logarithmically

dependent on supply voltage. However, it is

temperature dependent due to temperature

coefficients of both VBEandR.

Widlar source also achieves similar supplyindependence of output current.

1

2ln2

EAE

A

OIREF

I

RT

V

EI

FOI

Chap 16 - 23


24/55


25/55



Variation of Reference Cell Current with

Power Supply Fluctuations

R is absorbed into transistor model in

simplified small-signal circuit model.

EEVCCVxv or SSVDDVxv

2v'

21v)'

21(xi o

gm

gm

g

)2

vxv(4i

mgUsing

Determinant of these nodal equations is:

2

v

4xv)

31

(xv)

34

(

m

ng

o

g

m

g

o

g

m

ng

2

v

4xv)

31

(xv)

34

(

m

ng

o

g

m

g

o

g

m

ng

2)v'

24(

1v'

2xv4 o

gm

gm

gm

g

32

1

'

2141

Fm

g

Om

gm

g

n-mgmg m

Chap 16 - 25


26/55



Variation of Reference Cell Current with

Power Supply Fluctuations (contd.)

xv)'23

(41

v

f

ogmgOo

ngm

gm

gm

xv2

1

'21

412v

f

mgO

mgm

gn

mg

mg

m

1

'211

'2

1

'21

3

xixv

mgmgn

nor

mgm

gor

outR 1

1

'2

m

gm

g

nfor .This is important

for stability. Because of positive

feedback, overall output resistance

is reduced.

Output resistances of the Widlar source and current mirror, ro2and ro3determine sensitivity to power supply variations. To improve output resistance

of Widlar portion , cascode sources can be used and Wilson sources can be

used to improve output resistance of current mirror.

Chap 16 - 26


27/55



Reference Current Design Example

Problem: Design supply-independent current source to meet givenspecifications.

Given data: output current= 45 mA,T=300 K, total current


28/55



Bandgap Reference

To make the voltage reference

temperature independent,

negative temperature coefficient

of base-emitter junction can be

canceled by positive

temperature coefficient of

scaled PTAT voltage.

PTATGV

BEV

BGV

To have zero temperature coefficient,

VGO is silicon bandgap voltage at 0K (1.12

V)

BEV

TV

GOV

PTATGV

TPTAT

VG

T

TV

GOV

BEV

TPTATVG

TBEV

TBGV

3

03

TV

GOV

BGV 3

Chap 16 - 28


29/55



Bandgap Reference Circuit Realization

1

2ln

1

221E

AE

A

TVR

R

BEVBGV

PTATV

BEV

TV

GOV

TPTATV

TBEV

R

R

2

31

2

1

1

2

Circuit gain G =2R2 /R1.

Voltages other than1.2 V can be obtained

by a adding resistive

voltage divider.

BG

V

R

R

O

V

3

41

Chap 16 - 29


30/55



Bandgap Reference Example

Problem: Design bandgap reference to meet given specifications.Given data: VO = 5 V,T=320 K, collector current= 25 mA,IS= 0.5 fA.

Assumptions:VA is infinite,bFO is infinite,AE2 =10AE1, drop across R =2 V.

Analysis:

W

k539.2A25mV47.63PTAT

1

mV47.63mV)ln(10)57.27(1

2

2

1lnPTAT

mEI

VR

EA

EA

CI

CI

q

kTV

V6792.0

1

1lnTBE1

SIC

I

VV

124.42

3

1

2

PTATV

BEV

TV

GOV

R

R

W k47.101

124.42

RR

V203.1

1

221

PTAT

VR

RBE

VBG

V

157.31

3

4

BGV

OV

R

R

k24

33 I

BGVR k9.75

34

IBG

VO

VR

W k80A25

V2m

R

Chap 16 - 30


31/55

Jaeger/Blalock7/1/03 Microelectronic Circuit DesignMcGraw-Hill

CMOS Differential Amplifier with

Active Load: DC Analysis

ID3 =ID1= ID2 =ID4 =IDSS/2.

Mirror ratio is set byM3 andM4 and is exactlyunity when VSD4 = VSD3 and thus VSD1 = VSD2.

Differential amplifier is completely balanced at

dc when:

TP

V

pKSS

I

DDV

SDV

DDV

OV

4

TPV

pKSS

I

SGV

SDV

DDVpKSS

I

nKSS

I

TPVTNVDDVDSV

33

1

Chap 16 - 31


32/55


CMOS Differential Amplifier with Active

Load: Differential-Mode Signal Analysis

The differential amplifier can be

represented by its Norton equivalent.

Total short circuit output current:

idv

22id

v22oi m

gmg

Thevenin equivalent output resistance:

Differential-mode voltage gain:

42 or

or

thR

2

242

for

or

m2g

thRscidm

Am

Chap 16 - 32


33/55


CMOS Differential Amplifier with

Active Load: Output Resistance

AssumeRSS>>1/gm1.

Resistance looking into drain ofM2 (C-G transistor) is:

22

1

1

21

221

2 or

mgm

gor

SR

mg

or

o2R

Drain current ofM2 (vx/2ro2)is replicated by

current mirror as drain current ofM4. Total

current from source is 2(vx/2ro2)= vx/ro2.

Total current is:

Output resistance is:

4

xv

2

xv

iTx

or

or

42 or

or

odR

Chap 16 - 33


34/55



Load: Common-Mode Signal Analysis

From small-signal equivalent:

where it is assumed thatgm4 =gm3 and Goc


35/55



Load: CMRR and Mismatch Contribution

SSR

mg

for

or

SSRmgf

cmAdmA

232

/3

1

232CMRR mm

forro3 = ro2.

With mismatched transistors, assuming

vd1=0 and gate-sourcevoltages are equal,

With vgs= vic- vs, vd1=0 and vd2=0,

svoggsvmgdi

disci 21

icv

icv

SSRmgSS

Rmg

sv

21

2

ic

v

fSSRmgic

v

SSRmg

SSRog

gs

v

m

1

2

1

21

21

fog

og

fSSRmgmg

mg

or

ormg

cmA

dmAcmA

mm

11

2

1

42

1-CMRR

Chap 16 - 35


36/55


Bipolar Differential Amplifier with

Active Load: DC Analysis

IC3 =IC1= IC2 =IC4 =IEE/2.

IfbFO is very large, currentmirror ratio is set by Q3 and

Q4 and is exactly 1 when VEC4

= VEC3=VEB.

EBV

CCV

OV

CCV

BEV

EBV

CCV

EV

CV

CEV

CEV )()(

21

Differential amplifier is completely balanced at dc when:

Current gain defect in current mirror upsets dc balance.

As longs as BJTs are in forward-active region, VEC4

adjusts to make up for current-gain defect.

AsIC2 =IC4 andIC2=IC1, MR must be

1.

FO4AVCE

V

AV

CE4V

C1I

C4I

b

21

)/(1

FO4A

V

EBVEC4V b

2

This causes an equivalentinput offset voltage of

ddA

EBV

EC4V

ddA

EC3V

EC4V

OSV

Chap 16 - 36


37/55


Bipolar Differential Amplifier with Active

Load: Differential-Mode Signal Analysis

To eliminate offset error, buffered

current mirror active load is used.

Total short circuit output current:

idv

22id

v22sci m

gmg

Thevenin equivalentoutput resistance:

Differential-mode voltage gain:42 o

ror

thR

LRm2gLRororm2gdm

vth

RL

Rsci

dmA

42

With added stages,

output resistance of

differential input

stage is:

5542 rrororeqR

5/

25

2

CI

CI

o

eqRmg

dmA

b

Chap 16 - 37


38/55


Bipolar Differential Amplifier with Active

Load: Common-Mode Signal Analysis

oroEERicv

CR ic

vccA

oci b12 1

EE

Rorof2

icv

or

mgEE

Roroicvsci 2

11

)2

2(3

12112

bmb

From small-signal equivalent:

1

22

1

2

1

3

2

/

2CMRR

EER

mg

fooicv

thRsci

thR

mg

mbb

EE

Rorooicvsci 2

112bb

Current forced in differential output resistance

is doubled due to current mirror action.

Due to mismatches,

fog

og

fSSR

mgg

g

mg

mg

mm

11

2

11-CMRR

Chap 16 - 38


39/55


Active Loads in Op Amps: Voltage Gain

2

5)52

(2

))10

(5

(52

2

2)

42

(

21f

or

or

mg

or

GGR

or

mg

vtA

f

o

r

o

r

m

g

vt

A

m

m

4

52

21)1(

21bvov

avbv

idvav

ff

vtA

vtA

vtA

vtA

dmA

mm

Gain of output stage is approximately 1.

If Wilson stage is used in first-stage activeload,Avt1 = mf2. If current sourceM10 is

replaced by a Wilson or cascode source,

Avt2 = mf5.Overall gain can be raised to:

52 ffdm

A mm

Chap 16 - 39


40/55


Active Loads in Op Amps: DC Design

Considerations

When op amp with active load is

operated in closed-loop configuration,

ID5 =I2, the output current of source

M10.

For minimum offset voltage, (W/L)5

must be such that VSG5 = VSD4 = VSG3

precisely setsID5 =I2 and accounts for

VDSand ldifferences betweenM5 and

M10.

RGG, (W/L)6 and (W/L)7 determine

quiescent current in class-AB output

stage.

VGS11 can be used to bias output stage

in place ofRGG.

Chap 16 - 40


41/55


CMOS Op Amp Analysis

Problem: Find small-signal characteristics of given CMOS op amp.

Given data:IREF= 100 mA, VDD = VSS = 5 V, VTN= 1 V, VTP= -0.75 V,

Kn= 25 mA/V2,Kp= 10 mA/V

2, l= 0.0125 V-1

Analysis:A100

12

REF

I/2I

D

I

A200225

REFII

DI

000,16

5

52

5

1

2

22

2

141

4

52

DI

pK

DI

nK

ffdm

A

ll

mm

ic

Rid

R

V54.2

11

112

1111

n

KD

I

TNV

GSV

AsID6=ID7, VGS6= VSG7 = VGS11/2

A7.33

2)V75.0V27.1(2V

A

2

25067

DI

DI

S4103.167

mgmg

W k85.3

7

1

6

1

mg

mgout

R

Chap 16 - 41


42/55


Bipolar Op Amps

Q1 to Q4 form differential input

stage with active load.

First stage is followed by high-

gain C-E amplifier, Q5 and its

current source load, Q8.

Load resistance is driven by class-AB output stage formed by Q6 and

Q7 , biased byI2 and diodes Q11

and Q12.

2

55

5

225

5555

2

)1()16

(85252

321

fo

CIC

Ior

mgr

mg

mgm

g

LR

oor

or

mgr

mg

vt

A

vt

A

vt

A

dm

A

mb

b

Chap 16 - 42


43/55


Bipolar Op Amps with Improved

Voltage Gain

To improve gain, 2-transistor Darlington circuit

with current gain ofbo1bo2, amplification factormf2 /4, output resistance ro2 /2 and input

resistance 2bo1 r2,is used to replace Q5. It

requires emitter-base bias of 2VEB.

Buffered current mirror maintains dcbalance at collectors ofQ3 and Q4.

2

7)

1437

2(

27

2

2

23.0)

76

2

2

2(

21f

oro

rm

g

vtA

f

r

o

or

m

g

vt

A

m

m

b

UsingI2 =2I1,bo=50, VA=60 V,

VCE= 15 V,

51015.422

72

321

ff

vtA

vtA

vtA

dmA

mm

Chap 16 - 43


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Input Stage Breakdown in Bipolar Op

Amps

Input stage of bipolar op amp has no

overvoltage protection and can easily be

destroyed by large input voltage

differences due to fault conditions or

unavoidable transients, such as slew-rate

limited recovery.

In worst-case fault condition, B-E junction

ofQ1 is forward-biased and that ofQ2 is

reverse-biased by(VCC+ VEE- VBE1). IfVCC

= VEE=22 V, reverse voltage > 41 V.

Early IC op amps used external

diode protection across input

terminals to limit differential input

voltage to about 1.4 V at the cost of

extra components.

Chap 16 - 44


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mA741 Op Amp

High gain, input resistance andCMRR, low output resistance

and good frequency response.

Fully protected input and output

stages and offset adjustment port.

Input stage is a differentialamplifier with buffered current

mirror active load.

Two stages of voltage gain

(emitter-follower driving C-E

amplifier) followed by short-circuit protected class-AB output

stage buffered from second gain

stage by emitter follower.

Chap 16 - 45


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McGraw-Hill

mA741 Op Amp: Bias Circuitry

mA733.0

5

2

R

BEV

EEV

CCV

REF

I

1

ln50001 I

REFI

TV

ISolving iteratively,

I1 =18.4 mA.

Assuming VO =0, VCC=15 V and neglecting dropacrossR7 andR8 ,

VEC23 = 15+1.4=16.4 V and VEC24 = 15-0.7 =14.3 V

Given VA=60 V,bFO =50,

A666)50/2()60/7.0(1

)60/4.16(1mA)733.0(75.02 m I

A216)50/2()60/7.0(1

)60/4.14(1mA)733.0(25.0

3m

I

W

k115

mA666.0

16.4VV60

2

23232

I

ECV

AV

R

W

k344mA216.0

14.3VV60

3

24243 I

ECV

AV

R

Chap 16 - 46


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McGraw-Hill

mA741 Op Amp:DC Analysis of Input

Stage

/2IC

I161

42

)8

/8

()8

/2(1

)8

/8

(1

22

1 BI

AV

EBV

FO

AV

ECV

CII

b

41

412

2222 B

IFO

FO

FOEI

FCI

bbb

4

1

8

2

8

881

121

2

FOFOAV

EBV

ECV

I

CI

bb

214

4

2

12

444 CI

FO

FO

FO

FOEI

FCI

b

b

b

b

CCV

BEV

EBV

CCV

CEV

CEV

2921

V1.2

V)4.1(--V7.0333

EEV

EEV

CV

EV

ECV

V7.07

V4.18

EEV

CEV

CCV

ECV

Chap 16 - 47


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McGraw-Hill

mA741 Op Amp: Input Stage Bias

Currents Example

Problem: Calculate bias currents in the 741 input stage with given parameters.

Given data:I1 = 18 mA,VCC= VEE= 15 V,VAnpn = 75 V,bFOnpn = 150, VApnp = 60

V,bFOpnp = 60

Analysis:

A32.7

)160)(151/150(

1

)60/7.0()50/2(1

)60/4.16(11

2A18

21

V4.16318

mm

CI

CI

EBV

BEV

CCV

ECV

A25.735

A25.72151

150

61

60

214

4

2

12

2

2444436

m

m

b

b

b

b

CI

CI

CI

CI

FO

FO

FO

FO

F

CI

FEI

FCI

CI

CI

Chap 16 - 48


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mA741 Op Amp: Voltage Gain (Input

Stage)

idS)v41046.1(

idv

220

2id

v2-i2oi

C

Img

W

M54.6

4

79.0

4

2

6

3.1

42

261

646

o

r

o

r

o

r

orR

mg

or

outR

outR

thR

Based on values in Norton equivalent, open-

circuit voltage gain of first stage is -955.

Chap 16 - 50


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McGraw-Hill

mA741 Op Amp: Voltage Gain (Second

Stage)

k189

10

1010

A8.19k5011

11

111010

CI

or

BV

F

CI

EICI

b

mb

k63.511

r

To findy11 andy21:

WW

W

.4M211

k501101011

k7.201001111111

1

inR

ory

or

inR

b

b

1v921.0

11k501

1010

11k501

101vev

W

W

inR

or

inR

o

b

b

1v006701.0100)11

/1( e

v

2i Wm

g

mS70.621

y

Chap 16 - 51


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McGraw-Hill

mA741 Op Amp: Voltage Gain (Second

Stage contd.)

To findy12 andy22:

Open-circuit voltage gain for the first two

stages is:

W

W

k1.8911222

k40710011

11111

1

outRRy

ER

mg

or

outR

idv000,153)

idv256(597

2v

idv256

idv2.4M6.54M41046.1

1v

1v597

1v)k1.89(00670.0

2v

WW

W

Combined model for first and

second stages is:

Chap 16 - 52


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McGraw-Hill

mA741 Op Amp: Voltage Gain (Output

Stage)

From simplified output stage without

short-circuit protection:

W

W

W

M27.81

1121212

k1622313141

k3041

15152

eqR

or

inR

eqRR

dr

dr

eqR

L

R

o

r

eq

R

b

b

W

W

2.261

15

315

k08.2

112

12212

131433

o

eqRroR

o

yr

dr

drR

eqR

b

b

Actual op amp output resistance is:

W 537

RoRoutR

Chap 16 - 53


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McGraw-Hill

Gilbert Analog Multiplier

Q1 and Q2 have significant emitterdegeneration, transconductance of

the pair is 1/R1.Forv1


55/55

Jaeger/Blalock Microelectronic Circ it Design

Four-Quadrant Gilbert Analog Multiplier

with Predistortion Circuit

Forv3

Chap16-Analog Integrated Circuits

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