Analog Integrated Circuits Jieh-Tsorng Wu 6 de febrero de 2003 1. Introduction 2. PN Junctions and Bipolar Junction Transis- tors PN Junctions Small-Signal Junction Capacitance Large-Signal Junction Capacitance PN Junction in Forward Bias PN Junction Avalanche Breakdown PN Junction Breakdown Bipolar Junction Transistor (BJT) Minority Carrier Current in the Base Region Gummel Number (G) Base Transport Current Forward Current Gain BJT DC Large-Signal Model in Forward- Active Region Dependence of BF on Operating Condition Collector Voltage Effects Base Transport Model Ebers-Moll Model Leakage Current Common-Base Transistor Breakdown Common-Emitter Transistor Breakdown Small-Signal Model of Forward-Biased BJT Charge Storage Complete Small-Signal Model with Extrinsic Components Typical values of Extrinsic Components 3. MOS Transistors MOS Transistors Strong Inversion Channel Charge Transfer Characteristics Simplified Channel Charge Transfer Charac- teristics MOST I-V Characteristics Threshold Voltage Square-Law I-V Characteristics Channel-Length Modulation MOST Small-Signal Model in Saturation Re- gion OST Small-Signal Model in Saturation Re- gion MOST Small-Signal Capacitances in Satura- tion Region Channel Capacitance in Saturation Region Complete MOST Small-Signal Model in Sat- uration Region MOST Small-Signal Model in Triode Region MOST Small-Signal Model in Cutoff Region Carrier Velocity Saturation Effects of Carrier Velocity Saturation 1
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Analog Integrated Circuits
Jieh-Tsorng Wu
6 de febrero de 2003
1. Introduction
2. PN Junctions and Bipolar Junction Transis-tors
PN Junctions
Small-Signal Junction Capacitance
Large-Signal Junction Capacitance
PN Junction in Forward Bias
PN Junction Avalanche Breakdown
PN Junction Breakdown
Bipolar Junction Transistor (BJT)
Minority Carrier Current in the Base Region
Gummel Number (G)
Base Transport Current
Forward Current Gain
BJT DC Large-Signal Model in Forward-Active Region
Dependence of BF on Operating Condition
Collector Voltage Effects
Base Transport Model
Ebers-Moll Model
Leakage Current
Common-Base Transistor Breakdown
Common-Emitter Transistor Breakdown
Small-Signal Model of Forward-Biased BJT
Charge Storage
Complete Small-Signal Model with ExtrinsicComponents
Typical values of Extrinsic Components
3. MOS Transistors
MOS Transistors
Strong Inversion
Channel Charge Transfer Characteristics
Simplified Channel Charge Transfer Charac-teristics
MOST I-V Characteristics
Threshold Voltage
Square-Law I-V Characteristics
Channel-Length Modulation
MOST Small-Signal Model in Saturation Re-gion
OST Small-Signal Model in Saturation Re-gion
MOST Small-Signal Capacitances in Satura-tion Region
Channel Capacitance in Saturation Region
Complete MOST Small-Signal Model in Sat-uration Region
• Unmodified reproduction of these lecture notes for class or personal use is permitted.
• For commercial use, permission should be obtained from the author.
Contents 0-2 Analog ICs; Jieh-Tsorng Wu
Devices and Technologies
1. Introduction
2. PN Junctions and Bipolar Junction Transistors
3. MOS Transistors
4. Integrated Circuit Technologies
Contents 0-3 Analog ICs; Jieh-Tsorng Wu
Basic Circuits and Design Techniques
5. Single-Transistor Gain Stages
6. Multiple-Transistor Gain Stages
7. Differential Gain Stages
8. Current Mirrors and Active Loads
9. Voltage and Current References
10. Output Stages
11. Noise Analysis and Modelling
12. Feedback and Compensation
Contents 0-4 Analog ICs; Jieh-Tsorng Wu
Operational Amplifiers
13. Basic Two-Stage Operational Amplifier Design
14. Operational Amplifiers with Single-Ended Outputs
15. Fully Differential Operational Amplifiers
Contents 0-5 Analog ICs; Jieh-Tsorng Wu
Analog Functional Blocks
16. Operational Amplifiers and Their Basic Configurations
17. Analog Switches and Sample-and-Hold Circuits
18. Comparators and Offset Cancellation Techniques
19. Oscillators
Contents 0-6 Analog ICs; Jieh-Tsorng Wu
Subsystems
20. Fundamentals of Analog Filters
21. Active-RC Filters
22. MOST-C and Gm-C Filters
23. Switched-Capacitor Filters
24. Niquist-Rate Digital-to-Analog Converters
25. Niquist-Rate Analog-to-Digital Converters
26. Oversampling Converters
27. Phase-Locked Loops
Contents 0-7 Analog ICs; Jieh-Tsorng Wu
Introduction
Jieh-Tsorng Wu
July 16, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Analog Integrated Circuits
Storage MediaDiskTapeBubble
DigitalVLSI
System
Audio I/O
Transmission MediaWire PairsCoaxFiberRF
Physical Sensors & Actuators
Imagers & Displays
PowerSource
Analog/Digital Interfaces
• Usually integrated with digital VLSI circuits monolithically (mixed-signal integratedcircuits) for better performance and/or lower cost.
Introduction 1-2 Analog ICs; Jieh-Tsorng Wu
Analog Signal Processing
Analog Signals
• Always continuous in amplitude.
• Either continuous in time (s-transform) or discrete in time (z-transform).
Analog circuits provide interfaces between the analog environment of the physical worldand a digital environment. Major functions are
• Amplification.
• Filtering.
• Analog-to-digital conversion.
• Digital-to-analog conversion.
• Power supply conditioning.
Introduction 1-3 Analog ICs; Jieh-Tsorng Wu
Design for Analog Circuits
Signal path
• Small (variational) signals related by linear transfer function in the frequency domain.
• Model with linearized small-signal equivalent circuit.
• Analyze using Laplace transforms.
Biasing Circuit
• Establish operating conditions of devices in signal path.
• Concern with sensitivity to variations in temperature, supply voltage, and fabricationprocess.
• Analyze using large-signal device models.
Introduction 1-4 Analog ICs; Jieh-Tsorng Wu
Performance Considerations
• Small-signal response: gain, bandwidth, noises, . . .
• Large-signal response: settling time, distortion, . . .
• Sensitivity to device variation, temperature variation, external noises, . . .
• Cost: power dissipation, chip area, yield.
Introduction 1-5 Analog ICs; Jieh-Tsorng Wu
Design Practices
• Make simplifying assumptions that allow hand analysis.
• Keep in mind potential consequences of the assumptions.
• Use simulations to verify the design.
• Good designs are robust; i.e., insensitive to approximations in the modeling as wellas variations in temperature and fabrication process.
Introduction 1-6 Analog ICs; Jieh-Tsorng Wu
PN Junctions and Bipolar Junction Transistors
Jieh-Tsorng Wu
September 6, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
PN Junctions
Built-in potential = Ψ0 = UT lnNAND
n2i
UT =kT
q≈ 26 mV at 300K
ni ≈ 1.5 × 1010 cm−3 at 300K for Si
Solving Poisson’s equation,
W1 =
2ε(Ψ0 + VR)
qNA
(1 + NA
ND
)
1/2
W2 =
2ε(Ψ0 + VR)
qND
(1 + ND
NA
)
1/2
BJT 2-2 Analog ICs; Jieh-Tsorng Wu
Small-Signal Junction Capacitance
Depletion layer charge is Qj = qNAW1A = qNDW2A, where A is the cross-sectional area.
Depletion-region capacitance
Cj =dQj
dVR= A
[qε
2Ψ0
NAND
NA +ND
]1/2
· 1√1 + VR
Ψ0
=Cj0√1 + VR
Ψ0
BJT 2-3 Analog ICs; Jieh-Tsorng Wu
Small-Signal Junction Capacitance
• Cj can be expressed as
Cj = A · εxd
xd = W1 +W2
• In general
Cj =Cj0(
1 + VRΨ0
)m 13≤ m ≤ 1
2
– m = 1/2 for abrupt junction.– m = 1/3 for graded junction.
• In forward bias, diffusion capacitance dominates.
BJT 2-4 Analog ICs; Jieh-Tsorng Wu
Large-Signal Junction Capacitance
Depletion layer charge can be rewritten as
Qj =Cj0
1 −m· Ψ0 ·
(1 +
VR
Ψ0
)1−m
Average capacitance is defined as
Cj−av =Qj(V2) − Qj(V1)
V2 − V1
For an abrupt junction, m = 0.5,
Cj−av = 2Cj0Ψ0 ·
√1 + V2
Ψ0−√
1 + V1Ψ0
V2 − V1
• If V1 = 0 V, V2 = 5 V, and Ψ0 = 0.9 V
Cj−av = 0.56 · Cj0 ≈12Cj0
BJT 2-5 Analog ICs; Jieh-Tsorng Wu
PN Junction in Forward Bias
V D
I D
r d CT
Small-Signal Model
ID = IS(eVD/UT − 1) ≈ ISeVD/UT IS ≈ A
(1NA
+1ND
)1rd
=dID
dVD=
ID
UT
CT = Cd + Cj
Cd = τT ·ID
UT
=τT
rdτT = Transit Time
• For moderate forward-bias currents, Cd Cj , rdCT ≈ τT .
• For Schottky diode, Cd = 0.
BJT 2-6 Analog ICs; Jieh-Tsorng Wu
PN Junction Avalanche Breakdown
• The maximum electric field in the depletion region of an abrupt junction is
|Emax| =qNAW1
ε=[
2qNAND(Ψ0 + VR)
ε(NA +ND)
]1/2
|Emax| increases with both VR and doping density.
• As |Emax| → Ecrit, carriers crossing the depletion region acquire enough energyto create new electron-hole pairs when colliding with silicon atoms. The result isavalanche breakdown.
IRA = MIR M =1
1 −(
VRBV
)nBV is the breakdown voltage. And typically 3 ≤ n ≤ 6
• Ecrit is a function of doping density, which can vary from 3× 105 V/cm to 106 V/cm asNA (or ND) varying from 1015 atoms/cm3 to 1018 atoms/cm3.
BJT 2-7 Analog ICs; Jieh-Tsorng Wu
PN Junction Breakdown
Zener Breakdown
• In very heavily doped junctions where the electric field becomes large enough to stripelectrons always from the valence bonds. This process is called tunneling.
• The Zener breakdown mechanism is important only for breakdown voltages belowabout 6 V.
Punch Through
• A form of breakdown that occurs when the depletion regions of two neighboringjunctions meet.
BJT 2-8 Analog ICs; Jieh-Tsorng Wu
Bipolar Junction Transistor (BJT)
BJT 2-9 Analog ICs; Jieh-Tsorng Wu
Minority Carrier Current in the Base Region
There is a negligible flow of holes between emitter and collector junctions becauseneither can supply a significant flow of holes into the base. Thus, in the neutral baseregion,
Jp = qµppb(x)E(x) − qDp
dpb
dx= 0 ⇒ E(x) =
Dp
µp
1pb
dpb
dx=
kT
q
1pb
dpb
dx
• Note that for uniformly doped region dpb/dx = 0⇒ E(x) = 0
For electrons in the base,
Jn = qµnnb(x)E(x) + qDn
dnb
dx= kTµn
nb
pb
dpb
dx+ qDn
dnb
dx=
qDn
pb
(nb
dpb
dx+ pb
dnb
dx
)
=qDn
pb
[d (nbpb)
dx
]
BJT 2-10 Analog ICs; Jieh-Tsorng Wu
Minority Carrier Current in the Base Region
Assuming negligible recombination in the base, so that Jn is constant,
Jn
∫ WB
0
pb(x)
qDn
dx =∫ WB
0
d (nbpb)
dxdx = nb(0)pb(0) − nb(WB)pb(WB)
From the Boltzman approximation at the edges of the depletion layers,
nb(0)pb(0) = n2ieVBE/UT nb(WB)pb(WB) = n2
ieVBC/UT
Thus
Jn =qn
2i∫WB
0pbDndx
(eVBE/UT − eVBC/UT
)= JS
(eVBE/UT − eVBC/UT
)
where
JS ≡qn
2i∫WB
0pbDndx
BJT 2-11 Analog ICs; Jieh-Tsorng Wu
Gummel Number (G)
Dn is a weak function of x. Then, JS can be expressed as
JS =qn
2i∫WB
0pbDndx
=qn
2i Dn
G
where
G ≡∫ WB
0pb(x)dx ≈
∫ WB
0NA(x)dx
• The Gummel number, G, is simply the dopant concentration per unit cross-sectionalarea of the base.
• For a uniform base region, NA(x) = NA, then G = WBNA.
BJT 2-12 Analog ICs; Jieh-Tsorng Wu
Base Transport Current
The total minority carrier transport current across the base is
IT = JN × A = IS
[eVBE/UT − eVBC/UT
]where IS = JS × A =
qn2i Dn
G× A
The transport current can be separated into forward and reverse components as
IT = IS
(eVBE/UT − 1
)− IS
(eVBC/UT − 1
)= ICF + IER
• If VBE > 0 and VBC < 0, the device is biased in the forward-active region,
IT = ISeVBE/UT
• If VBE < 0 and VBC > 0, the device is biased in the inverse-active region,
IT = ISeVBC/UT
• If VBE > 0 and VBC > 0, the device is biased in the saturation region.
BJT 2-13 Analog ICs; Jieh-Tsorng Wu
Base Current
In the forward-active regionIB = IBB + IBE
• IBB is due to the recombination of holes and electrons in the base.
• IBE is due to the injection of holes from the base into the emitter.
Define Qe as the minority carrier charge in the base region
Qe = qA
∫ WB
0nb(x)dx or Qe =
12qAWBnb(0) =
12qAWB
n2i
NA
eVBE/UT
IBB is related to Qe by the lifetime of minority carriers in the base, τb
IBB =Qe
τb=
12
qAWB
τb
n2i
NA
· eVBE/UT
BJT 2-14 Analog ICs; Jieh-Tsorng Wu
Base Current
IBE depends on the gradient of minority carriers (holes) in the emitter.
• For a “long-base” emitter (all minority carriers recombine in the quasi-neutral region)with a diffusion length Lp
IBE =qADp
Lp
peoeVBE/UT =
qADp
Lp
n2i
ND
eVBE/UT ND = Emitter Doner Density
• For a “short-base” emitter (all recombination at the contact) with emitter width WE , WE
simply replaces Lp in the expression for IBE .
The total base current in the forward-active region is
IB =
[12
qAWB
τB
n2i
NA
+qADp
Lp
n2i
ND
]eVBE/UT
• In modern narrow-base transistors IBE IBB.
BJT 2-15 Analog ICs; Jieh-Tsorng Wu
Forward Current Gain
In the forward-active region, the forward current gain is
βF ≡IC
IB=
1W 2B
2τbDn+
Dp
Dn
WB
LP
NA
ND
The emitter current is
IE = −(IC + IB) = −(IC +
IC
βF
)= −
IC
αF
where
αF ≡ −IC
IE=
βF
βF + 1=
1
1 + 1βF
=1
1 +W 2B
2τbDn+
Dp
Dn
WB
LP
NA
ND
≈ αT · γ
αT =1
1 +W 2B
2τBDn
γ =1
1 +Dp
Dn
WB
LP
NA
ND
• αT is called the base transport factor, and γ is called the emitter injection efficiency.
BJT 2-16 Analog ICs; Jieh-Tsorng Wu
BJT DC Large-Signal Model in Forward-Active Region
VV BE(on)BE
I E
C
E
IB II C
B
E
C
B I
I
E
B C
IB =IS
βF
eVBE/UT IC = βF IB
• The voltage on the emitter junction can be approximated by a constant VBE (on).
• VBE (on) is usually 0.6 V to 0.8 V, and has a temperature coefficient of −2 mV/C.
BJT 2-17 Analog ICs; Jieh-Tsorng Wu
Dependence of βF on Operating Condition
• At high currents, due to high-level injection
IC → ISeVBE/(2UT )
• At low currents, due to recombination in the B-E depletion region
IB → ISeVBE/(2UT )
BJT 2-18 Analog ICs; Jieh-Tsorng Wu
Collector Voltage Effects
In the forward-active region, an increase ∆VCE in VCE results in an increase in thecollector depletion layer width, thereby reducing WB by ∆WB, and increasing IC.
IC = ISeVBE/UT = A
qn2i Dn
GeVBE/UT G = Gummel number
∂IC
∂VCE= −A
qn2i Dn
G2eVBE/UT · dG
dVCE= −
IC
G· dGdVCE
BJT 2-19 Analog ICs; Jieh-Tsorng Wu
Collector Voltage Effects
For a uniform-base transistor
G = WBNA and∂IC
∂VCE= −
IC
WB
·dWB
dVCE
• dWB/dVCE is typically a weak function of VCE for a reverse biased collector junctionand is often assumed to be constant.
The Early voltage, VA, is given by
VA =IC
∂IC/∂VCE= −WB
1
dWB/dVCE
The influence of changes in VCE on IC can thus be represented as
IC = ISeVBE/UT
(1 +
VCE
VA
)
• Typical values of VA are 15–100 V.
BJT 2-20 Analog ICs; Jieh-Tsorng Wu
Base Transport Model
B
E
C
IT
IC
IE
IS/βR
IS/βF
IT = IS
(eVBE/UT − eVBC/UT
)IC = IT −
IS
βR
(eVBC/UT − 1
)IE = −IT −
IS
βF
(eVBE/UT − 1
)
IB =IS
βF
(eVBE/UT − 1
)+
IS
βR
(eVBC/UT − 1
)
BJT 2-21 Analog ICs; Jieh-Tsorng Wu
Ebers-Moll Model
RecallingIT = IS
(eVBE/UT − eVBC/UT
)IC = IT −
IS
βR
(eVBC/UT − 1
)IE = −IT −
IS
βF
(eVBE/UT − 1
)SPICE uses the base transport model with the equations rewritten as:
IC = IS
(eVBE/UT − 1
)− IS
(1 +
1βR
)(eVBC/UT − 1
)= IS
(eVBE/UT − 1
)−
IS
αR
(eVBC/UT − 1
)
IE = −IS(
1 +1βF
)(eVBE/UT − 1
)−IS(eVBC/UT − 1
)= −
IS
αF
(eVBE/UT − 1
)−IS(eVBC/UT − 1
)
• Note that, in the classical Ebers-Moll model, parameters IES and ICS are defined suchthat
αF IES = αRICS = IS
BJT 2-22 Analog ICs; Jieh-Tsorng Wu
Leakage Current
In the forward-active region, eVBE/UT 1 and eVBC/UT 1, then
IC ≈ ISeVBE/UT +
IS
αR
IE ≈ −IS
αF
eVBE/UT − IS
thusISe
VBE/UT = −αF IE − αF IS
and
IC = −αF IE +(
1αR
− αF
)IS = −αF IE + ICO
where
ICO ≡ (1 − αF αR)IS
αR
• ICO is the collector-base leakage current with the emitter open.
• In practice, because of surface leakage effects, ICO is several orders of magnitudelarger than the value predicted by the above definition.
BJT 2-23 Analog ICs; Jieh-Tsorng Wu
Common-Base Transistor Breakdown
• Avalanche multiplication at the junctionsof a BJT limits the voltage that can besustained.
• BVCBO is the breakdown voltage of C-Bjunction with IE = 0.
BVEBO is much less than BVCBO.
Neglecting leakage currents
IC = −αF IEM where M =1
1 −(
VCBBVCBO
)n
BJT 2-24 Analog ICs; Jieh-Tsorng Wu
Common-Emitter Transistor Breakdown
IC
IB
VCE
BJT 2-25 Analog ICs; Jieh-Tsorng Wu
Common-Emitter Transistor Breakdown
In this configuration, holes generated in the avalanche process are swept into the basewhere they act as a supply of base current. The avalanche current is thus effectivelyamplified by βF .
IB = −(IC + IE ) = −IC +IC
MαF
⇒ IC =(
MαF
1 −MαF
)IB
where M is as defined above for the common-base case.
BVCEO is defined as the value of VCE for which IC → ∞; that is, for which MαF → 1.Assume VCB ≈ VCE , then
Mα =αF
1 −(BVCEO
BVCBO
)n = 1 ⇒BVCEO
BVCBO= (1 − αF )1/n =
1
(βF + 1)1/n≈ 1
β1/nF
• Note: Here must use value of BVCBO for intrinsic transistor. Actual BVCBO is lower thanthis because of sidewall effects.
Single-T Gain Stages 5-5 Analog ICs; Jieh-Tsorng Wu
Common-Source Amplifier
+
-
vin
VIN
RS v + Vo O
LZ
VDD
M1
Vo = VDD − Id · RL = VDD −12µnCox
W
L(Vi − Vtn)2 · RL
• DC voltage VI is chosen to bias M1 so that M1 is in active (saturation) region and itsdrain voltage is near the midpoint of the output swing (VO ≈ VDD/2).
Single-T Gain Stages 5-6 Analog ICs; Jieh-Tsorng Wu
Differential Gain Stages 7-11 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Common-Mode Half Circuit
VCC VCC
VEE VEE
Q1 Q2 Q1
RC RCRC
RSRSRS
2REE2REE 2REE
ix
voc vocvoc
vicvic vic
ix = 0 ⇒ Acm =voc
vic= −
gmRC
1 + 2gmREE
αo
≈ −RC
2REE
Differential Gain Stages 7-12 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Input Resistances
i1
R
vi1vi1
Rid2
Rid2
Ric2
vi1vid
ic RicR
Assume RS = 0 and rb = 0. When vic = 0, ib1 = −ib2 ≡ ibd ,
Differential-Mode Input Resistance = Rid ≡vid
ibd
∣∣∣∣vic=0
= 2rπ
When vid = 0, ib1 = ib2 ≡ ibc,
Common-Mode Input Resistance = Ric ≡vic
ibc
∣∣∣∣vid=0
= rπ + 2REE (βo + 1) ≈ 2βoREE
In general
ib1 = +vid
Rid
+vic
Ric
ib2 = −vid
Rid
+vic
Ric
Differential Gain Stages 7-13 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Frequency Response
VCC VCC
Q1
Differential-Mode
Q1
Common-Mode
RCRC
RSRS
2REE
CE
2
vid2
vod2
vic
voc
|Adm|
|Acm|
CMRR = |Adm||Acm|
ω
ωzE p1
Differential Gain Stages 7-14 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Frequency Response
• Using the Miller approximation, the differential Response can be written as
Adm(s) =vod
vid≈
Adm(0)
1 − s/p1
Adm(0) = −gmRC
(rπ
RS + rb + rπ
)p1 = − 1
Ct[(RS + rb)‖rπ]Ct = Cπ + Cµ(1 + gmRC)
• Because REE is usually large, the common-mode response is typically dominated bythe time constant at the tail node of the pair.
Acm(s) =voc
vic≈ −
RC
ZE (s)≈ Acm(0)
(1 − s/zE
)ZE (s) =
11
2REE+ s
CE
2
=2REE
1 + sCEREE
Acm(0) = −RC
2REE
zE = − 1REECE
Differential Gain Stages 7-15 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Input Offset Voltage and Current
VEE
V o
V i
I
VCC
RC1 R
EE
C2
VCC
RCRC
V OS
I OS
V
2
VEE
I EE
V o
i
Q1 Q2 Q1 Q2
Circuit with No Mismatches
• VOS and IOS is equal to the value of VID = VI1 − VI2 and IBD = IB1 − IB2 that must beapplied to the input to drive VOD = 0.
Differential Gain Stages 7-16 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Input Offset Voltage
For BJTs in the forward-active region,
IC = ISeVBE/UT VBE = UT ln
IC
ISIS = A
qn2i Dn
G(VCB)
The output condition is
VOD = −(IC1RC1 − IC2RC2) = 0 ⇒IC1
IC2=
RC2
RC1
Since VOS = VID = VBE1 − VBE2, we have
VOS = UT lnIC1
IS1− UT ln
IC2
IS2= UT ln
(IC1
IC2
IS2
IS1
)= UT ln
[RC2
RC1·A2
A1·G1(VCB1)
G2(VCB2)
]
Differential Gain Stages 7-17 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Input Offset Voltage
To describe the mismatch in the components, using
∆X = X1 − X2 X =X1 + X2
2⇒ X1 = X +
∆X
2X2 = X − ∆X
2
Then
VOS = UT ln
RC −
∆RC
2
RC + ∆RC
2
·A − ∆A
2
A + ∆A2
·G + ∆G
2
G − ∆G2
·
= UT ln
1 − 1
2∆RC
RC
1 + 12∆RC
RC
·1 − 1
2∆AA
1 + 12∆AA
·1 + 1
2∆GG
1 − 12∆GG
From Taylor series, if y 1, ln(1 + y) = y − y2
2 + y3
3 − · · · ≈ y . We have
VOS ≈ UT
(−∆RC
RC
− ∆A
A+∆G
G
)or VOS = UT
(−∆RC
RC
−∆IS
IS
)
Differential Gain Stages 7-18 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Input Offset Voltage
• The offset voltage drift due to temperature variation is
dVOS
dT=
d
dT
[kT
q
(−∆RC
RC
−∆IS
IS
)]=
k
q
(−∆RC
RC
−∆IS
IS
)=
VOS
T
• Nulling VOS usually doesn’t null dVOS/dT because of how it is accomplished.
• VOS drifts in the 1 µV/C range can be obtained with careful design.
RC2RC1
R R
VCC
RC1
xx
C2R
VCC
Q1 Q2Q1 Q2
Differential Gain Stages 7-19 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Input Offset Current
The input offset current is defined as
IOS ≡ IBD|VOD=0 = IB1 − IB2 =IC1
βF 1−
IC2
βF 2
As before, the formula can be arranged as
IOS =IC + ∆IC
2
βF + ∆βF
2
−IC −
∆IC2
βF −∆βF
2
≈IC
βF
(∆IC
IC−∆βF
βF
)
Since VOD = 0, we have
IC1RC1 = IC2RC2 ⇒∆IC
IC= −
∆RC
RC
⇒ IOS ≈ −IC
βF
(∆RC
RC
+∆βF
βF
)
• A typical βF mismatch distribution displays a deviation of about 10%.
Differential Gain Stages 7-20 Analog ICs; Jieh-Tsorng Wu
Source-Coupled Pair Input Offset Voltage
M2M1M2M1
SS
RD1 RD2 RDRD
V OS
V i
I SS
V o
VDD VDD
I
VSS VSS
Circuit with No Mismatches
iV
oV
VOS = VGS1 − VGS2 VGS = Vt +
√2ID
k′(W/L)k′ = µCox
Differential Gain Stages 7-21 Analog ICs; Jieh-Tsorng Wu
Source-Coupled Pair Input Offset Voltage
Since VOD = 0, we have
ID1RD1 = ID2RD2 ⇒∆ID
ID= −
∆RD
RD
The offset voltage is
VOS = VGS1 − VGS2 = ∆Vt +
√2ID
k′(W/L)×
√√√√√ 1 + 1
2∆IDID
1 + 12∆(W/L)(W/L)
−
√√√√√ 1 − 12∆IDID
1 − 12∆(W/L)(W/L)
Using Taylor series,
VOS ≈ ∆Vt +VGS − Vt
2
[∆ID
ID−∆(W/L)
(W/L)
]≈ ∆Vt +
VGS − Vt
2
[−∆RD
RD
−∆(W/L)
(W/L)
]
VGS − Vt ≡√
2IDk′(W/L)
= Vov =
√2[(ID1 + ID2)/2]
k′(W/L)=
√ISS
k′(W/L)
Differential Gain Stages 7-22 Analog ICs; Jieh-Tsorng Wu
Source-Coupled Pair Input Offset Voltage
• ∆Vt can be minimized by careful layout. Large-geometry structures can achieve a ∆Vtwith standard deviations on the order of 2 mV in modern MOS process.
• Due to the VGS − Vt term, offset in MOST pairs is typically 10 times larger than that ofBJT pairs.
• Both Vt and Vov have a strong temperature dependence, affecting VGS in oppositedirections.
• dVOS/dT in MOST pairs is not well correlated with VOS , unlike BJT pairs.
Differential Gain Stages 7-23 Analog ICs; Jieh-Tsorng Wu
Unbalanced Resistor Circuit Analysis
v11R
i1
v22R
i2
RR
c
Differential HC Common-Mode HC
id2
∆R2
ic 2∆R
cidi
2
vdv
2
vd = v1 − v2 = i1R1 − i2R2 =(ic +
id
2
)(R +
∆R
2
)−(ic −
id
2
)(R − ∆R
2
)= idR + ic(∆R)
vc =v1 + v2
2=
(ic +
id2
) (R + ∆R
2
)+(ic −
id2
) (R − ∆R
2
)2
= icR + id∆R
4
Differential Gain Stages 7-24 Analog ICs; Jieh-Tsorng Wu
Unbalanced gm Circuit Analysis
i1 i2
cidi
2
g
Common-Mode HCDifferential HC
mg2mg
gm1 1v gm2 2v
∆cv∆gm
22dv
mv
cv2d
id = i1 − i2 =(gm +
∆gm
2
)(vc +
vd
2
)−(gm −
∆gm
2
)(vc −
vd
2
)= gmvd + ∆gmvc
ic =i1 + i2
2=
(gm + ∆gm
2
) (vc +
vd2
)−(gm −
∆gm2
) (vc −
vd2
)2
= gmvc +∆gmvd
4
Differential Gain Stages 7-25 Analog ICs; Jieh-Tsorng Wu
Unbalanced Differential Amplifier
c
1v
1Ri
2R
∆gm
2mg∆
vo1 vo1
2
v
R
Common-Mode HC
SSR
gm2 vi2gm1 vi1
2
v
s
Differential HC
R
vgm id2
v
v1
2odv
di
2ic 2∆R ∆
id
R2
SS2R
i
oc
d
icv
2
gm 1v
If ∆R = 0 and ∆gm = 0, we have
Adm = −gmR Acm = −gmR
1 + 2gmRSS
Acdm = 0 Adcm = 0
Differential Gain Stages 7-26 Analog ICs; Jieh-Tsorng Wu
Unbalanced Differential Amplifier
Including mismatches, the voltage gains are
[vodvoc
]=[Adm Acdm
Adcm Acm
][vidvic
]
where
Adm =vod
vid
∣∣∣∣vic=0
= −gmR +∆gmRSS
∆gm2 R − ∆gm
2∆R2
1 + 2gmRSS
Acdm =vod
vic
∣∣∣∣vid=0
= −gm∆R + ∆gmR
1 + 2gmRSS
Adcm =voc
vid
∣∣∣∣vid=0
= −14
gm∆R +
∆gmR − gm∆R
(2gmRSS
(∆gm2gm
)2)
1 + 2gmRSS
Acm =voc
vic
∣∣∣∣vid=0
= −gmR + ∆gm
2∆R2
1 + 2gmRSS
Differential Gain Stages 7-27 Analog ICs; Jieh-Tsorng Wu
Simplified Analysis for Unbalanced Differential Amplifier
First assume no mismatches, and find Adm, Acm, vod , id , voc, ic, and v1,
Adm = −gmR Acm = −gmR
1 + 2gmRSS
vod = Admvid = −gmRvid id = gmvid
voc = Acvic = −gmRvic
1 + 2gmRSS
v1 =vic
1 + 2gmRSS
ic =gmvic
1 + 2gmRSS
Then consider only the mismatch terms,
−ic∆R
2− R
∆gm
2v1 =
v′od
2⇒ Acdm =
v′od
vic
∣∣∣∣∣vid=0
= −gm∆R + ∆gmR
1 + 2gmRSS
−id
2∆R
2− R
∆gm
2(1 + 2gmRSS)
vid
2= v ′oc⇒ Adcm =
v′oc
vid
∣∣∣∣vic=0
= −14
(gm∆R +
∆gmR
1 + 2gmRSS
)
Differential Gain Stages 7-28 Analog ICs; Jieh-Tsorng Wu
Current Mirrors and Active Loads
Jieh-Tsorng Wu
November 7, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Sensitivity and Temperature Coefficient
• The sensitivity of a parameter y to a second one x is defined as
Syx ≡
(∆y
y
)(∆xx
) =x
y· ∂y∂x
• The variation of a parameter y that results from changes in temperature is usuallycharacterized by its fractional temperature coefficient, which is defined as thefractional change per degree centigrade change in temperature.
TCy ≡
(∆y
y
)∆T
=1y· ∂y∂T
Voltage and Current References 9-2 Analog ICs; Jieh-Tsorng Wu
Simple Current Sources
VD2RR
VDDVCC
ID2
Q1 Q2 M2M1
IC2
VC2
IC2 ≈ IC1 ≈VCC − VBE1(on)
R≈
VCC
R
SIC2VCC
=VCC
IC2·∂IC2
∂VCC=
VCC
VCC/R· ∂
∂VCC
(VCC
R
)= R ·
(1R
)= 1
∂IC2
∂T=
1R
∂VCC
∂T−VCC
R2
∂R
∂T= IC2
(1VCC
∂VCC
∂T− 1R
∂R
∂T
)⇒ TCIC2
= TCVCC− TCR
Voltage and Current References 9-3 Analog ICs; Jieh-Tsorng Wu
BJT Widlar Current Source
Q1
VCC
Q2
R1
R2
IIN IO
Let βF →∞ and VA→∞,
IIN ≈VCC − VBE1
R1≈
VCC
R1S
IINVCC≈ 1
UT lnIIN
IS1= UT ln
IO
IS2+ IOR2⇒ UT ln
(IIN
IO·IS2
IS1
)= IOR2
If IS1 = IS2 ⇒ UT lnIIN
IO= IOR2
Differentiating both sides of the above equation with respect to VCC,
UT
IO
IIN
(1IO
∂IIN
∂VCC−IIN
I2O
∂IO
∂VCC
)= R2
∂IO
∂VCC⇒
∂IO
∂VCC=
1
1 + IOR2UT
IO
IIN
∂IIN
∂VCC
SIO
VCC=
VCC
IO
∂IO
∂VCC=
1
1 + IOR2UT
VCC
IIN
∂IIN
∂VCC=
1
1 + IOR2UT
S
IINVCC≈ 1
1 + IOR2UT
Voltage and Current References 9-4 Analog ICs; Jieh-Tsorng Wu
MOST Widlar Current Source
R1
R2
IO
VDD
IIN
M1 M2
Let VA→∞ and γ → 0,
IIN =VDD − Vov1 − Vt
R1=
12k′(W
L
)1V 2ov1 Vov1 =
√2IIN
k′(W/L)1
Vov1 = Vov2 + IOR2 ⇒ IOR2 +
√2IO
k′(W/L)2
− Vov1 = 0
√IO =
12R2
(−√
2
k′(W/L)2
+
√2
k′(W/L)2
+ 4R2Vov1
)
1
2√IO
∂IO
∂VDD
=1
4R2
1√2
k′(W/L)2+ 4R2Vov1
4R2
∂Vov1
∂VDD
∂Vov1
∂VDD
=
√2
k′(W/L)1
1
2√IIN
∂IIN
∂VDD
SIO
VDD=
Vov1√V 2ov2 + 4IOR2Vov1
SIINVDD≈
Vov1√4V 2
ov1
SIINVDD
=12S
IINVDD
Voltage and Current References 9-5 Analog ICs; Jieh-Tsorng Wu
BJT Peaking Current Source
Q1
R
VCC
INI
O
Q2
I
Since
VBE1 − IINR = VBE2
UT lnIIN
IS1− IINR = UT ln
IO
IS2
We have
UT ln(IIN
IO·IS2
IS1
)= IINR
If Q1=Q2, then
IO = IINe−IINR/UT R =
UT
IINln
IIN
IO
Voltage and Current References 9-6 Analog ICs; Jieh-Tsorng Wu
MOST Peaking Current Source
M1
R
IIN
OI
VDD
M2
For M1 and M2 in strong inversion
IO =12k′(W
L
)2V 2ov2 =
12k′(W
L
)2
(Vo1 − IINR)2
Vov1 =
√2IIN
k′(W/L)1
For M1 and M2 in weak inversion region,
VGS2 − Vt = nUT ln
(IIN
(W/L)1It
)− IINR
If M1=M2,
IO ≈ It
(W
L
)2e(VGS2−Vt)/(nUT ) ≈ IINe
−IINR/(nUT )
Voltage and Current References 9-7 Analog ICs; Jieh-Tsorng Wu
BJT VBE Referenced Current Source
Q1
Q2
VCC
R1
R2
IINIO
IIN =VCC − VBE1 − VBE2
R1
VBE1 = UT lnIIN
IS1
IO =VBE1
R2=
UT
R2ln
IIN
IS1
∂IO
∂VCC=
UT
R2
(IS1
IIN
)(1IS1
∂IIN
∂VCC−
IIN
I2S1
∂IS1
∂VCC
)=
UT
R2
1IIN
∂IIN
∂VCC
SIO
VCC=(VCC
IO
)∂IO
∂VCC=(VCC
IO
)UT
R2
1IIN
∂IIN
∂VCC=
UT
IOR2S
IINVCC
=UT
VBE1(on)S
IINVCC
Voltage and Current References 9-8 Analog ICs; Jieh-Tsorng Wu
MOST Vt Referenced Current Source
R1
R2
IIN
VDD
OI
M2
M1
IIN =VDD − VGS1 − VGS2
R1=
VDD − Vov1 − Vov2 − Vt1 − Vt2
R1
Vov1 =
√2IIN
k′(W/L)1
Vov2 =
√2IO
k′(W/L)2
IO =VGS1
R2=
Vt1 + Vov1
R2=
Vt1 +√
2IINk′(W/L)1
R2
SIO
VDD=
Vov1
2IOR2S
IINVDD
=Vov1
2VGS1S
IINVDD
Voltage and Current References 9-9 Analog ICs; Jieh-Tsorng Wu
Self-Biasing BJT VBE Reference
VCC
VEE
IO1
IO2
IOIIN
IIN
IO
Q1
R
Q2
Q3
Q5
Q6
A
B
Q4
IIN ≈ IO ·IS3
IS4
IO ≈VBE1
R=
UT
Rln(IIN
IS1
)
TCIO= TCVBE1
− TCR
• Two possible operating states, A and B. State A is stable and desirable.
• State B, where only leakage currents flow, would normally be unstable. However, itmay become stable due to low loop gain under low-current condition.
• There may exist hidden states when the supply is ramping from 0 V.
Voltage and Current References 9-10 Analog ICs; Jieh-Tsorng Wu
Self-Biasing BJT VBE Reference with Start-Up Circuit
VEE
IO2
VCC
4V BE(on)
Rs
IIN
Rx V x
IO
IO1
Q1
R
Q2
Q5
Q3 Q6
D1
D2
D3
D4
D5
Q4 • When in zero-current state (B), Vx ≈ 0,and D5 is forward biased, forcing a currentflowing into the self-basing loop.
• Choose Rx so that, in State A,
Vx = IINRx ≥ 2VBE (on)
Thus, D5 is reversed biased and the start-up circuit won’t disturb the self-biasing loopwhen in State A.
• The start-up circuit may also introduce additional bias points.
Voltage and Current References 9-11 Analog ICs; Jieh-Tsorng Wu
Self-Biasing BJT UT Reference
VCC
VEE
V BE
IO1
IO2
I IN
IO
IOI IN
Q1
Q3
A
B
Q2
R
Q5
Q6Q4
IIN ≈ IO ·IS3
IS4
UT lnIIN
IS1= UT ln
IO
IS2+ IOR
TCIO= TCUT
− TCR
∆VBE = VBE1 − VBE2 = UT ln(IIN
IO·IS2
IS1
)= UT ln
(IS3
IS4·IS2
IS1
)IO =
∆VBE
R
• The UT reference is a proportional-to-absolute-temperature (PTAT) circuit.
• A start-up circuit is required to avoid the “zero-current” state.
Voltage and Current References 9-12 Analog ICs; Jieh-Tsorng Wu
Self-Biasing MOST Vt Referenced Current Source
Start-Up
R
IOIIN
IO1
I
VDD
O2M2
M1
M3M4
M6
M5M11
M13
M12
Vov1 =
√2IIN
k′(W/L)1
Vov2 =
√2IO
k′(W/L)2
IIN
IO=
(W/L)3
(W/L)4
IO =VGS1
R=
Vt1 + Vov1
R=
Vt1 +√
2IINk′(W/L)1
R≈
Vt1
R
Voltage and Current References 9-13 Analog ICs; Jieh-Tsorng Wu
Self-Biasing MOST gm Referenced Current Source
V
V
R
R
O1I
INI
VDD
IIIN
IO1
IO2
OI
VDD
O2I
M1 M5
M3M4
M6
M2
O
M2
M3M4
M6
M5M1
k′ = µnCox
α ≡(W/L)2
(W/L)1
> 1
∆V = I · R
Let M3=M4, then
IIN = IO = I
I =12k′(W
L
)1V 2ov1 =
12k′(W
L
)2
(Vov1 − ∆V )2 ⇒ Vov1 =√α
√α − 1
· ∆V
I =∆V
R=
2(√α − 1)2
α
1
k′(W/L)1R2
gm1 =2IVov1
=∆V
R· 2(√α − 1)√α∆V
=2R
√α − 1√α
Voltage and Current References 9-14 Analog ICs; Jieh-Tsorng Wu
Self-Biasing MOST VBE and UT Referenced Current Source
Q1 V
ReferenceTUReferenceBEV
RR
Q2
V
Q1
VDD
IOIININI OI
VDD
M1
M3M4
M6
M1
M3M4
M6
M2 M2
∆V = VBE1 ∆V = UT ln
(IS2
IS1·(W/L)3
(W/L)4
)
Voltage and Current References 9-15 Analog ICs; Jieh-Tsorng Wu
Band-Gap References
GeneratorPTAT
IC
VBE
K · UT
VO = VBE + KUT
• UT = kT/q = 26 mV at T = 300K. ∂UT/∂T = k/q = 0.087 mV/
C.
• VBE = 600 mV at T = 300K. ∂VBE/∂T ≈ −2 mV/
C.
• Want K = 23 so that ∂Vo/∂T = 0 at 300K and VO ≈ 1.2 V.
Voltage and Current References 9-16 Analog ICs; Jieh-Tsorng Wu
Band-Gap References
For a BJT biased in the forward-active region, we have
VBE = VG0
(1 − T
T0
)+ VBE0
T
T0+mUT ln
(T0
T
)+ UT ln
(JC
JC0
)UT =
kT
q
VG0 Bandgap voltage of Si extrapolated to 0K (≈ 1.206 V)
k Boltzmann’s constantm Constant (≈ 2.3)T0 Reference temperatureJC Collector current density (= IC/AE )JC0 Collector current density at T0
Let
VO = VBE + KUT andJC
JC0=(T
T0
)αWe have
VO = VG0 +T
T0(VBE0 − VG0) + (m − α)UT ln
(T0
T
)+ K · UT
Voltage and Current References 9-17 Analog ICs; Jieh-Tsorng Wu
Band-Gap References
Then∂VO
∂T=
1T0
(VBE0 − VG0) + (m − α)k
q
[ln(T0
T
)− 1]+ K · k
q
Set ∂VO/∂T = 0 at T = T0, we obtain
K =1UT0·[VG0 + (m − α)UT0 − VBE0
]UT0 =
kT0
q
VO = VG0 + UT (m − α)[
1 + ln(T0
T
)]∂VO
∂T=
k
q(m − α) ln
(T0
T
)
• At T = T0,
VO = VG0 + UT0(m − α)∂VO
∂T= 0
• If T0 = 300K and α = 1, then,
K =1.24 − VBE0
0.0258and VO = 1.24 V at T = T0
Voltage and Current References 9-18 Analog ICs; Jieh-Tsorng Wu
Kujik Band-Gap References
Q1 Q2Q2
Q1
R1 R2
R3 R3
R2R1
VCC
VEE VEE
I1I1 I2I2
∆VBE∆VBE
VO
VO
I1
I2=
R2
R1VR2 =
R2
R3∆VBE ∆VBE = UT ln
(I1
I2·IS2
IS1
)= UT ln
(R2
R1·IS2
IS1
)
VO = |VBE1| + VR2 = |VBE1| +R2
R3∆VBE = |VBE1| + UT ×
R2
R3ln(R2
R1·IS2
IS1
)
Voltage and Current References 9-19 Analog ICs; Jieh-Tsorng Wu
Kujik Band-Gap References
• Both IC1 and IC2 are proportional to T .
• In n-well CMOS technologies, use vertical pnp BJTs with with collectors tied to VSS .
• Reference: Kujik, JSSC 6/73, pp. 222–226.
Q1 Q2
R1 R2
R3
VEE
I1 I2
VO
VOS
Let VOS be the opamp’s input offset voltage.
VR3 = |VBE1| − |VBE2| + VOS = ∆VBE + VOS
VR2 =R2
R3VR3 =
R2
R3(∆VBE + VOS)
VO = |VBE1| + VOS + VR2
= |VBE1| +R2
R3∆VBE +
(1 +
R2
R3
)VOS
• The ratio R2/R3 is typically 5 ∼ 10.
Voltage and Current References 9-20 Analog ICs; Jieh-Tsorng Wu
Ahuja Band-gap Reference
Cc
VBE
VDD
VSS
M1 M2 M3 M4 M5 M6
M7 M8 M9 M10 M11
M12
R2
R3
Q6
Q5
Q4
Q1
Q2
Q3
VO
Voltage and Current References 9-21 Analog ICs; Jieh-Tsorng Wu
Ahuja Band-gap Reference
VO = 3|VBE | + 3R2
R3∆VBE +
(1 +
R2
R3
)VOS
• Increase number of VBE to suppress the contribution from VOS.
• Opamp doesn’t need to drive resistive load.
• Cc provides a feedforward path for negative feedback to ensure stability.
• Cascode current sources for better current matching.
• M12 is added for auto start-up to avoid the zero-current state.
• Reference: Ahuja, JSSC 12/84, pp. 892–899.
Voltage and Current References 9-22 Analog ICs; Jieh-Tsorng Wu
Brokaw Band-Gap References
1
VEEVEE
VEE
VEEVEE
Q3 Q4
V o2
R2R1
V o1
VCC VCC
R4
R3
Q1
R12
R11
R4
R3
Q1Q2 Q2
Rx
I1
I1
I2
I2
∆VBE ∆VBE
βF →∞ ⇒I1
I2=
R2
R1I2 =
∆VBE
R3∆VBE = UT ln
(I1
I2·IS2
IS1
)
Voltage and Current References 9-23 Analog ICs; Jieh-Tsorng Wu
Brokaw Band-Gap References
The output voltages are
VO1 = VBE1 + (I1 + I2)R4 = VBE1 +∆VBE
R3
(I1
I2+ 1)R4
= VBE1 + UT ×R4
R3
(R2
R1+ 1)
ln(R2
R1·IS2
IS1
)
VO2 =(
1 +R11
R12
)[VBE1 + UT
R4
R3
(I1
I2+ 1)
ln(I1
I2·IS2
IS1
)]
• Both I1 and I2 are proportional to T .
• The resistor Rx =(R3R4R11
)‖ R12 is added to cancel the effects of the finite base
currents going through R11.
• Reference: Brokaw, JSSC 12/74, pp. 388–393.
Voltage and Current References 9-24 Analog ICs; Jieh-Tsorng Wu
Widlar Band-Gap Reference
VEE
VEE
VCC
Q4
R1R2
R3
Q1Q2Q3
I1I2
I3
∆VBE
Vo
βF →∞I1
IS1=
I3
IS3VBE1 = VBE3
I1
I2=
R2
R1∆VBE = UT ln
I1
I2
IS2
IS1= UT ln
R2
R1
IS2
IS1
VO = VBE1 +R2
R3∆VBE
= VBE1 + UT ×R2
R3ln(R2
R1·IS2
IS1
)
• Both I1 and I2 are proportional to T . I3 can be mirrored from a separate PTAT source.
• In the simplest form, I3 can be implemented with a resistor.
Voltage and Current References 9-25 Analog ICs; Jieh-Tsorng Wu
Song Band-Gap Reference
V R
Q1 Q2
I o
M3M4
M2M1
Q3
M5
M6M6
M8
M9 M10
M11
VDD
VSS
V o
R
R = y Ry
x
Voltage and Current References 9-26 Analog ICs; Jieh-Tsorng Wu
Song Band-Gap Reference
Let Q2=Q3, IS2/IS1 = n, and M3=M4=M5, then
∆V = UT ln(n)
The output voltage, VO, and current, IO, are thus
VO = VBE3 + UT · y ln(n) and IO =VO
Rx
• A PTAT current from M8 develops a UT -dependent voltage across resistor Ry . Aproper choice of the ratio y can give a band-gap voltage at VO.
• All currents are proportional to T .
• If desired, a temperature-independent output current can be realized by choosing y
to give an appropriate TC to VO to cancel the TC of resistor R2.
• Reference: Song, et al., JSSC 12/83, pp. 634–643.
Voltage and Current References 9-27 Analog ICs; Jieh-Tsorng Wu
Band-Gap Reference Output Issues
RG
RG
RG
RG RG
Reference Generator
CL
Reference
VO
Generator
V
Reference Generator
VOV
O
RO
V’O
R
Voltage and Current References 9-28 Analog ICs; Jieh-Tsorng Wu
Band-Gap Reference Output Issues
• Feedback is employed in the reference generator. Loop stability must be ensured.
• The stability can be tested by observing the output step response.
• Capacitive loading at the output of reference generator has to be either extremelylarge (i.e., off-chip capacitors, undesirable because of extra pin, lead inductance, ...)or very small (not easy to accomplish).
• Can use buffers to reduce the output loading. But additional offset and drift areintroduced.
• One possible scheme is using separate generators for different parts of system soas to isolate more sensitive circuits from other ones. However, mismatch amonggenerators, area, power, and trimming cost must be considered.
Voltage and Current References 9-29 Analog ICs; Jieh-Tsorng Wu
Output Stages
Jieh-Tsorng Wu
December 5, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Output Stage Requirements
Vi Output
Stage
Io
LCLR
VoI
Outputo
Stage
Vi
L
o
CR
V
L
• Deliver large output current to low-impedance loads (resistive and/or capacitive).
• Usually is a voltage buffer, i.e., low voltage gain, high Zin, and low Zo.
• High Zin is to maintain voltage gain and bandwidth of previous stage.
• Wide bandwidth if in the feedback loop,
• May need protection against load shorts.
Output Stages 10-2 Analog ICs; Jieh-Tsorng Wu
Output Stage Design Issues
• Frequency response.
• Output impedance.
• Output current.
• Output voltage range.
• Power efficiency.
• Distortion.
Output Stages 10-3 Analog ICs; Jieh-Tsorng Wu
Nonlinearity and Harmonic Distortion
For a nonlinear system with input x, the output y can be expressed as:
y = a0 + a1x + a2x2 + a3x
3 + · · ·
With a pure sinusoidal input x = v cosωt,
y = a0 + a1v cosωt + a2v2 cos2 ωt + a3v
3 sin3 ωt + · · ·
= a0 + a1v cosωt +a2v
2
2(1 + cos 2ωt) +
a3v3
4(3 cosωt + cos 3ωt) + · · ·
= b0 + b1 cosωt + b2 cos 2ωt + b3 cos 3ωt + · · ·
where
b0 = a0 +12a2v
2 + · · · b1 = a1v +34a3v
3 + · · ·
b2 =12a2v
2 + · · · b3 =14a3v
3 + · · ·
Output Stages 10-4 Analog ICs; Jieh-Tsorng Wu
Nonlinearity and Harmonic Distortion
The harmonic distortion factors are
HD2 ≡∣∣∣∣b2
b1
∣∣∣∣ ≈ 12
a2
a1· v
HD3 ≡∣∣∣∣b3
b1
∣∣∣∣ ≈ 14
a3
a1· v2
The total harmonic distortion (THD) is
THD =
√b2
2 + b23 + · · ·
b1
The SINAD is the ratio of signal plus noise plus distortion powers to noise and distortionpowers, i.e,
SINAD =S + N + D
N + D
Output Stages 10-5 Analog ICs; Jieh-Tsorng Wu
Class-A BJT Emitter Follower
Q2
Q1
R3
R2R1
IQ
IoV
Vi
o
LR
VCC
VCC
Vbe1 = UT ln(Ic1
IS1
)Ic1 = IQ +
Vo
RL
⇒ Vi = Vo + Vbe1 = Vo + UT ln
(IQ + Vo/RL
IS1
)
Output Stages 10-6 Analog ICs; Jieh-Tsorng Wu
Class-A BJT Emitter Follower Output Power
Vce1 = VCC − (Ic1 − IQ)RL
For a sinusoidal Vo with amplitudes Vo and Io,
Average Output Power = PL =12VoIo
Average Supply Power = Psupply = 2VCCIQ
Maximum output swing and output power are
Vom = VCC − VCE (sat) = IQ · RL Iom = IQ
PL(max) =12VomIom =
12
[VCC − VCE (sat)
]IQ
Power Conversion Efficiency = ηC =PL
PsupplyηC(max) =
14
(1 −
VCE (sat)
VCC
)≤ 1
4
Output Stages 10-7 Analog ICs; Jieh-Tsorng Wu
Instantaneous Power Dissipation
Q1 Instantaneous Power Dissipation is
Pc1 = Vce1Ic1
At maximum ηC,
Pc1 = VCC(1 + sinωt) × IQ(1 − sinωt)
=VCCIQ
2(1 + cos 2ωt)
• The maximum Pc1 occurs at the midpointof any load line.
Output Stages 10-8 Analog ICs; Jieh-Tsorng Wu
Class-A MOST Source Follower
IQ
IoM1
Vo
Vi
LR
M2
VDD
VDD
Id1 = IQ +Vo
RL
Vi = Vo + Vgs1 = Vo + Vt1 + Vov1
⇒ Vi = Vo + Vt0 + γ
(√2φf + Vo + VDD −
√2φf
)+
√√√√2(IQ + Vo/RL
)k′(W/L)1
Output Stages 10-9 Analog ICs; Jieh-Tsorng Wu
Distortion in the MOST Source Follower
Since Vi = f (Vo), we have
Vi = VI + vi =∞∑n=0
bn(vo)n vo = Vo − VO bn =1n!f (n)(VO) ⇒ vi =
∞∑n=1
bn(vo)n
To find
vo =∞∑n=1
an(vi)n
use
vi =∞∑n=1
bn(vo)n =∞∑n=1
bn
( ∞∑m=1
am(vi)m
)n
= b1a1vi + (b1a2 + b2a21)v2
i+ (b1a3 + 2b2a1a2 + b3a
31)v3
i+ · · ·
Output Stages 10-10 Analog ICs; Jieh-Tsorng Wu
Distortion in the MOST Source Follower
Matching coefficients, we obtain
a1 =1b1
a2 = −b2
b31
a3 =2b2
2
b51
−b3
b41
• Assume RL→∞, and let VM = VO + VDD + 2φf , vi = vi sinωt, then
a1 =1
1 + γ
2V−1/2M
a2 =γ
8V−3/2M(
1 + γ
2V−1/2M
)3a3 = −
γ
16V−5/2M(
1 + γ
2V−1/2M
)5
HD2 =12
a2
a1· vi =
γ
16
V−3/2M(
1 + γ
2V−1/2M
)2· vi
HD3 =14
a3
a1· v2
i= − γ
64
V−5/2M(
1 + γ
2V−1/2M
)4· v2
i
Output Stages 10-11 Analog ICs; Jieh-Tsorng Wu
Class-A BJT Common-Emitter Stage
R1 R2
Q1
Q2
R3
i
IoVo
LRV
IQ
VCC
VCC
Io = IQ − Ic1 ⇒ Vo = IoRL =(IQ − ISe
Vi/UT
)RL
Same output power, ηC, and Pc1 as the class-A emitter followers, since
Vce1 = VCC − (Ic1 − IQ)RL
Output Stages 10-12 Analog ICs; Jieh-Tsorng Wu
Distortion in Class-A BJT Common-Emitter Stage
Assume the input isVi = VBE1 + vi IQ = ISe
VBE1/UT
Then, the output voltage is
Vo = −RL
[ISe
(VBE1+vi )/UT − IQ
]= −RLIQ
(evi/UT − 1
)
= −RLIQ
[vi
UT
+12
(vi
UT
)2
+16
(vi
UT
)3
+ · · ·]= a1vi + a2v
2i+ a3v
3i+ · · ·
Let vi = vi sinωt, then the harmonic distortion factors are
HD2 =12
a2
a1· vi =
14
vi
UT
HD3 =14
a3
a1· v2
i=
124
(vi
UT
)2
Output Stages 10-13 Analog ICs; Jieh-Tsorng Wu
Class-A MOST Common-Source Stage
IQ
M1
M2
V R
Io
i
Vo
L
VDD
VDD
Vo = IoRL = (IQ − Id1)RL
Id1 =12µCox
W
L(Vi − Vt)
2 =12k(Vi − Vt)
2
Let Vi = VI + vi , VI = Vov + Vt and IQ = (1/2)kV 2ov
Vo = RL (IQ − Id ) = RL
[IQ −
12k(Vov + vi)
2]
= −RLIQ
[2(
vi
Vov
)+(
vi
Vov
)2]
Let vi = vi sinωt, then the harmonic distortion factors are
HD2 =12
a2
a1· vi =
14
(vi
Vov
)HD3 = 0
Output Stages 10-14 Analog ICs; Jieh-Tsorng Wu
Class-B Push-Pull Emitter Follower
Q1Io
Q2
Vo
LR
Vi
VCC
VCC
Output Stages 10-15 Analog ICs; Jieh-Tsorng Wu
Output Power of Class-B Push-Pull Emitter Follower
M11 and M12 remain off for only a small range of input voltages.
Output Stages 10-30 Analog ICs; Jieh-Tsorng Wu
Noise Analysis and Modeling
Jieh-Tsorng Wu
December 5, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Noise in Time Domain
n(t)
t
PDF
n
0
0
Mean = n =1T
∫ T0n(t)dt = 0 Noise Power = n2 =
1T
∫ T0n2(t)dt
Root Mean Square = nrms =(n2)1/2
• T is a suitable averaging time interval. Typically, a longer T gives a more accuratemeasurement.
Noise 11-2 Analog ICs; Jieh-Tsorng Wu
Probability Density Function
• The probability that the noise lies between values n and n + dn at any time is givenby P (n)dn. P (n) is the probability density function (PDF).
• The PDF of a random noise is usually Gaussian, i.e.,
P (n) =1√
2πσe− n
2
2σ2
We have ∫ +∞−∞
PDF(n)dn = 1
and
Variance =∫ +∞−∞
n2 · PDF(n)dn = n2 = σ2
Noise 11-3 Analog ICs; Jieh-Tsorng Wu
Noise in Frequency Domain
f
log f
log f
Spectral Density
Root Spectral Density
n
PowerMeterf
BPF
V2
Hz
V√Hz
One-sided power spectral density
SD(f ) = lim∆f→0
n2(f )
∆f
One-sided root spectral density
RD(f ) = (SD)1/2
The total noise power is
∫ ∞0
SDn(f )df = n2
Noise 11-4 Analog ICs; Jieh-Tsorng Wu
Filtered Noise
n i n oH(s) SDno(f ) = SDni
(f ) × |H(j2πf )|2
If SDni(f ) = N is a constant (white noise), then
n2o =∫ ∞0
SDni(f ) · |H(j2πf )|2df = N ·
∫ ∞0|H(j2πf )|2df = N · Bn
• Bn is called the noise bandwidth of the filter.
• For a single-pole filter H(s) = 11+s/ωo
,
Bn =∫ ∞0|H(j2πf )|2df =
∫ ∞0
1
1 +(
ffo
)2df =
π
2· fo
Noise 11-5 Analog ICs; Jieh-Tsorng Wu
Noise Summation
n i1
n i2
n i3
n i1
n i2
n o2
H (s)
H (s)2
H (s)
1
3
n o1
If two noises, ni and nj , are uncorrelated then, i.e., ni · nj = 0. Then
n2o1 = (ni1 + ni2)2 = n2
i1 + n2i2 + 2 · ni1ni2 = n2
i1 + n2i2
SDno2(f ) = |H1(j2πf )|2SDni1
+ |H2(j2πf )|2SDni2+ |H3(j2πf )|2SDni3
Noise 11-6 Analog ICs; Jieh-Tsorng Wu
Piecewise Integration of Noise
N1 N2 N3 N4
101010101010 1010 102 3 4 5 6 7f
200
20
2
2
2
2
(nV)2
Hz ∝ 1f
The noise power in each frequency region is
PN1=∫ 102
100
2002
fd f = 2002 ln(f )|102
100 = 1.84 × 105 (nV)2
PN2=∫ 103
102202df = 202 f |103
102 = 3.6 × 105 (nV)2
Noise 11-7 Analog ICs; Jieh-Tsorng Wu
Piecewise Integration of Noise
PN3=∫ 104
103
(20
103
)2
f 2df =(
20
103
)2 13f 3
∣∣∣∣104
103= 1.33 × 108 (nV)2
PN4=∫ ∞104
2002
1 +(
f
105
)2=∫ ∞0
2002
1 +(
f
105
)2df −
∫ 104
02002df
= 2002(π
2
)105 − 2002 · 104 = 5.88 × 109 (nV)2
Total rms of the noise is
nrms =(PN1
+ PN2+ PN3
+ PN4
)1/2= 77.5 µV rms
• 1/f noise tangent principle: Lower a 1/f line until it touches the spectral densitycurve; the total noise can be approximated by the noise in the vicinity of the 1/f line.
Noise 11-8 Analog ICs; Jieh-Tsorng Wu
Thermal Noise
RRR
v2i2
v2
∆f= 4kTR
i2
∆f= 4kT
1R
f = 0 ∼ ∞
T = Absolute Temperature in Kelvins
k = 1.38 × 10−23 watt/K-Hz (Boltzmann’s Constant)
∆f = Bandwidth per Hertz
• Thermal noise is a white noise, i.e., its power spectral density v2/∆f is independentof frequency, and its amplitude distribution is Gaussian.
• For a 1 kΩ resistor at 300K, v2/∆f ≈ (4 nV/
√Hz)2.
Noise 11-9 Analog ICs; Jieh-Tsorng Wu
Thermal Noise with Loading
RL
RRC
P n
v2 v2
v2o
• The RL load receives the maximum power if RL = R. Thus the available noise powerfor RL is
Pn =1
4R· v2 · Bn = kTBn Bn = Noise Bandwidth
• For the RC low-pass network
Bn =π
2· 12πRC
=1
4RCv2o = 4kTR · 1
4RC=
kT
C
If C = 1 pF and T = 300K, v2
o = (64 µV)2
Noise 11-10 Analog ICs; Jieh-Tsorng Wu
Shot Noise
ID
rd i2
rd =kT
qID
i2
∆f= 2qID f = 0 ∼ ∞
q = 1.6 × 10−19 C (Electronic Charge)
kT/q = UT ≈ 26 mV at T =300K
• Shot noise is also a white noise.
• The shot noise from a diode with 50 µA bias current is the same as the thermal noisefrom a 1 kΩ resistor at room temperature.
Noise 11-11 Analog ICs; Jieh-Tsorng Wu
Flicker Noise ( 1/f Noise)
• Flicker noise, which is always associated with a flow of direct current, displays aspectral density of the form
i2
∆f= K1
Ia
f bf = 0 ∼ ∞
a ≈ 0.5 ∼ 2 b ≈ 1 K1 = a constant for a particular device
• The flicker noise’s power spectral density is frequency dependent, and its amplitudedistribution is non-Gaussian.
• Flicker noise is caused mainly by traps associated with contamination and crystaldefects. The constant K1 can varies widely even for devices from the same wafer.
Noise 11-12 Analog ICs; Jieh-Tsorng Wu
BJT Noise Model
v1
v2b
i2b i2
crπ Cπ gmv1
Cµrb
ro
rc
Ccs
B B′
E
C
v2b
∆f= 4kT rb
i2c
∆f= 2qIC
i2b
∆f= 2qIB + K1
IaB
f
• All noise sources are independent of each other.
• The thermal noise of rc is neglected.
• Avalanche noise is found to be negligible if VCE is kept at least 5 V below BVCEO.
• Cµ can be neglected in noise calculation.
Noise 11-13 Analog ICs; Jieh-Tsorng Wu
FET Noise Model
v1gmv1
i2g i2
dCgs
Cgd
ro
G
S
D
i2g
∆f= 2qIG +
1615
kTω2C2gs
i2d
∆f= 4kT (γgd0) + K1
IaD
f
• Since the channel material is resistive, it exhibits thermal noise. γ is a constant, gd0is the channel conductance at VDS = 0.
γ ≈ 23
gd0 ≈ gm
Noise 11-14 Analog ICs; Jieh-Tsorng Wu
FET Noise Model
• For short-channel device (L < 1 µm), the thermal noise is 2 to 5 times larger than4kT (2/3)gm.
• The gate-current noise, (16/15)kTω2C
2gs, is usually insignificant at low frequencies.
Its correlation with the thermal noise is 0.39.
• IG is the gate leakage current.
• Cgd can be neglected in noise calculation.
• The 1/f noise in the surface devices, such as MESFETs and MOSFETs, is usuallylarger than that of BJTs.
• pMOSTs have less 1/f noise than nMOSTs, since holes are less likely to be trapped.
Noise 11-15 Analog ICs; Jieh-Tsorng Wu
Equivalent Input Noise Generators
Noisy
Network Network
Noiseless
RS RS
v2i
i2i
• The noise in network is lumped and represented by a noise voltage generator v2i
and
a noise current generator i2i. This representation is valid for any source impedance, if
correlation between the noise generators is considered.
• And the total input equivalent noise can be found by
viN = vs + vi + iiRS and v2iN
= v2s + v2
i+ i2
iR2S
Noise 11-16 Analog ICs; Jieh-Tsorng Wu
Equivalent Input Noise Generators
• In most practical circuits, the correlation between vi and ii is small and may be
neglected. If either v2i
or i2i
dominates, the correlation may be neglected in any case.
• The value of v2i
can be found by shorting the input ports and equating the output noisein each case.
• The value of i2i
can be found by opening the input ports and equating the output noisein each case.
Noise 11-17 Analog ICs; Jieh-Tsorng Wu
Noise Factor and Input Noise Generators
Network
Noiseless
RS
v2s
v2i
i2i
v2s is the thermal noise of RS, i.e.,
v2s = 4kTRS∆f
Assume no correlation between v2i
and i2i, we have
Na
Ni
=v2i+ i2
iR
2S
v2s
Noise 11-18 Analog ICs; Jieh-Tsorng Wu
Noise Factor and Input Noise Generators
Thus, the noise factor for the two-port network is
F =SNRin
SNRout=
Si/Ni
(G · Si)/[G · (Ni + Na)]= 1 +
Na
Ni
= 1 +v2i
4kTRS∆f+
i2iRS
4kT∆f
• For small RS, v2i
dominates, whereas for large RS, i2i
dominates.
• There exits an optimal RS for minimum F :
R2S,opt
=v2i
i2i
and Fopt = 1 +i2iRS
2kT∆f
This is one reason for the widespread use of transformers at the input of low-noisetuned amplifiers.
Noise 11-19 Analog ICs; Jieh-Tsorng Wu
Noise Generators of a BJT Common-Emitter Stage
v1
v1
gmv1
gmv1
rb
rb
rπ
rπ
Cπ
Cπ
io
io
v2b
i2b i2
c
v2i
i2i
v2b
∆f= 4kT rb
i2b
∆f= 2qIB + K1
IaB
f
i2c
∆f= 2qIC
Noise 11-20 Analog ICs; Jieh-Tsorng Wu
Noise Voltage Generator of a BJT Common-Emitter Stage
By shorting the input ports, we obtain
io = gmvb + ic = gmvi
Since rb is small, i2b
is neglected. We have
vi = vb +ic
gm
v2i= v2
b+
i2c
g2m
v2i
∆f= 4kT rb +
2qIC
g2m
= 4kT
(rb +
IC/UT
2g2m
)= 4kT
(rb +
12gm
)= 4kTReq
Req = Equivalent Input Noise Resistance = rb +1
2gm
Noise 11-21 Analog ICs; Jieh-Tsorng Wu
Noise Current Generator of a BJT Common-Emitter Stage
By opening the input ports, we obtain
io = β(jω)ib + ic = β(jω)ii ⇒ ii = ib +ic
β(jω)i2i= i2
b+
i2c
|β(jω)|2
Thus
i2i
∆f= 2q
[IB + K ′1
IaB
f+
IC
|β(jω)|2
]= 2qIeq K ′1 =
K1
2q
Ieq = Equivalent Input Shot Noise Current = IB + K ′1IaB
f+
IC
|β(jω)|2
β(jω) =βo
1 + j ωωβ
=βo
1 + j ffTβo
=βo
1 + βo
Cπ+Cµ
gmjω
Noise 11-22 Analog ICs; Jieh-Tsorng Wu
BJT Equivalent Input Shot Noise Spectral Density
f a
f 2
log ff b
1/flog
(i2i
∆f
)
At high frequencies
IC
|β(jω)|2=
IC
β2o
(1 +
f2
f 2T
β2o
)≈ IC
f2
f 2T
Let IB = ICf
2b
f 2T
⇒ fb = fT
√IB
IC=
fT√βF
Noise 11-23 Analog ICs; Jieh-Tsorng Wu
Total Equivalent Noise Voltage of a BJT Common-Emitter Stage
The total equivalent noise voltage with a source resistance RS can be found as
v2iN
∆f=
v2s
∆f+
v2i
∆f+
i2i
∆fR2S
= 4kT(RS + rb +
12gm
)+ R2
S· 2q(IB + K ′1
IaB
f+
IC
|β(jω)|2
)
= 4kT
[(RS + rb +
12gm
)+
R2S
2UT
(IB + K ′1
IaB
f+
IC
|β(jω)|2
)]
= 2qR2S
[2UT
R2S
(RS + rb +
12gm
)+
(IB + K ′1
IaB
f+
IC
|β(jω)|2
)]
Noise 11-24 Analog ICs; Jieh-Tsorng Wu
Noise Generators of a FET Common-Source Stage
v1
v1
gmv1
gmv1
i2g i2
dCgs
Cgs
ro
ro
v2i
i2i
io
io
i2g
∆f= 2qIG +
1615
kTω2C2gs
i2d
∆f= 4kT (γgd0) + K1
IaD
f
Noise 11-25 Analog ICs; Jieh-Tsorng Wu
Noise Voltage Generator of a FET Common-Source Stage
By shorting the input ports, we obtain
io = id = gmvi ⇒ v2i=
i2d
g2m
v2i
∆f= 4kTγ
gd0
g2m
+ K1
IaD
g2mf
= 4kTReq K ′1 =K1
4kT
Req = Equivalent Input Noise Resistance = γgd0
g2m
+ K ′1IaD
g2mf≈ 2
31gm
+ K ′1IaD
g2mf
• For MOST, its voltage generator for flicker noise is approximately independent of biascurrent and voltage and is inversely proportional to the gate-oxide capacitance, i.e.,
v2i
∆f≈ 4kT
(23
1gm
)+
Kf
WLCox
· 1f
Kf ∼ 3 × 10−24 V2-F
Noise 11-26 Analog ICs; Jieh-Tsorng Wu
MOST Equivalent Input Noise Voltage Spectral Density
f a
1/f
log f
log
(v2i
∆f
)
• At frequencies above the flicker noise region, the Req of a FET is significantly higherthan that of a BJT at a comparable bias current.
• For a MOST, it is not uncommon for the fa to extend well into the MHz region.
Noise 11-27 Analog ICs; Jieh-Tsorng Wu
Noise Current Generator of a FET Common-Source Stage
By opening the input ports, we obtain
io = iggm
jωCgs
+ id = iigm
jωCgs
⇒ ii = ig +jωCgs
gm
id i2i= i2
g +ω
2C
2gs
g2m
i2d
i2i
∆f= 2qIG +
1615
kTω2C2gs +
ω2C
2gs
g2m
(4kTγgd0 + K1
IaD
f
)= 2qIG +ω2C2
gs(4kTReq)
Req = γgd0
g2m
+K1
4kTg2m
·IaD
f+
415≈ 2
31gm
+K′1
g2m
·IaD
f+
415
• When the source impedance is large, i2i
dominates. Since Ig is very small, FETshave noise performance much superior to that of BJTs. However, for low source
impedances where v2i
dominates, BJTs often have noise performance superior tothat of FETs.
Noise 11-28 Analog ICs; Jieh-Tsorng Wu
Noise Factor of a BJT Common-Emitter Stage
Neglecting flicker noise,
v2i
∆f= 4kT
(rb +
12gm
)i2i
∆f= 2q
(IB +
IC
|β(jω)|2
)= 2q
(IC
βF
+IC
|β(jω)|2
)
The noise factor is
F = 1 +v2i
4kTRS∆f+
i2i
4kT 1RS∆f
= 1 +1RS
(rb +
12gm
)+ RS
(gm
2βF
+gm
2|β(jω)|2
)
= 1 +1RS
(rb +
12gm
)+ RS
[gm
2βF
+gm
2β2o
(1 + β2
o
(ω
ωT
)2)]
Noise 11-29 Analog ICs; Jieh-Tsorng Wu
Noise Factor of a BJT Common-Emitter Stage
For high-frequency circuits, if ω/ωT 1/βo and ω/ωT 1/βF ,
F ≈ 1 +1RS
·(rb +
12gm
)+ RS ·
gm
2·(ω
ωT
)2
• For fixed RS and ωT ,
gm,opt =1RS
·ωT
ωFopt = 1 +
rb
Rs
+ω
ωT
• For fixed gm and ωT ,
RS,opt =
√2rbgm
+1
g2m
·ωT
ωFopt = 1 +
√2rbgm + 1 · ω
ωT
Noise 11-30 Analog ICs; Jieh-Tsorng Wu
Noise Factor of a BJT Common-Emitter Stage
For low-frequency circuits, if ω/ωT 1/βo and ω/ωT 1/βF ,
F ≈ 1 +1RS
·(rb +
12gm
)+ RS ·
gm
2·(
1βF
+1
β2o
)
≈ 1 +1RS
·(rb +
12gm
)+ RS ·
gm
2· 1βF
• For fixed RS and βF ,
gm,opt =1RS
·√βF Fopt = 1 +
rb
Rs
+1√βF
• For fixed gm and βF ,
RS,opt =
√2rbgm
+1
g2m
·√βF Fopt = 1 +
√2rbgm + 1 · 1√
βF
Noise 11-31 Analog ICs; Jieh-Tsorng Wu
Noise Factor of an FET Common-Source Stage
Neglecting flicker noise, IG, and gate-current noise,
v2i
∆f= 4kTγgd0 ·
1
g2m
i2i
∆f= ω2C2
gs · 4kTγgd0 ·1
g2m
The noise factor is
F = 1 +v2i
4kTRS∆f+
i2i
4kT 1RS∆f
= 1 +1RS
·γgd0
g2m
+ RS ·ω2C2gs ·
γgd0
g2m
Noise 11-32 Analog ICs; Jieh-Tsorng Wu
Noise Factor of an FET Common-Source Stage
For low-frequency circuits, ωCgs 1/RS ,
F ≈ 1 +1RS
·γgd0
g2m
• For fixed RS, gm,opt →∞ and Fopt → 1
• For fixed gm, RS,opt →∞ and Fopt → 1
• For RS of the order of MΩ or higher, the FET usually has significantly lower noisefigure than a BJT.
For high-frequency circuits, ωCgs 1/RS,
F ≈ 1 + RS ·ω2C2gs ·
γgd0
g2m
≈ 1 + RS · γgd0 ·(ω
ωT
)2
Noise 11-33 Analog ICs; Jieh-Tsorng Wu
Noise Performance of Other Configurations
Common−Base Stage
Emitter Follower
zLzL
v2i
v2i
v2i
v2i
i2i
i2i
i2i
i2i
Noise 11-34 Analog ICs; Jieh-Tsorng Wu
Noise Performance of Other Configurations
• The equivalent input noise generators of a common-base stage or emitter followerare the same as those of a common-emitter stage.
• For the common-base configuration, since its current gain ≈ 1, any noise current atthe output is referred directly back to the input without reduction.
• For the emitter follower, since its voltage gain ≈ 1, any noise voltage at the output,including noise due to zL, is transformed unchanged to the input.
• In most low-noise designs, common-emitter connection is used for the input stage.
Noise 11-35 Analog ICs; Jieh-Tsorng Wu
Emitter-Coupled Pair Noise Performance
Q1 Q2
VCC
VEE
Q1 Q2
VCC
VEE
RL RL RL RL
vo vo
IEE IEEREE REE
v2i1 v2
i1v2i2 v2
i2
i2i1
i2i1i2
i2
i2i2
• If the circuit is balanced, the current-source noise represents a common-mode signaland will produce no differential output.
Noise 11-36 Analog ICs; Jieh-Tsorng Wu
Effect of Ideal Feedback on Noise Performance
v1v1 vovo aa
f × vof × vo
v2i
v2i
i2i
i2i
• For ideal feedback systems, the equivalent input noise generators can be movedunchanged outside the feedback loop and the feedback has no effect on the circuitnoise performance.
Noise 11-37 Analog ICs; Jieh-Tsorng Wu
Effect of Input Series Feedback Feedback on Noise Performance
v1v1 vovo aa
v2ia
i2ia
RFRFv2f
RERE
v2e
v2i
i2i
v2f= 4kTRF∆f v2
e = 4kTRE∆f R = RF ‖RE
vi = via + iiaR +RF ve
RF + RE
+REvf
RF + RE
ii ≈ iia
⇒ v2i= v2
ia+ i2
iaR2 + 4kTR∆f i2
i≈ i2
ia
Noise 11-38 Analog ICs; Jieh-Tsorng Wu
Effect of Input Shunt Feedback Feedback on Noise Performance
v1v1 vovo aa
v2ia
i2ia
RFRF
i2f
v2i
i2i
i2f= 4kT
1RF
∆f
vi ≈ via ii = iia +via
RF
+ if
⇒ v2i≈ v2
iai2i= i2
ia+
v2ia
R2F
+ 4kT1RF
∆f
Noise 11-39 Analog ICs; Jieh-Tsorng Wu
Effect of Feedback on Noise Performance
To analyze the noise performance of a practical feedback system, first use the loadingapproximation according to its feedback configuration to find the loading for the inputport due to the feedback network.
For series feedback at the input
v2i= v2
ia+ i2
ia|Zfb|2 + 4kTRfb∆f i2
i≈ i2
ia
For shunt feedback at the input
v2i≈ v2
iai2i= i2
ia+
v2ia
|Zfb|2+ 4kT
1Rfb
∆f
where Zfb is the loading of the feedback network for the input port, and Rfb representsthe resistive part (thermal noise) of the loading.
Noise 11-40 Analog ICs; Jieh-Tsorng Wu
Effect of Cµ on Noise Performance
v1
v2b
i2b i2
crπ Cπ gmv1
Cµrb
ro
rc
Ccs
B B′
E
C
• Note that the collector-base capacitor Cµ represents single-stage shunt feedback, andthus does not significantly affect the equivalent input noise generators of a transistor,even if Miller effect is dominant. The capacitor itself contributes no noise. Also, in
calculating i2i, the term v2
ia/|Zfb|
2 can be neglected, since |Zfb| = 1/|ωCµ| is quitelarge at frequencies of interest.
Noise 11-41 Analog ICs; Jieh-Tsorng Wu
Single-Stage Amplifier with Local Feedback
V o
iV
RFRFRF RF
i2f
i2f
RERERERE
v2e
v2i1
i2i1
v2i2
i2i2
v2i
i2i
v2i1
∆f≈ 4kT
(rb +
12gm
)v2i2
∆f≈ 4kT
(rb +
12gm
+ RE
)v2i
∆f≈ 4kT
(rb +
12gm
+ RE
)
i2i1
∆f≈ 2qIB
i2i2
∆f≈ 2qIB
i2i
∆f≈ 2qIB +
4kTRF
Noise 11-42 Analog ICs; Jieh-Tsorng Wu
Operational Amplifier Noise Model
v2ia
i2ia+
i2ia−
• With FET input stage, the current noises can often be ignored at low frequenciessince their values are small.
Noise 11-43 Analog ICs; Jieh-Tsorng Wu
A Low-Pass Filter Example
Rf
V o
R2
Cf
R1
Rf
R2
V i
Cf
R1V o
v2ia i2
ia+
i2ia−
i21
v22
i2f
v2o1 =
(i2a− + i2
1 + i2f
)∣∣∣∣ Rf
1 + j2πfRfCf
∣∣∣∣2
v2o2 =
(v2ia+ i2
a+R22 + v2
2
)∣∣∣∣∣1 +Rf/R1
1 + j2πfRfCf
∣∣∣∣∣2
v2oT
= v2o1 + v2
o2
Noise 11-44 Analog ICs; Jieh-Tsorng Wu
A Current Amplifier Example
20 k
Q2
Q1
5.5 k 5k || 500
20 kQ1
5 k
Q2
500is
io
io
i2f
v2ia
i2ia
Noise 11-45 Analog ICs; Jieh-Tsorng Wu
A Current Amplifier Example
• Neglect flicker noise and assume
IC1 = 0.5 mA IC2 = 1 mA rb1 = rb2 = 100 Ω β1 = β2 = 100
fT1 = 300 MHz fT2 = 500 MHz
• For both first and second stages, the driving signals are high-impedance currentsources, thus we need to consider only equivalent noise current generators.
• The equivalent noise current from the 2nd stage is approximately
2qIB2 + 4kT1
20 kΩ= 2q(10 µA + 2.6 µA)
which can be neglected when compared to 2qIC1 = 2q × 500 µA.
Noise 11-46 Analog ICs; Jieh-Tsorng Wu
A Current Amplifier Example
• The equivalent input noise current for the amplifier is
i2i
∆f=
i2ia
∆f+
v2ia
(5.5 kΩ)2∆f+
4kT5.5 kΩ
= 2q(IB +
IC
|β1|2
)+
4kT
(5.5 kΩ)2
(rb1 +
12gm1
)+
4kT5.5 kΩ
= 2q(
5 µA +500 µA
|β1|2
)+ 2q × 0.2 µA + 2q × 9.1 µA
= 2q(
14.3 +500
|β1|2
)× 10−6 A2/Hz
• We know that
β(j f ) =βo
1 + jβof
fT1
⇒ 1
|β1(j f )|2=
1
β2o1
(1 +
β2o1f
2
f 2T1
)
Noise 11-47 Analog ICs; Jieh-Tsorng Wu
A Current Amplifier Example
• The current gain of the amplifier is AI ≈ 11 and is constant up to B = 100 MHz =fT1/3. The total output noise is
i2oT
=∫ B0A2I
i2i
∆fd f = A2
I×∫ B0
2q(
14.3 +500
|β1|2
)× 10−6df
= A2I× 2q × 10−6
[14.3f +
500
β2o1
f +500
f 2T1
f3
3
]B0
= A2I× 2q × 10−6 × (14.3B + 18.6B) = A2
I× 1.05 × 10−15 A2
• The equivalent input noise current is
i2iT
=i2oT
A2I
⇒ iiT = 32.4 nA rms
Noise 11-48 Analog ICs; Jieh-Tsorng Wu
Feedback and Frequency Compensation
Jieh-Tsorng Wu
December 5, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Feedback
a
f
Si So
Se
Sfb
So = a · Se Sfb = f · So Se = Si − Sfb
Closed-Loop Gain = A ≡So
Si=
a
1 + af=
a
1 + T≈ 1
fif T 1
Gain Sensitivity =δA
A=
11 + T
· δaa
Loop Gain = T ≡ a × f
Feedback 12-2 Analog ICs; Jieh-Tsorng Wu
Effect of Negative Feedback on Distortion
If a is a nonlinear amplifier
So = a1Se + a2S2e + a3S
3e + · · · T = a1f
• For constant input level, the harmonic distortions are
HD2 =1
(1 + T )2· HD2|T=0 HD3 =
1 − 2a22f
a3(1+T )
(1 + T )3· HD3|T=0
• For constant output level, the harmonic distortions are
• Define αt ≡ ωt/ω2 and αp ≡ f (ωu/ω2). Note that αt ≈ αp for PM > 65.
• Design with PM > 65 for no peaking in frequency response.
• Design with PM > 80 for no overshoot in step response.
Feedback 12-28 Analog ICs; Jieh-Tsorng Wu
Dominant-Pole Compensation
gm1 m2g
1p’
Cc > 0
V ip 2
R1 C1 Cc
f
2 C1p
V o
R 2
s-plane
f = 0
σ
jω
The original poles of a(s) are
p1 =−1R1C1
p2 =−1R2C2
ωu = |Av(0)| · |p1| = gm1R1gm2R2 · |p1| =gm1
C1· gm2R2
By adding compensation capacitor Cc
p′1 =−1
R1(C1 + Cc)ω′u =
gm1
(C1 + Cc)· gm2R2
Feedback 12-29 Analog ICs; Jieh-Tsorng Wu
Dominant-Pole Compensation
• The −3 dB bandwidth of the closed loop gain is approximately
f ·ω′u = αp · |p′2| ω−3dB ≈ ωt = αt · |p′2|
where αt and αp are determined by the required phase margin.
• Cc usually is quite large (typically > 1000 pF) and cannot be realized on a monolithicchip.
• For a general-purpose opamp where 0 < f ≤ 1, if the opamp is compensated forf = 1, it it guaranteed to be stable for all f , although it will be slower than necessary.
• To ensure p2 and p3 are in the LHP, want gm3 > gm2.
• If |p1| |p2| |p3|,
p1 ∝1Cc2
p2 ∝1Cc1
p3 ≈ −gm3 − gm2
C2 + C3
The two-pole model can be used by making |p3| ωt.
• If Cc1 is not large enough, p2 and p3 are either complex conjugates or real but closelyspaced. Higher unity-gain bandwidth may be achievable when p2 and p3 are not realand widely separated.
Feedback 12-43 Analog ICs; Jieh-Tsorng Wu
Zeros in the Nested-Miller Compensation
The numerator of a(s) is
N(s) = gm1R1gm2R2gm3
[1 − s
(Cc1
gm3+
Cc2
gm2R2gm3
)− s2Cc2(C2 + Cc1)
gm2gm3
]
Assuming Cc1 C2 and Cc1 Cc2/(gm2R2), then
N(s) ≈ gm1R1gm2R2gm3
[1 − s
Cc1
gm3− s2 Cc2Cc1
gm2gm3
]
z1 = −gm2
2Cc2
1 +
√1 +
4gm3Cc2
gm2Cc1
z2 = −
gm2
2Cc2
1 −
√1 +
4gm3Cc2
gm2Cc1
• z1 is a LHP zero and z2 is a RHP zero. |z1| > |z2|
• |z1| and/or |z2| can be comparable to |p2|, thus degrading phase margin.
Feedback 12-44 Analog ICs; Jieh-Tsorng Wu
Nested-Miller Compensation with Feedforward Transconductors
mf2
Fbk
g
gm1v1
gm3
g
2vgm2
v3
mf1
C2R2
Cc1
1
c2C
3C
V oV i
C3R1R
a(s) = −R3(n0 + n1s + n2s
2)
1 + b′1s + b′2s2 + b′3s
3
Feedback 12-45 Analog ICs; Jieh-Tsorng Wu
Nested-Miller Compensation with Feedforward Transconductors
• If gmf1 = gm1 and gmf2 = gm2, then n0, n1, and n2 are all negative, and both zeros arein the LHP.
• With gmf1 = gm1 and gmf2 = gm2, b1 ≈ a1 and the dominant pole p1 is not changedby gmf . However, p2 and p3 will be different from the case without gmf1 and gmf2.
Feedback 12-46 Analog ICs; Jieh-Tsorng Wu
Basic Two-Stage Operational Amplifier Design
Jieh-Tsorng Wu
December 23, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
• The range is limited to the voltage levels where any transistor goes out of saturation.
Output Voltage Range
Vo(max) = VDD − VDSAT6 Vo(min) = VSS + VDSAT7
• Output resistive load can also limit the voltage range, if the available output current isinsufficient.
Maximum Output Current
Io(sink,max) = ID7 Io(source,max) =12k′p
(W
L
)6
[Vgs6(max) − Vt6]2 − ID7
Vgs6(max) = VDD − Vi+ + Vt2
Opamp-I 13-15 Analog ICs; Jieh-Tsorng Wu
Slew Rate
B1V
Vi cI
oV
x
SR
C oVi
ISS
I
VDD
VSS
C2
int
SR ext
Log (C )
i
V o
V o
V i
SR
V
2
M1 M2
M3 M4
M6
M7
Log (SR)Exponential
t
t
Opamp-I 13-16 Analog ICs; Jieh-Tsorng Wu
Slew Rate
The internal slew rate is generally limited by current available to charge and dischargeCc from input stage. Therefore,
SRint =dVo
dt
∣∣∣∣max
=Ix(max)
Cc
=ISS
Cc
=ISS
gm1×gm1
Cc
=ISS
gm1×ωu
= (VGS1 − Vt1) ×ωu
= Vov1 ×ωu
The external slew rate is limited by the available current to charge and discharge C2.Thus,
SRext =ID7 − Ix(max)
C2=
ID7 − ISS
C2
Opamp-I 13-17 Analog ICs; Jieh-Tsorng Wu
Settling Time
The frequency response and step response of a single-pole amplifier is
A(s) =Ao
1 + s/ωp
Vo(t) = Ao
(1 − e−ωpt
)
The settling time can be written as
ts(ε) =1ωp
ln1ε=
Ao
ωu
ln1ε
• ωu = Ao ·ωp is the dominant-pole unity-gain frequency.
• ε = 1 − |Vo(ts)/Ao| is the error when settling occurs.
The 10% to 90% rise time is
tr =1ωp
ln(9) =2.2ωp
=0.35fp
ωp = 2πfp
Opamp-I 13-18 Analog ICs; Jieh-Tsorng Wu
Input Impedance
C
C
Vi
C
V
oV
iVVB1
C
in-
o
C
VoVi c
in+
d
C
VDD
VSS
Cgd2
Ct
cC
M1 M2
M3 M4
M5
M6
M7M6
R1
R2
M2g m2
Opamp-I 13-19 Analog ICs; Jieh-Tsorng Wu
Input Impedance
Shorting the noninverting input to ground,
Cin− = Cd + C− ≈Cgs1
2
Shorting the inverting input to ground,
Cin+ = Cd + C+ ≈Cgs1
2+ Cgd2 · (1 + Ao1) Ao1 = gm2R1
And we have
Cd ≈Cgs2
2C− ≈ 0 C+ ≈ Cgd2 · (1 + Ao1)
Opamp-I 13-20 Analog ICs; Jieh-Tsorng Wu
Input Impedance
The equivalent voltage gain of the M2 stage decreases with increasing frequency, duethe the effect of Ct. The capacitance C+ is then modified as
C+ ≈ Cgd2 · Ao1 ·1 +
Cgd2gm2
s
1 + Ao1Cgd2+Ct
gm2s
whereCt = Cgs6 + Cc · (1 + Ao2) = Cgs6 + Cc · (1 + gm6R2)
• For gm2/[Ao1(Cgd2 + Ct)] < ω < gm2/Cgd2, C+ become resistive, and
C+ → R+ ≈1
gm2·(
1 +Ct
Cgd2
)
Opamp-I 13-21 Analog ICs; Jieh-Tsorng Wu
Output Impedance
m6Z o
1/g
Log |Zo|
Log fwith unity-gain feedback
gm6v1R1 C1 R2
R2
v1
Cc
|p1| |p2||z1| ωu
Assuming gm6 R1 and R2, we have
Zo = R2 ·1 + sR1(Cc + C1)
1 + sgm6R1R2Cc + s2R1C1R2Cc
p1 ≈ −1
gm6R1R2Cc
= −gm1
Cc
· 1
|Av(0)|p2 ≈ −
gm6
C1z1 ≈ −
1R1(Cc + C1)
Opamp-I 13-22 Analog ICs; Jieh-Tsorng Wu
Output Impedance
• For frequencies larger than z1, Cc acts as a short, the Zo is a resistive 1/gm6.
• The closed-loop Zo of the unity-gain buffer is
Zoc ≈Zo
Av
≈R2
Av(0)· (1 − s/z1) for ω < ωu
where ωu = gm1/Cc.
Opamp-I 13-23 Analog ICs; Jieh-Tsorng Wu
Systematic Input O ffset Voltage
V
Vi
V
c
I
YV1
OS
VB1
SS
iVVo
C
VDD
VSS
M1 M2
M3 M4
M6
M7M5
ID =12kV 2
ov (1 + λVDS)
λ1 = λ2 λ3 = λ4
∆I1−2 = ID1 − ID2 =ISS
2λ1(VY − V1)
∆I3−4 = |ID3| − |ID4| =ISS
2λ3(V1 − VY )
The systematic input referred dc offset can be expressed as
−VOS,s =1
gm1· (∆I1−2 − ∆I3−4) =
Vov,1−2
2· (λ1 + λ3)(VY − V1)
Opamp-I 13-24 Analog ICs; Jieh-Tsorng Wu
Systematic Input O ffset Voltage
• The systematic offset is caused by asymmetry in the dc biasing of VY and V1.
• To minimize VOS,s, want VDS3 = VDS4 = VGS6, then
(W/L)3
(W/L)6
=(W/L)4
(W/L)6
=(W/L)5
2(W/L)7
• Further, to minimize process induced variations choose
L3 = L4 = L6
However, this constraint may conflict with frequency response and noise constraints.
Opamp-I 13-25 Analog ICs; Jieh-Tsorng Wu
Random Input O ffset Voltage
∆Vi−j = |Vi | − |Vj | Vi−j =|Vi | + |Vj |
2∆Ii−j = |Ii | − |Ij | Ii−j =
|Ii | + |Ij |2
∆
(W
L
)i−j
=(W
L
)i
−(W
L
)j
(W
L
)i−j
=12
[(W
L
)i
+(W
L
)j
]
⇒∆ID,3−4
ID,3−4=
∆(W/L)3−4
(W/L)3−4
− 2∆Vt,3−4
Vov,3−4=
∆ID,1−2
ID,1−2
−VOS,r = ∆Vt,1−2 +Vov,1−2
2
[∆ID,1−2
ID,1−2−∆(W/L)1−2
(W/L)1−2
]
= ∆Vt,1−2 −Vov,1−2
Vov,3−4· ∆Vt,3−4 +
Vov,1−2
2
[−∆(W/L)1−2
(W/L)1−2
+∆(W/L)3−4
(W/L)3−4
]
= ∆Vt,1−2 −gm3
gm1· ∆Vt,3−4 +
Vov,1−2
2
[−∆(W/L)1−2
(W/L)1−2
+∆(W/L)3−4
(W/L)3−4
]
Opamp-I 13-26 Analog ICs; Jieh-Tsorng Wu
Input O ffset Voltage and Common-Mode Rejection Ratio
The output voltage change due to common-mode input variation is
∆Vo = Acm · ∆Vic
Want to change differential input so that ∆Vo = 0, then
∆Vid = −∆Vo
Adm
= −Acm
Adm
· ∆Vic
Therefore, we have
CMRR ≡∣∣∣∣Adm
Acm
∣∣∣∣ =∣∣∣∣∣∣(
∂Vid
∂Vic
∣∣∣∣∆Vo=0
)−1∣∣∣∣∣∣ =∣∣∣∣∣(∂VOS
∂Vic
)−1∣∣∣∣∣
Opamp-I 13-27 Analog ICs; Jieh-Tsorng Wu
CMRR Due to Systematic and Random O ffset
SinceVOS = VOS,s + VOS,r
We have
1CMRR
=
∣∣∣∣∂VOS,s∂Vic+∂VOS,r
∂Vic
∣∣∣∣∂VOS,s
∂Vic=
∂VOS,s
∂Vov1·∂Vov1
∂Id1·∂Id1
∂Vic= −1
2(λ1 + λ3)(VY − V1) · 1
gm1·
gm1
1 + 2(gm1 + gmb1)ro5
= −12
(λ1 + λ3)(VY − V1) · 11 + 2(gm1 + gmb1)ro5
≈ −(λ1 + λ3)(VY − V1)
4(gm1 + gmb1)ro5
∂VOS,r
∂Vic=
∂VOS,r
∂Vov1·∂Vov1
∂Id1·∂Id1
∂Vic= −1
2
[−∆(W/L)1−2
(W/L)1−2
+∆(W/L)3−4
(W/L)3−4
]· 11 + 2(gm1 + gmb1)ro5
= −[−∆(W/L)1−2
(W/L)1−2
+∆(W/L)3−4
(W/L)3−4
]· 14(gm1 + gmb1)ro5
Opamp-I 13-28 Analog ICs; Jieh-Tsorng Wu
Mismatches and Input Stage Transconductance
Define
∆gm,i−j = gm,i − gm,j gm,i−j =gm,i + gm,j
2∆ro,i−j = ro,i − ro,j ro,i−j =
ro,i + ro,j
2
Then
Gmd ≈ gm,1−2 ·1 −(∆gm,1−22gm,1−2
)2
1 +(∆gm,3−42gm,3−4
) Gmc ≈ −gm,1−2
1 + 2gm,1−2ro5· (εd + εm)
where
εd ≈1
gm3ro1−∆gm,1−2
gm,1−2
(1 +
2ro5
ro1
)−
2ro5
ro1·∆ro,1−2
ro,1−2
εm =1
1 + gm3ro3+
(gm3 − gm4)ro3
1 + gm3ro3≈ 1
gm3ro3+∆gm,3−4
gm,3−4
Opamp-I 13-29 Analog ICs; Jieh-Tsorng Wu
Power Supply Rejection Ratio (PSRR)
oV
v
ddv
B1
C
V
ss
cvid
VDD
VSS
VDD
VSS
M1 M2
M3 M4
M6
M7M5
vo = −Avvid + Addvdd + Assvss
PSRRDD ≡Av
Add
PSRRSS ≡Av
Ass
Av =Av(0)
1 − s/p1
Av(0) = gm1gm6R1R2
Av(0)p1 = −gm1
Cc
Av ≈gm1
sCc
for ω |p1|
Opamp-I 13-30 Analog ICs; Jieh-Tsorng Wu
Power Supply Rejection Ratio (PSRR SS)
vo
r x C
x
x
Cc
VDD
VSS
vss1 ss2
Z 6
VSS
v
M1 M2
M3 M4
r C7o7
M6vo
vss1= Av,cm =
Av
CMRR
Z6 ≈1
gm6
Z7 =1
go7 + sC7
vo
vss2=
Z6
Z6 + Z7≈
Z6
Z7≈
go7 + sC7
gm6
1PSRRSS
=vo/vss1 + vo/vss2
Av
=1
CMRR+
(1 + sro7C7)(1 − s/p1)
gm6ro7Av(0)≈ 1
CMRR
Opamp-I 13-31 Analog ICs; Jieh-Tsorng Wu
Power Supply Rejection Ratio (PSRR DD)
B1V
Cc
VSS
1
xov
y
v
v
y0C
1
g m3
c
g m6 (vdd1 1- v
y
vdd1R1d C1d
v1
g m6
C
vo
R2
y
g m4 (v - v
oC
Cc
v
R2
)
R2
voR1
vdd2
vdd1
Ry0
vdd2 vdd1y )dd2
M1 M2
M4
M5
vy
M3
M6
M7
Opamp-I 13-32 Analog ICs; Jieh-Tsorng Wu
Power Supply Rejection Ratio (PSRR DD)
The voltage gain from vdd1 to vo is
vo
vdd1=
1
1 + 1+(g1d+sC1d )/(sCc)R2(g1d+sC1d )+gm6R2
≈ 1
1 + C1d/Cc
gm6R2
≈ 1
For vdd2 input, since gm3 + sCy Gy0 + sCy0, the resulting current flow in M3 isapproximately
iy0 ≈ vdd2 · (gy0 + sCy0)
The current is mirrored in M4, and amplified by M6 and Cc. The voltage gain is
vo
vdd2= iy0 · Av2 ≈ −
gy0 + sCy0
sCc
⇒vo
vdd2
vo
vdd1
Thus
PSRRDD ≈Av
vo/vdd1
≈ Av
Opamp-I 13-33 Analog ICs; Jieh-Tsorng Wu
PSRRDD with Common-Gate Miller Compensation
M3
M2
y 1
x
v1
voCc
vdd1
R1d C1d
vo
R2
v1
Cp
vdd1
Cc
g m6 (vdd1 1− v )
g m6
R2
Cc
vdd1
Cp
vo
Bias
vy
VSS
M6
M10
M7M5
M4
M1M10
M10
Assume the M10 stage has Rin = 1/gm10 and AI = 1. Neglecting R1d and C1d , we have
vo
vdd1=
1
11+sCc/gm10
·(Cc
Cp+ sCc
gm6
)+ 1
gm6R2
≈Cp
Cc
·(
1 + sCc
gm10
)
Opamp-I 13-34 Analog ICs; Jieh-Tsorng Wu
Supply Capacitance
CI
Vo
CI
CsupVn
cxV
yV
oVC
gd1
VB1
Id5gs1C
C
VDD
VSS
M1 M2
M3 M4
M5
M6
M7Vo = −Csup
CI· Vn
• Both Cgs1 and Cgd1 can function as Csup, and noises at Vx and Vy can leak to theoutput.
Opamp-I 13-35 Analog ICs; Jieh-Tsorng Wu
Power-Supply Rejection and Supply Capacitance
• The VDD noise can be coupled to Vy through the diode-connected M3 device. The useof cascode input stage can overcome this problem.
• If Id5 is modulated by the supply voltage variation, then vx ≈ id5/(2gm1). The use ofsupply-independent bias reference can overcome this problem.
• The noises at the substrate/well terminals of M1 and M2 can change the Vt of thedevices due to body effect, and cause Vgs variation, introducing noises at Vx. Asolution is to place both M1 and M2 in a single well, and connect well and sourceterminals together to eliminate body effect.
• Interconnect crossovers can introduce undesired coupling capacitors to the Vi−summing node. Careful layout is required.
• Fully-differential circuit topology generally has better power-supply rejectionperformance.
Opamp-I 13-36 Analog ICs; Jieh-Tsorng Wu
Device Noise Analysis
I SS
V DS3
vnT
I SS
V DS3
vn1 vn2
vn4vn3
I oI o
M1
M3
M2
M4
VDD
VSS
M1
M3
M2
M4
VDD
VSS
v2n ≈ 4kT
(23· 1gm
)+
Kf
W LCox
· 1f
i2n ≈ 0
v2nT
= v2n1 + v2
n2 +(gm3
gm1
)2(v2n3 + v2
n4
)
Opamp-I 13-37 Analog ICs; Jieh-Tsorng Wu
Thermal Noise Performance
Assuming M1=M2 and M3=M4, and knowing ID1 = ID3 so that
(gm3
gm1
)2
=µpCox(W/L)3
µnCox(W/L)1
=µp(W/L)3
µn(W/L)1
k′n = µnCox k′p = µpCox
The input referred thermal noise is
v2(Θ)T
∆f= 4kT
(43
1gm1
)+(gm3
gm1
)2
× 4kT(
43
1gm3
)= 4kT
(43
1gm1
)×[
1 +gm3
gm1
]
= 4kT
4
3· 1√
2k′n(W/L)1ID1
×
1 +
√√√√µp
µn
·(W/L)3
(W/L)1
• The load contribution can be made small by making gm1 > gm3 or (W/L)1 > (W/L)3.
• gm1 should be made as large as possible to minimize thermal noise contribution.
Opamp-I 13-38 Analog ICs; Jieh-Tsorng Wu
Flicker Noise Performance
The input referred 1/f noise is
v2(1/f )T
∆f=
2Kfn
W1L1Coxf+(gm3
gm1
)2
×2Kfp
W3L3Coxf=
2Kfn
W1L1Coxf+µp(W/L)3
µn(W/L)1
×2Kfp
W3L3Coxf
=1f×
2Kfn
W1L1Cox
(1 +
Kfp
Kfn
·µp
µn
·L
21
L23
)
• Kfp is typically smaller than Kfn by a factor of two or more.
• The load contribution can be made small by making L3 > L1. But longer L3 can limitsthe signal swing somewhat.
• The width of load devices does not affect the 1/f noise performance. But make itwider can maximize signal swing.
• Making W1 wider can reduce 1/f noise.
Opamp-I 13-39 Analog ICs; Jieh-Tsorng Wu
2-Stage Opamp with pMOST Input Stage
oV
Vi
B1
o
Vi
V
V’
VDD
Cc Buffer
VSS
Output
M1 M2
M3 M4
M5
M6
M7
Opamp-I 13-40 Analog ICs; Jieh-Tsorng Wu
2-Stage Opamp with pMOST Input Stage
Comparing to the nMOST-input opamps, the pMOST-input opamps have
• Similar dc voltage gain.
• Smaller gm1 and larger gm6.
• Larger unity-gain frequency since ωu |p2| and |p2| = gm6/C2.
• Better slew rate since both Vov1 and ωu are larger.
• Better 1/f noise performance.
• Poorer thermal noise performance.
Opamp-I 13-41 Analog ICs; Jieh-Tsorng Wu
Operational Amplifiers with Single-Ended Outputs
Jieh-Tsorng Wu
December 23, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Two-Stage Operational Amplifier with Cascode
o
Vi
Vi
I
B1V
B1
cCV
VDD
VSS
M7
VDD
M3
M3A
M1 M2
M6
M5
M2AM1A
M4A
M4
M8
M10
M9
• The volage gain Av ∝ (gmro)3.
• Size M8 so that
VDS1 = VDS2 VDSAT
• Input common-mode range isreduced by cascodes.
• The additional poles are non-dominant and located near ωT .
• The dominant poile is associated with the only high-impedance node at Vo. All otherpoles are located near ωT , and their magnitude are normally larger than |p2| of thetwo-stage opamps.
• CL provides the dominant-pole frequency compensation. Increasing CL improves thephase margin.
• If lead compensation is desired, a resistor can be placed in series with CL.
• Use nMOST input stage for larger gm1 and better thermal noise performance.
• Good PSRR since no pole-splitting Cc.
• Slightly higher noise due to more devices.
• Suitable for low-voltage operation.
• Active cascodes can be used to increase voltage gain.
Opamp-II 14-6 Analog ICs; Jieh-Tsorng Wu
Folded-Cascode Operational Amplifier
VDD
V ccp
VSS
V ccn
V o
CL
V i+
V i-
I 1
V bsp
M2M1
M3M4
M5M6
M7M8
M9M10M11 M12
Opamp-II 14-7 Analog ICs; Jieh-Tsorng Wu
Folded-Cascode Operational Amplifier
If bias currents ID1,D2 > ID3,D4, i.e., I1 > ID9,D10,
• Without M11 and M12, the slew rate is
SR =ID9
CL
=ID10
CL
• During slew condition, M11 and M12 can be used to clamp the drain volage of M1and M2 to reduce bias recovery time, and increase ID9 and ID10 to improve SR.
If bias currents ID1,D2 < ID3,D4, i.e., I1 < ID9,D10,
• This slew rate is
SR =I1
CL
I1 = ID1 + ID2
• M11 and M12 are not required.
Opamp-II 14-8 Analog ICs; Jieh-Tsorng Wu
Current-Mirror Operational Amplifier
V ccp
VDD
V ccn
V o
CL
V i+
V i-
I 1
VSS
M2M1
M3 M4 M5M6
M9M10 M11M12
M7 M8
M13M14
Opamp-II 14-9 Analog ICs; Jieh-Tsorng Wu
Current-Mirror Operational Amplifier
(W
L
)3=(W
L
)4=(W
L
)6=
1K
(W
L
)5
(W
L
)7=
1K
(W
L
)8
ID1,D2 = ID3,D4 = ID6 = ID7 =1KID5 =
1KID8 =
12I1 SR =
K I1
CL
Av(0) = Kgm1Ro Ro =1
go5gm11ro11
+ go8gm14ro14
p1 = − 1RoCL
ωu =Kgm1
CL
• For a given power dissipation, the current-mirror opamps have larger bandwidth andSR than the folded-cascode opamps. But they also suffer from larger thermal noise.
• For small CL, K may have to be reduced to prevent the nondominant poles fromdegrading the phase margin.
• A practical upper limit on K is around 5. For a general-purpose opamp, K 2.
Opamp-II 14-10 Analog ICs; Jieh-Tsorng Wu
Rail-to-Rail Complementary Input Stage
I
o,p1I
o,n2I
o,n1I
o,p2
V i-
i+ V i-
V i+
V
i-V i+
I
I 2n
I 2p
I 1n
I n
I pV
1p
VDD
VSS
M1 M2
M3 M4
Opamp-II 14-11 Analog ICs; Jieh-Tsorng Wu
Rail-to-Rail Complementary Input Stage
• Total input stage transconductance is
Gm = gm1 + gm3
• Gm variation due to Vic change can degrade CMRR. Want
gm1 + gm3 =õnCox(W/L)1In +
õpCox(W/L)3Ip = Constant
If µnCox(W/L)1 = µpCox(W/L)3, want
√In +
√Ip =
√I1n − I2p +
√I1p − I2n = Constant
Opamp-II 14-12 Analog ICs; Jieh-Tsorng Wu
Rail-to-Rail Complementary Input Stage
• LetI1n = I1p = 4I I2n = I2p = 3I
At Vic (VDD − VSS)/2 √In +
√Ip =
√1I +
√1I = 2
√I
At Vic VSS , In = 0 and I2n = 0,
√In +
√Ip =
√0I +
√4I = 2
√I
At Vic VDD, Ip = 0 and I2p = 0,
√In +
√Ip =
√4I +
√0I = 2
√I
• Less than 5% change in Gm is possible.
• The variation of the input-referred dc offset VOS due to Vic change also degradeCMRR.
Opamp-II 14-13 Analog ICs; Jieh-Tsorng Wu
A Rail-to-Rail Input/Output Opamp
V i-V i+V bon
V bop
V ccp
V ccn
VDD
VSS
Cc
Cc
V o
CL
M1 M2
M3 M4
I p
I n M16
M11 M12
M13M14
M15
M17M18
M23
M24
M25
M26
M21
M22
Opamp-II 14-14 Analog ICs; Jieh-Tsorng Wu
A Rail-to-Rail Input/Output Opamp
• Two cascaded gain stages.
• Noises in Vbop and Vbon are canceled at output.
• The bias of the output stage is insensitive to variations in Ip, In and supply voltage.
• The two Cc are connected as Miller frequency compensation using common-gatestages.
• The output pole is
p2 =Cc
Cgso
×gmo
CL
where gmo and Cgso are respectively the total gm and Cgs of the output stage.
• Reference: Hogervorst, et al., JSSC 12/94, pp. 1505–1513.
Opamp-II 14-15 Analog ICs; Jieh-Tsorng Wu
Low-Voltage Multi-Stage OpampVDD
VSS
V o
V i+ V i-
Bias
M2M1
M3M4
M5 M6M7
M8
M9
M10
C3
C2a C2b
C1b
C1a
M11
M12
Opamp-II 14-16 Analog ICs; Jieh-Tsorng Wu
Low-Voltage Multi-Stage Opamp
• Four cascaded gain stages.
• Hybrid nested Miller compensation.
• Class-AB output stage.
• A supply voltage below 1.5 V is possible.
• Reference: Eschauzier, et al., JSSC 12/94, pp. 1497–1504.
Opamp-II 14-17 Analog ICs; Jieh-Tsorng Wu
Current-Feedback Configuration
RL
V i
Z iI x
I oV o
V i
RL
V o
R2
R1
Current-Feedback Opamp
R2
R1
V x
Voltage-Feedback Opamp
For the voltage-feedback opamp, let Vo/Vx = A ≈ ωu/s and Zi →∞, then
Av =Vo
Vi= −
R2
R1· 1
1 + 1A
(1 + R2
R1
) ≈ −R2
R1· 1
1 + sωu
(1 + R2
R1
)
• Trade-off between closed-loop gain and closed-loop bandwidth.
Opamp-II 14-18 Analog ICs; Jieh-Tsorng Wu
Current-Feedback Configuration
For the current-feedback opamp, let Io/Ix = A ≈ ωu/s, then
Av =Vo
Vi= −
R2
R1·
1 − Zi
AR2
1 + 1A
[1 + R1R2+Zi (R1+R2+RL)
R1RL
] ≈ −R2
R1· 1
1 + sωu
[1 +
R2+Zi
(1+
R2+RLR1
)RL
]
If Zi → 0,
Av ≈ −R2
R1· 1
1 + sωu
(R2RL
)
• The closed-loop gain can be modified by changing R1, leaving the closed-loopbandwidth unchanged.
• For a given R2, frequency compensation can be optimized. Suitable for high-frequency applications.
Opamp-II 14-19 Analog ICs; Jieh-Tsorng Wu
A CMOS Current-Feedback Driver
V bon
V bop
V ccp
V ccn
V icm
V o
V o
VDD
VSS
V i
M21
M22
2I
2I
M4
I
I
LR
R2
R1
M2
M3M23
M24
M11
M12
M1
Opamp-II 14-20 Analog ICs; Jieh-Tsorng Wu
A CMOS Current-Feedback Driver
• This opamp has been designed to drive RL = 25 Ω and provide 50 mA of outputcurrent.
• Two-stage opamp with only one high-impedance node.
• Cgs and Cgd of M21 and M22 are large enough to provide adequate frequencycompensation.
• The class-AB common-gate input stage provides large internal slew rate.
• Large voltage swing of Vgs21 and Vgs22 are required.
• Open-loop current gain is determined by the output stage,
A(s) ≈gmo
sCgo
=ωu
sωu =
gmo
Cgo
• Loop gain T (s) ≈ A(s)RL/(RL + R2) is independent of R1.
Opamp-II 14-21 Analog ICs; Jieh-Tsorng Wu
A General-Purpose BJT Current-Feedback Opamps
V nV i
VCC
VEE
I B
I B
Ro Cc
V o
I f
I f
Q1
Q2
1:1
1:1
R2
R1
BufferOutput
1Q3
Q4
Opamp-II 14-22 Analog ICs; Jieh-Tsorng Wu
A General-Purpose BJT Current-Feedback Opamps
Due to the symmetry of the input stage, we have Vi = Vn.
If R1 ‖ R2 1/(gm1 + gm2), we have
If =Vo − Vn
R2−
Vn
R1= Vo
(1R2
)− Vi
(1R1
+1R2
)Vo = −If
(1
sCc + 1/Ro
)
Av =Vo
Vi=[Ro(R1 + R2)
(Ro + R2)R1
][1
1 + sCc(Ro‖R2)
]
If Ro R2,
Av ≈(
1 +R2
R1
)(1
1 + sCcR2
)Also the loop gain is
T (s) =
(1
sCc + 1/Ro
)(1R2
)≈ 1
sCcR2
Opamp-II 14-23 Analog ICs; Jieh-Tsorng Wu
Fully Differential Operational Amplifiers
Jieh-Tsorng Wu
July 16, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Vcfb = (Voc − VCM) · T (s) Voc = Vnc − Vcfb ⇒ Voc =T
1 + T× VCM +
11 + T
× Vnc
• Want large CMFB loop gain, T , to stabilize Voc.
• May want large ωt of T to suppress high-frequency components in Vnc.
• Must check the frequency stability of 1/[1 + T (s)].
Opamp-III 15-6 Analog ICs; Jieh-Tsorng Wu
A Fully Differential Two-Stage Operational Amplifier
v
Vi2Vi1
VB2
VB1
i1
g
2x
Vo1
o5
VB1
v
Cc1 Cc2
Cc1
DM Half Circuit
v o1i1
Vo2
VB1
Cc1v
CM Half Circuit
C
o1
2
VDD VDD
VDD
VSS
M3 M4
M5
M1 M2
M6
M7
M8
M9
M1
M3
M7
M6
M1
M3
M7
M6
Opamp-III 15-7 Analog ICs; Jieh-Tsorng Wu
CMFB Using Resistive Divider and Error Amplifier
IB3
VB1
VCM
VB1
B1 I
o1V
B2
o2
I
V
VDD VDD
VSS VSS
C1
R1
M7
C2
R2
M9
MB2
MB4
MB1
MB3
M6 M8
MB5 MB6
Common-Mode Feedback
Opamp-III 15-8 Analog ICs; Jieh-Tsorng Wu
CMFB Using Resistive Divider and Error Amplifier
C1
R1
MB3
mb1g
2
MB5MB6v
C
nc1i
nc2i
Cc1
oc
v
L
oc
M7
M6
• The loop gain |T | ≈ gmb5(ro6 ‖ ro7) · gmb1/(2gmb3).
• C1 and C2 are used to improve high-frequency response.
• The resistive loading of R1 and R2 can degrade Adm. Voltage buffers can be addedbetween the opamp’s outputs and the resistive divider.
Opamp-III 15-9 Analog ICs; Jieh-Tsorng Wu
CMFB Using Resistive Divider and Direct Current Injection
I
VB1
B2B1
VB1 IB3
CM
I
o2Vo1V
V
VDD VDD
VDD
VSSVSS
C1
R1
M7
C2
R2
M9
M6 M8
Common-Mode Feedback
MB3MB1 MB2
Opamp-III 15-10 Analog ICs; Jieh-Tsorng Wu
CMFB Using Dual Differential Pairs
VB1 VB1
CM 1I2I
o2V
o1V
B3I B4I
3I
IB1 IB2
V
VDD
VSS
VDD
VSS
M7 M9
M6 M8
MB7 MB8
MB1MB2MB4MB3
MB6 MB5
Common-Mode Feedback
Opamp-III 15-11 Analog ICs; Jieh-Tsorng Wu
CMFB Using Dual Differential Pairs
For the MB1-MB2 and MB3-MB4 source-coupled pairs,
IBB = IB3 = IB4 = 2 × k
2· V 2
ov k = k′(W
L
)
Idd =k
2Vid
√4IBB
k− V 2
idId1 =
IBB
2+Idd
2Id2 =
IBB
2−Idd
2
I1 =IBB
2+k
4(Voc + Vod/2 − VCM)
√4IBB
k− (Voc + Vod/2 − VCM)2
≈IBB
2+k
4(Voc − VCM + Vod/2)
√4V 2
ov − (Vod/2)2 − (Voc − VCM)Vod
≈IBB
2+k
4(Voc − VCM + Vod/2)
√4V 2
ov − (Vod/2)2
×
1 − 1
2
[(Voc − VCM)Vod
4V 2ov − (Vod/2)2
]− 1
8
[(Voc − VCM)Vod
4V 2ov − (Vod/2)2
]2
+ · · ·
Opamp-III 15-12 Analog ICs; Jieh-Tsorng Wu
CMFB Using Dual Differential Pairs
I2 ≈IBB
2+k
4(Voc − VCM − Vod/2)
√4V 2
ov − (Vod/2)2
×
1 +
12
[(Voc − VCM)Vod
4V 2ov − (Vod/2)2
]− 1
8
[(Voc − VCM)Vod
4V 2ov − (Vod/2)2
]2
+ · · ·
I3 = I1 + I2 ≈ IBB +k
2(Voc − VCM)
√4V 2
ov − (Vod/2)2
×
1 − 1
4
[V
2od
4V 2ov − (Vod/2)2
]− 1
8
[(Voc − VCM)Vod
4V 2ov − (Vod/2)2
]2
+ · · ·
• The input devices, MB1–MB4, must remain in the forward-active region over thevoltage range of Vo1 and Vo2.
• The variation in Vod can produce an ac component in I3 as well as Voc.
• If Voc = VCM , I1 and I2 are nonlinear functions of Vod , but I3 = I1 + I2 is a constant.
Opamp-III 15-13 Analog ICs; Jieh-Tsorng Wu
CMFB Using Transistors in the Triode Region
MB3
MB5
MB6
VB1
MB4
MB2
B2
VB1
Vo1
Vo2
MB1VCM
IB3I
V
1I 2I
x y
B1
V
I
VDD
VSS
VDD
VSS
M7 M9
M6 M8
Common-Mode Feedback
Opamp-III 15-14 Analog ICs; Jieh-Tsorng Wu
CMFB Using Transistors in the Triode Region
MB1, MB2, and MB5 are in the triode region. Let kB1 = kB2 = kB5 = k,
I1 = k
(Vo1 − Vtn −
12Vx
)Vx I2 = k
(Vo2 − Vtn −
12Vx
)Vx IB3 = k
(VCM − Vtn −
12Vy
)Vy
⇒ I1 + I2 = 2k(Voc − Vtn −
12Vx
)Vx Vx ≈ Vy =
IB3
k(VCM − Vtn − 1
2Vy)
I1 + I2 = 2IB3 ·Voc − Vtn − 1
2Vx
VCM − Vtn − 12Vy
= 2IB3
(1 +
Voc − VCM
VCM − Vtn − 12Vy
)
• Output swing is reduced, since it is required that Vo1,o2 > Vtn + Vx.
• MB1 and MB2 are in the triode region, their effective gm can be small, thus degradingloop gain and bandwidth of the CMFB.
Opamp-III 15-15 Analog ICs; Jieh-Tsorng Wu
Switched-Capacitor CMFB
S2S1
S8VB1
S5 S6
S4S3
C4C2
VB1 S7
C1
MB3MB2
Vo1
Vo2
MB1
IB1 IB2
C3
1
φ
2
IB3
CBVx
φ
VCB
VCM
V2
2
2
I1 I2
VCM
1
1
2
1
1
VDD
VSS
VDD
M7 M9
M6 M8
Common-Mode Feedback
VSS
Voc − Vx = VCM − VCB ⇒ Voc ≈ VCM
Opamp-III 15-16 Analog ICs; Jieh-Tsorng Wu
Switched-Capacitor CMFB
• The opamp operates in two different modes. It is in the normal mode when φ2 is low.
• Assuming ∆Q charges are injected into C3 and C4 when φ1 switches are turned off,
Voc − Vx = VCM − VCB +∆Q
C3⇒ Voc ≈ VCM +
∆Q
C3
• The loop gain of the CMFB is approximately
|T | ≈C1
C1 + Cgs,B1× gm,B1 · Ro1
• C1 and C2 add differential-mode capacitive loading to the outputs.
• The additional common-mode capacitive loading is (C1 + C2) ‖ (Cgs,B1 + Cgs,B2).
• The value of C3,4 may be between 1/4–1/10 of C1,2 for low-pass filter function.
Opamp-III 15-17 Analog ICs; Jieh-Tsorng Wu
Folded-Cascode Operational Amplifier
V
o1V
BN1V
BP1
1I
VBP2
V
VVi2
CMFB
V
Vi1 o2
BN2 BN2
VDD
VSS
M4
M10
M2M1
MB3M6M5 MB4
MB1M8M7 MB2
M3
M9
Opamp-III 15-18 Analog ICs; Jieh-Tsorng Wu
Folded-Cascode Operational Amplifier
• Frequency compensation is provided by the capacitive loads at the outputs.
• Non-dominant poles are determined by M3 and M4, and ≈ ωt3 (ωt4).
• It is not uncommon that ID1,D2 ID3,D4.
• For high-speed designs, use pMOST input stage. The resulting opamps has highernon-dominant poles.
• Active cascode configuration can be applied to M3, M4, M5, and M6.
Opamp-III 15-19 Analog ICs; Jieh-Tsorng Wu
Current-Mirror Operational Amplifier
i1
V
V
o1VV
BP2V
i2
CMFB
o2
1IBN1
BN2V
V
VBN2
VDD
VSS
M2M1
M3 M4 M5M6
M9M10 M12
M13M14
M7M8
MB3MB4
MB1MB2
M11
Opamp-III 15-20 Analog ICs; Jieh-Tsorng Wu
Current-Mirror Operational Amplifier
The M3-M5 and M4-M6 current mirrors have a current gain of K .
(W
L
)3
=(W
L
)4
=1K
(W
L
)5
=1K
(W
L
)6
ID1 = ID2 = ID3 = ID4 =1KID5 =
1KID6 =
12I1
• The single-ended maximum output current for slewing is
Io(max) =K
2I1
• For a general-purpose fully differential opamp, may use large pMOST input stage,K=2, and wide-swing enhanced output-impedance cascode current mirrors.
Opamp-III 15-21 Analog ICs; Jieh-Tsorng Wu
Current-Mirror Push-Pull Operational Amplifier
1
CMFBCMFB
I1I
Vo2o1Vi2VVi1
Vi2 Vi1
VSS
VDD
1:1K:1
K:1
1:1 1:K
M1 M2 M3M4
1:K
Opamp-III 15-22 Analog ICs; Jieh-Tsorng Wu
Current-Mirror Push-Pull Operational Amplifier
• The single-ended maximum output current for slewing is
Io(max) = K I1
• The small-signal response is slower due to additional signal paths.
Opamp-III 15-23 Analog ICs; Jieh-Tsorng Wu
Class-AB Operational Amplifier
CMFB1 2I
o1V o2V
Vi2i1
I
CMFB
V
VSS
1:KK:1
M1 M2M3 M4
VDD
K:1 1:K
M5 M6M7 M8
II
Opamp-III 15-24 Analog ICs; Jieh-Tsorng Wu
Class-AB Operational Amplifier
If nMOSTs M1–M4 are identical, and pMOSTs M5–M8 are identical, and all currentmirrors have a current gain of K , then the bias currents are
ID1 = ID2 = ID3 = ID4 =1KI1 =
1KI2 = I
• Low quiescent power and large slew rate.
• The input level shifter increases the noise and offset, and adds additional poles.
• A1 and A2 auxiliary amplifiers are used to increaseoutput impedance and the dc voltage gain, Av(0).
• Explicit compensation capacitors may be required atthe outputs of A1 and A2.
• To increase ∆Vo, M7, M8, and M9, can be biased inthe triode region. However, Av(0) is reduced due to thereduced ro of M7 and M8. Also, CMRR and PSRR aredegraded due to the reduced ro of M9.
• Reference: Gulati and Lee, JSSC 12/98, pp. 2010–2019.
• The VOS is sampled in the sample mode, and canceled in the hold mode.
• The opamp’s output has small voltage variation. Thus, it is easier to design the opampfor high speed.
• Suitable for high speed.
S/H 17-25 Analog ICs; Jieh-Tsorng Wu
A MOST Recycling S/H
A1
CH2CH1
B1
V o
Hold Mode
A1
CH2CH1
B1
V oV i
Sample Mode
CLK
A1
M1
B2B1
M5
CH3
M2
M3
M4
CH1
V o
CH2
V i
φ1
φ1 φ2
φa1
φa1
φa2
φ1
φ2
φa1
φa1
φ1
φ2
S/H 17-26 Analog ICs; Jieh-Tsorng Wu
A MOST Recycling S/H
• B1 and B2 are two unity-gain buffer.
• M5 and CH3 is to compensate for the M4’s switching error.
• The switching errors of M1 and M2 does not affect Vo.
• The switching error of M3 does affect Vo. But its effect is reduced by the opamp’svoltage gain.
• Mismatch between B1 and B2 can affect Vo.
S/H 17-27 Analog ICs; Jieh-Tsorng Wu
Closed-Loop S/H
V iV o
M11
CH
A1
φ
S/H 17-28 Analog ICs; Jieh-Tsorng Wu
Closed-Loop S/H
• The circuit is in the track mode when φ = 1, and is in the hold mode when φ = 0.
• High input impedance.
• The offset and gain of the output buffer are not critical.
• The input offset of the A1 opamp is not canceled.
• The speed can be seriously degraded due to the necessity of guaranteeing that theloop is stable in the track mode.
• The A1 opamp is open loop when in the hold mode. It takes time to recover the biaswhen switches to the track mode.
S/H 17-29 Analog ICs; Jieh-Tsorng Wu
Closed-Loop S/H with Improved tslew
V iV o1
CH
A1M1
M3
M3φ
φ
φ
• During hold mode, A1 is configured as a unity-gain amplifier. Thus, the slewing timeis greatly minimized.
S/H 17-30 Analog ICs; Jieh-Tsorng Wu
Closed-Loop S/H Using Active Integrator
V oA2
M3
V i M1
M2
A1
C
CH1
H2
φ
φφ
S/H 17-31 Analog ICs; Jieh-Tsorng Wu
Closed-Loop S/H Using Active Integrator
• When in the track mode, the voltage on both sides of M1 are closed to ground, andare nearly signal independent.
• Aperture jitter is minimized.
• The switching error of M1 causes a dc offset in Vo, which will be signal independent.
• M2 and CH2 are to compensate for the M1 switching error.
• When in the hold mode, M3 clamps the A1’s output to ground, speeding up the timeit takes the S/H to return to the tack mode.
• M3 also reduces signal feedthrough when in the hold mode.
• The speed is degraded because of the necessity to guarantee stability in the trackmode.
S/H 17-32 Analog ICs; Jieh-Tsorng Wu
An RC Closed-Loop S/H
V oV i
M1
CH
A1M2
R
R
φ
φ
• The A1 opamp need to have low output impedance.
S/H 17-33 Analog ICs; Jieh-Tsorng Wu
A Switched-Capacitor Closed-Loop S/H
Sample Mode
Hold Mode
o
Vo
V
M3
CH1
C
M1
M2
M4
M5
M6
CH3
H4CH2
A1
V i
A2
A1
CH3
A2
CH1
CH2
o
A1
C
CH3
H4
CH1
V i
A2
CH2
V
φ1 φ2
φa1
φa2
φ1
φ2
φa1
φa1
φa2
φa2
φ1 = 1
φ2 = 1
S/H 17-34 Analog ICs; Jieh-Tsorng Wu
A Switched-Capacitor Closed-Loop S/H
• The Vo is always valid.
• The VOS1 of A1 is stored in CH2 during the sample mode.
• The M2’s switching error is canceled by M3.
• The M5’s switching error is canceled by M6.
• The switching error of M1 and M4 doesn’t affect Vo.
S/H 17-35 Analog ICs; Jieh-Tsorng Wu
Charge Redistribution Sampled-Data Amplifier
V1
1t 2t
OSV
V oC1
OSV
V oC1
V i
OSV
1a
S3
C2
V o
Q
C12
1V i
C2C2
S2
S1
φa1
φ1
φ2
φ1 = 1 φ2 = 1
S/H 17-36 Analog ICs; Jieh-Tsorng Wu
Charge Redistribution Sampled-Data Amplifier
To consider the ideal case, let A =∞ and VOS = 0, then
Vo(t1) = 0
C1Vi(t1) = C2Vo(t2) ⇒ Vo(t2) =C1
C2× Vi(t1)
To consider the VOS effect, let A =∞, then
Vo(t1) = VOS(t1)
Vo(t2) =C1
C2× Vi(t1) + VOS(t1) +
(1 +
C1
C2
)×[VOS(t2) − VOS(t1)
]=
C1
C2×[Vi(t1) +
C2
C1· VOS(t1)
]+(
1 +C1
C2
)×[VOS(t2) − VOS(t1)
]
• The input referred offset is VOS · (C2/C1).
S/H 17-37 Analog ICs; Jieh-Tsorng Wu
Charge Redistribution Sampled-Data Amplifier
To consider the finite gain effect, let VOS = 0, then during φ2 = 1
C1Vi + C1V1 = C2(Vo − V1) Vo = −AV1 ⇒ Vo =C1
C2· 1
1 + 1A
(1 + C1
C2
) × Vi
To consider the effect S3 switching error, let A = ∞, VOS = 0, and Vi = 0, then duringφ2 = 1
Vo = V ′OS
= −∆QC2
• V′OS is independent of input.
• If S3 is opened before S1, the switching errors of S1 and S2 have no effect on Vo.
S/H 17-38 Analog ICs; Jieh-Tsorng Wu
Charge Redistribution Summing Amplifier
1
1OSV
C1
S1V i1
V2
S2
C
V
V2
i2
i3
i4
S3
S4
2
1a
S5
C3
V o
During the sample mode (φ1 = 1)
Vo = VOS
During the hold mode (φ2 = 1)
Vo =C1
C3(Vi1 − Vi2)
+C2
C3(Vi3 − Vi4) + VOS
S/H 17-39 Analog ICs; Jieh-Tsorng Wu
Sampled-Data Amplifier with CDS
V1
1t 2t
OSV
V oC1
OSV
V oC1
1
2V i
1a
C2 1C2
OSV
V oC1
C2
V i
S2
S1
S3
2
S5S4
φa1
φ1
φ2
φ1 = 1 φ2 = 1
S/H 17-40 Analog ICs; Jieh-Tsorng Wu
Sampled-Data Amplifier with CDS
Let A =∞, then
Vo(t1) = Vc1 = Vc2 = VOS(t1)
Vo(t2) = −C1
C2× Vi(t2) +
(1 +
C1
C2
)[VOS(t2) − VOS(t1)]
• The correlated double-sampling (CDS) technique, resulting in VOS(nTs) − VOS(nTs −Ts/2), can reduce the effects of the opamp’s input offset voltage and its 1/f noise.
• To minimize switching noises, realize switches with nMOSTs whenever possible, andturn off the switches near the virtual ground node of the opamps first.
• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Effectsof Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and ChopperStabilization,” Proc. IEEE, Nov. 1996, pp. 1584–1614.
S/H 17-41 Analog ICs; Jieh-Tsorng Wu
A Capacitive-Reset Sampled-Data Amplifier
3t 4t1t 2t
V1V1
C1
C2a1
V o
C3
1
2V i
1
OSV OSV
V o
C3
OSV
V o
C3
V i
C4
S5
S2
S1
2
S4S3
S6
2a
C1C1
C2 C2
φa1
φa2
φ1
φ2
φ1 = 1 φ2 = 1
S/H 17-42 Analog ICs; Jieh-Tsorng Wu
A Capacitive-Reset Sampled-Data Amplifier
To consider the VOS effect, let A =∞ and Vi = 0, then
V1(t1) = VOS(t1)
Vo(t2) =(
1 +C1
C2
)×[VOS(t2) − VOS(t1)
]Vo(t3) = VOS(t3) + Vo(t2) +
C2
C3× Vo(t2) +
(1 +
C1 + C2
C3
)×[VOS(t3) − VOS(t2)
]≈ VOS(t3)
Vo(t4) =(
1 +C1
C2
)×[VOS(t4) − VOS(t3)
]
• During φ2 = 1, the effects of opamp’s VOS and 1/f noise are reduce by CDS.
S/H 17-43 Analog ICs; Jieh-Tsorng Wu
A Capacitive-Reset Sampled-Data Amplifier
To consider the finite gain effect, let VOS = 0, then
• During φ2 = 1, the effects of opamp’s VOS and 1/f noise are reduce by CDS.
• During φ2 = 1, the errors due to opamp’s finite gain, A, are proportional to 1/A2 forlow-frequency input.
• During φ1 = 1, the output keeps the value obtained in the previous φ2 = 1 period.
• C4 is an optional deglitching capacitor used to provide continuous-time feedbackduring the nonoverlap clock times. This capacitor would normally be small.
• The clock phases for S1 and S2 can be exchanged, to obtain noninverting gain.
• When CDS is used, the opamps should be designed to minimize thermal noise ratherthan 1/f noise.
S/H 17-45 Analog ICs; Jieh-Tsorng Wu
A Capacitive-Reset CDS Amplifier
C2
1a
V o
2S6
2S5
1
1C’
V i
2C’
C2
V oV i
1C’
C1
2C’
C2
V i
V o
C1
1C’
S1
2
C1
1S3
S2
S7
S9
1
S8S10
a2
2C’1
S42 A
A
φ1 = 1
φ2 = 1
S/H 17-46 Analog ICs; Jieh-Tsorng Wu
A Capacitive-Reset CDS Amplifier
• During φ1 = 1, C′1 and C′2 are used in the feedback network to have
Vo ≈ −C′1
C′2· Vi
but with errors due to VOS , 1/f noise, and A.
• During φ1 = 1, the opamp input voltage is sampled and stored in C1 and C2.
• During φ2 = 1, C1 and C2 are used in the feedback network, the output errorsdue to VOS , 1/f noise, and A are canceled by the correlated double-sampling (CDS)operation.
S/H 17-47 Analog ICs; Jieh-Tsorng Wu
Comparators and O ffset Cancellation Techniques
Jieh-Tsorng Wu
October 25, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Comparators
Vi1
Vi2Vo
Vi1 Vi2
Vo VoVi2
Vi1
0
A
CLK
Latch
Typical Architecture
• A comparator compare the instantaneous values of two inputs generate a digital 1 or0 level depending on the polarity of the difference.
• Usually a clock is applied to improve the performance.
Comparators 18-2 Analog ICs; Jieh-Tsorng Wu
Comparator Design Considerations
• Resolution (gain).
• Accuracy (offset).
• Input range (dynamic range).
• Common-mode rejection.
• Speed (conversion time, over-drive recovery).
• Power dissipation.
• Input kickback noise.
• Area
Comparators 18-3 Analog ICs; Jieh-Tsorng Wu
Comparison with Single-Pole Amplifier
Vi
Vo
VoVi
U
tt a
A o
R
V ig m
C
U =Vo
Vi= Ao
[1 − e−ta/(RC)
]Ao = gmR τm =
C
gm
ta
τm= Ao × ln
1
1 − UAo
⇒
ta
τm≈ U if U Ao
• The amplification in a comparator need not be linear.
Comparators 18-4 Analog ICs; Jieh-Tsorng Wu
Comparison with Multi-Stage Cascaded Amplifier
Vi
Vo2Vo1 Vo
VV o1 o(N−1)
R C
g m g mV ig m
R C R C
ta
τm≈ (U ×N!)
1N for ta Aoτm
• There exits an optimum number of cascaded stages for minimum ta.
• Optimum in N is very broad.
• Gain of√
10 (i.e. 10 dB) per stage results in near optimum delay (within 10%).
Comparators 18-5 Analog ICs; Jieh-Tsorng Wu
Comparison with Positive-Feedback Regeneration
Vo1 Vo2Vo (0)
(t)
oVoV
CRRC
U
tg m g m t a
U =Vo(ta)
Vo(0)= e
(Ao−1)taRC Ao = gmR τm =
C
gm
ta
τm=
1
1 − 1Ao
× ln(U) ⇒ta
τm≈ ln(U) if Ao 1
Comparators 18-6 Analog ICs; Jieh-Tsorng Wu
Comparison with Positive-Feedback Regeneration
• The gain is not bounded by Ao.
• It is faster than the multi-stage cascaded amplifier, and dissipates less power.
• Require a strobe signal (clock).
• Let Tc be the conversion time, the final output Vo(Tc) = V , and the initial sampledinput Vo(0) has a uniform distribution between −V and +V . Then the probability ofobserving a metastable state is
P =V/U
V=
1U
= e−(Ao−1)Tc
RC ≈ e− TcC/gm
The metastable state occurs when the sampled input is so small that the regeneratedoutput, |Vo|, cannot reach |V | after the Tc period.
Comparators 18-7 Analog ICs; Jieh-Tsorng Wu
Output O ffset Storage (OOS)
V o
CL1a
S3
oV’Q
V i
V OS
V c
CoV OSL
LatchAS1
2
S21
During the reset mode (φ1 = 1)
Vo = 0 Vc = A × VOS
During the amplification mode (φ2 = 1)
V ′o = Vi × A ·Co
Co + CL
+∆Q
Co + CL
− VOSL = A ·Co
Co + CL
(Vi +
∆Q
ACo
−VOSL
A·Co + CL
Co
)
Input-Referred Offset = VOS,in =1A· ∆QCo
−VOSL
A·Co + CL
Co
Comparators 18-8 Analog ICs; Jieh-Tsorng Wu
Output O ffset Storage (OOS)
• During the reset-to-amplification transition, let S3 open before S2, so that ∆Q can bea constant.
• Amplifier A cannot employ high gain.
• Amplifier A must cover the input common-mode range.
• Want latch with high-impedance (capacitive) input so as not to discharge Co duringamplification.
During Period V (amplification mode), S2 closed, S1 open.
Vo = A1 · A2 · A3 · Vi + ε4
VOS,in =ε4
A1 · A2 · A3
Comparators 18-12 Analog ICs; Jieh-Tsorng Wu
Input O ffset Storage (IOS)
V c
V OS
1a
S3
V iiC
V o
CL
Q
AS2
2
1
S1
V OSL
Latch oV’
During the reset mode (φ1 = 1)
Vo = Vc = VOS ×A
A + 1
During the amplification mode (φ2 = 1)
V ′o = −Vi × A + VOSA
A + 1− ∆Q
Ci
A − VOSL = −A(Vi −
VOS
A + 1+∆Q
Ci
+VOSL
A
)
Input-Referred Offset = VOS,in = −VOS
A + 1+∆Q
Ci
+VOSL
A
Comparators 18-13 Analog ICs; Jieh-Tsorng Wu
Input O ffset Storage (IOS)
• The S3 switching error ∆Q is input-independent.
• During the reset-to-amplification transition, let S3 open before S2.
• The IOS allows rail-to-rail input common-mode level and quick overdrive recovery.
• Amplifier A can employs high gain.
• Amplifier A may require compensation Cc to ensure closed-looped stability. Cc canbe switched off during the amplification mode.
Comparators 18-14 Analog ICs; Jieh-Tsorng Wu
Multistage Input O ffset Storage
V oC1
Vc1
C2
Vc2
X
V
A
S3
V
A 1
OS1
S4
OS2
2
S1
S2
V i
S1
S2
S3
S4
I II III IV
Comparators 18-15 Analog ICs; Jieh-Tsorng Wu
Multistage Input O ffset Storage
During Period I, S1 open, S2–S4 closed.
Vc1 =A1
A1 + 1VOS1 Vc2 =
A2
A2 + 1VOS2 − Vc1 =
A2
A2 + 1VOS2 −
A1
A1 + 1VOS1
During Period region II, S3 open. Let ε1 be the 3 switching error.
Vc1 =A1
A1 + 1VOS1 + ε1 Vc2 =
A2
A2 + 1VOS2 −
A1
A1 + 1VOS1 + A1ε1
During Period III, S4 open. Let ε2 be the S4 switching error.
Vc2 =A2
A2 + 1VOS2 −
A1
A1 + 1VOS1 + A1ε1 + ε2 Vo =
A2
A2 + 1VOS2 − A2ε2
Comparators 18-16 Analog ICs; Jieh-Tsorng Wu
Multistage Input O ffset Storage
During Period IV (amplification mode), S2 open, S1 closed.
Vo = A1A2Vi +A2
A2 + 1VOS2 − A2ε2 = A1A2
[Vi +
VOS2
A1(A2 + 1)−
ε2
A1
]
Input-Referred Offset = VOS,in =VOS2
A1(A2 + 1)−
ε2
A1
Comparators 18-17 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Auto-Zeroing Inverter
VSS
VDD
2
1MB
V o
V i1
V i2
V o
V x
CI
S1
S2
1
S3
XMA
Bias Poin t
Comparators 18-18 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Auto-Zeroing Inverter
• Trade-off between speed and resolution by selecting different value of C.
• Very sensitive to supply noises.
• Power dissipation is strongly process- and supply-dependent.
• Kickback noise presented at the inputs.
• Reference: T. Kumamoto, et. al., JSSC, 12/86, pp. 976–982.
Comparators 18-19 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Cascaded Auto-Zeroing Inverters
S1
S2
S3 S4C1 C2
M1
M2
M3
M4
VSS VSS
VDDVDD
CK
Latch
V i2
V i1
V o
S1
S2
S3
S4
CK
Comparators 18-20 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Preamp + Regenerative Sense Amplifier
VDD
VSS
V i1
VSS
V i2
VSS
V o
I 1
M1 M2
M3
M4
M5
M6
M7 M8 M9 M10
M11 M12VDD φ
Comparators 18-21 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Preamp + Regenerative Sense Amplifier
• During the track mode (φ = 1), want gm7,m8 < gm9,m10 so that the combination ofM7-M8 and M9-M10 pair become the resistive loads for M5 and M6. The small-signalvoltage gain is
vo
vi≈
gm1
gm9 − gm7·(W/L)6
(W/L)4
• During the latch mode (φ = 0), M7, M8, and M11 must be large enough to preventthe change of latched state by the Vi variation.
• All nodes are low impedance, thus giving fast operation.
• Overdrive recovery can be improved by adding an equalizing switch between the Vonodes.
• The preamplifier buffers the kickback from the input circuitry.
• Reference: B. Song, et al., JSSC, 12/90, pp. 1328–1338.
Comparators 18-22 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Preamp + Regenerative Sense Amplifier
VDD
VSS
V i1
VSS
V i2
I 1
VSS
VDD
V o
M3
M4 M6
M5
M1 M2
M7M8M9 M10
M11 M12
M13
IVT1
IVT2
A
B
φ
φ
Comparators 18-23 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Preamp + Regenerative Sense Amplifier
• During the track mode (φ = 1), need M7 and M8 large enough to overpower the M9-M10 cross-coupled pair and pull VA and VB below the input threshold level of IVT1 andIVT2.
• During the latch mode (φ = 0), the M9-M10 and M11-M12 pairs provide regeneration.They must be large enough to to prevent the change of latched state by the Vivariation.
The input threshold level of IVT1 and IVT2 must be high enough to avoid falsetriggering.
Comparators 18-24 Analog ICs; Jieh-Tsorng Wu
MOST Comparator: Merged Preamp + Sense Amplifier
CKCKM8
M2
M7M5
M9 M10
M11
M4M3
M1
CK
Vi
Vo
M6
VSS
VDD
• No power dissipation whenCK=0.
• When CK=1, the M1-M2 pair isactivated first, the M3-M4 pair issecond, and the M5-M6 pair isthe last.
• Kickback noise is generated atinput during the 0-to-1 transitionof CK.
• Reference: B. Razavi, 1999ISSCC Short Course.
Comparators 18-25 Analog ICs; Jieh-Tsorng Wu
Offset Canceled Latches: Idea
Gm1
RL1
RL2
V i V o
Gm2
C1
C2
S5
S6
S1
S2
S3
S4
12
1
1
• During reset mode (φ1 = 1), the OOS is applied to both Gm1 and Gm2.
• During reset mode, the finite on-resistance of S5 and S6 may cause oscillation.
• During reset-to-regeneration transition, any mismatch of the switching errors betweenS5 and S6 can trigger a false regeneration, yielding a large input-referred offset.
Comparators 18-26 Analog ICs; Jieh-Tsorng Wu
Offset Canceled Latches: Simplified Schematic
Gm1
RL1
RL2
V i V o
C2
C1
S31
Gm2
a2
S1
S2S41
B1
B2
S51
S61
1
S7
S8
S9
S10
1
2
2
Comparators 18-27 Analog ICs; Jieh-Tsorng Wu
Offset Canceled Latches: Simplified Schematic
• During reset mode, the positive feedback loop is completely broken.
• The regeneration begins only after Vi has been sensed and amplified.
• Buffers B1 and B2 isolate output nodes from C1 and C2, thus enhancing regenerationspeed.
• The residual offset is primarily cause by the switching errors of S5–S10.
• Reference: B. Razavi, et al., “Design Techniques for High-Speed High-ResolutionComparators,” JSSC, 12/92, pp. 1916–1926.
Comparators 18-28 Analog ICs; Jieh-Tsorng Wu
Offset Canceled Latches: MOST Implementation
VSS
VSSVSS
VDD
V o+ V o-
V 1+
V 2+ V 2-
V 1-
VSS
V B1 V B1
M1 M2
I1
I2
M3 M4
M5 M6M7 M8
M9M10
C1 C2
I4I3
MS1
MS3
MS2
MS4
MS5 MS6
MS7 MS8
MS9 MS10A B
E F DC
φ1 φ1
φ1 φ1
φ2 φ2φ1φ1
Comparators 18-29 Analog ICs; Jieh-Tsorng Wu
Offset Canceled Latches: MOST Implementation
• M7 and M8 are active loads, which both decrease the voltage drops across M5 andM6, increase available gain, increase Vo output swing, and enhance speed.
• An equalizing switch driven by φd1 can be placed between node C and D to eliminate
the switching error mismatch between MS7 and MS8.
• An equalizing switch driven by φd2 can be placed between node E and F to eliminate
the mismatch between MS5 and MS6. In this case, MS9 and MS10 are driven byφ
dd2 and the charge absorption mismatch between MS9 and MS10 becomes the only
significant contribution to the offset, which is
VOS(in) =∆Q
C·gm3 + gm7
gm1
• Reference: B. Razavi, JSSC, 12/92, pp. 1916–1926.
Comparators 18-30 Analog ICs; Jieh-Tsorng Wu
BJT Latched Comparator
V oV i
Q1 Q2 Q3 Q4
Q5 Q6
Q7
Q8
R1 R2
I1 I2 I3
VEE
VCC
φ
Comparators 18-31 Analog ICs; Jieh-Tsorng Wu
BJT Latched Comparator
• During the track mode (φ = 1), the variation of input capacitance with Vi causesinput-dependent delay and hence harmonic distortion.
• Speed may be limited by overdrive recovery.
• During latch-to-track transition, Q1 and Q2 are initially off, the I1 current then flowsthrough Q5 and the emitter junctions of Q1 and Q2 to the input, creating kickbacknoise.
• Usually preceded by a buffer.
Comparators 18-32 Analog ICs; Jieh-Tsorng Wu
BJT Comparator with High-Level Latch
I1
VEE
VCC
V i
V o
R1 R2
Q1 Q2
Q6 Q7Q8
Q3 Q4
Q5
AB
φ φ
• During the latch mode (φ = 0), the variationin Vi will not disturb the latched state.
• Q1 and Q2 are never turned off, thusreducing kickback noise.
• The kickback noise results only from thetransients at nodes A and B. Adding aresistor between A and B decreases thesetransient and improves the recovery at thesenode.
Comparators 18-33 Analog ICs; Jieh-Tsorng Wu
A Sampled-Data Amplifier with Internal O ffset Cancellation
V o1
V o2
C3
C5
C6
o1V
o2V
C5
C6
V o2
V o1
V i2
V i1
C1
2CC3
C4
C41
1
2
2
C
C
C
C
3
4
5
6
a1 a2
1
1
1
1
a1 a2
C1V i1
V i2
2C
a1 a2
2C
C1
2
1
1
φ1 = 1
φ2 = 1
Comparators 18-34 Analog ICs; Jieh-Tsorng Wu
A Sampled-Data Amplifier with Internal O ffset Cancellation
• During reset mode, OOS is applied to a1 and IOS is applied to a2. a1 is low gain anda2 is high gain.
• The OOS and IOS perform correlated double sampling (CDS) so that the effect of 1/fnoise is also reduced.
• Additional capacitors in the signal path (i.e., C5 and C6) can degrade the closed-loopsettling behavior.
• Reference: Yen, JSSC, 12/82, pp. 1008–1013.
Comparators 18-35 Analog ICs; Jieh-Tsorng Wu
Operational Amplifier with O ffset Compensation
V i
C1
Gm1
Gm2
V o
C2
S1 S3
S4
2
1
1 S5
1
R
S6
S2
• The Gm2 compensation circuit is not in the signal path. The original frequency/speedperformance can be maintained.
Comparators 18-36 Analog ICs; Jieh-Tsorng Wu
Operational Amplifier with O ffset Compensation
During the reset mode (φ1 = 1)
Vo = VOS1 · Gm1R + (VOS2 − Vo) · Gm2R
⇒ Vo =VOS1 · Gm1R + VOS2 · Gm2R
1 + Gm2R⇒ Vo ≈ VOS1 ·
Gm1
Gm2+ VOS2 If Gm2R 1
• VOS1 and VOS2 are the input-referred offset of the Gm1-R and Gm2-R pairs.
During the amplification mode (φ2 = 1)
Vo = Vi · Gm1R + VOS1
Gm1
Gm2+ VOS2 + ∆V · Gm2R = Gm1R
(Vi +
VOS1
Gm2R+
VOS2
Gm1R+ ∆V
Gm2
Gm1
)
Input-Referred Offset = VOS,in =VOS1
Gm2R+
VOS2
Gm1R+ ∆V ·
Gm2
Gm1
• ∆V is due to the mismatch between the switching errors of S5 and S6. Its effect on Vocan be reduced by making Gm2/Gm1 small.
Comparators 18-37 Analog ICs; Jieh-Tsorng Wu
Operational Amplifier with O ffset Compensation
2
VBP2
VBP1
Vi1 V
o1V
VBN2V
1
i2
I VBN1 I
o2
VSS
C1
VDD
C2
M4
M10
M6M5
M8M7
M3
M9
1
1
S2
S1
2
211
S5 S6
M2M1
S3
S4
M11M12
Comparators 18-38 Analog ICs; Jieh-Tsorng Wu
The Chopper Stabilization Technique
11fc
V
f
VOS
iV o
cfc
1f
A
f0 0000
LPF
ff ff
• The bandwidth of the amplifier A must be wider than fc.
• The amplifier A should employ design of minimizing thermal noise.
Comparators 18-39 Analog ICs; Jieh-Tsorng Wu
A Chopper Operational Amplifier
φ
φ
1
iV
I3I
I
o
L
I5
R
I1
φ
φ
V
2R1R
i
φ
V
b
a
4
2
a
a
b
b
2C
1C
VDD
VSS
M7 M8 M9
M5 M6
M4M3
M2M1
Comparators 18-40 Analog ICs; Jieh-Tsorng Wu
A Chopper Operational Amplifier
• The M1–M2 is a low-gain low-noise stage.
• The M3–M4 is a high-gain stage with low Gm. A common-mode feedback circuit isrequired to stabilize the drain voltages of M3 and M4.
• The M5–M8 is a high-gain Miller stage for frequency compensation and low-passfilter.
• The M9 is a low-gain buffer stage.
• The chopper can introduce additional kT/C noise.
• Reference: A. Bakker, et al., “A CMOS Nested-Chopper Instrumentation Amplifierwith 100-nV Offset,” JSSC 12/2000, pp. 1877–1883.
• Reference: C. Enz and G. Temes, “Circuit Techniques for Reducing the Effectsof Op-Amp Imperfections: Autozeroing, Correlated Double Sampling, and ChopperStabilization,” Proc. IEEE, 11/1996, pp. 1584–1614.
Comparators 18-41 Analog ICs; Jieh-Tsorng Wu
Residual O ffset of Chopper Amplifier
Residual Offset
t Spikes at Input
t
VOS
Demodulation Signal
t Demodulated Spikes
t Modulation Signal
cf
VoVi
11
f1
A
LPF
Comparators 18-42 Analog ICs; Jieh-Tsorng Wu
Chopper Modulation with Guard Time
Residual Offset
t Demodulated Spikes
t
VOS
Spikes at Input
t Demodulation Signal
t Modulation Signal
cf
VoVi
11
f1
A
LPF
Comparators 18-43 Analog ICs; Jieh-Tsorng Wu
Chopper Modulation with Guard Time
• The spikes at the input is due to the switching error mismatch of the chopper.
• The residual offset is linear dependent on chopper frequency.
• Reference: Q. Huang and C. Menolfi, “A 200nV Offset 6.5nV/√
• To maintain M1 and M2 in the forward-active region, ISR < Vt1,2.
• For complete switching, want ∆V >√
2Vov ⇒ Vov < ∆V/√
2.
• For enough loop gain, want gmR = [(IS/2)/(Vov/2)] · R >√
2 ⇒ Vov < ∆V/√
2.
• The minimum VDD can be approximated by
VDD,min ≈ Vov5 + Vt + Vov +∆V
2
OSCs 19-8 Analog ICs; Jieh-Tsorng Wu
Delay Variation Using Variable Resistors
Vb Va
ISVct
VRVcb
M1 M2
M4M3
MB1
M5
MB2
VDD MB1=M3=M4 and MB2=M5,
∆V = VDD − VR ≈ ISRon
ωp =1
RonC≈
IS
∆V · CA0 = gm1,2Ron
=∆V
IS
√2µnCox
(W
L
)1,2
IS
=∆V√IS
√2µnCox
(W
L
)1,2
• MB1, M3, and M4 are biased in the triode region.
• A0 decreases at higher oscillation frequencies.
OSCs 19-9 Analog ICs; Jieh-Tsorng Wu
Delay Variation Using Positive Feedback
Vct1 Vct2Vb
Va
1R 2RIT
IS1 IS2VB2VB1VB1 VB2
M1 M2 M3 M4
M5 M6
VDD
IT = IS1 + IS2 ∆V = ITR1,2 ωp =≈ C
G1,2 − gm3,4A0 ≈
gm1,2
G1,2 − gm3,4
gm1,2 =√
2µnCox(W/L)1,2IS1 gm3,4 =√
2µnCox(W/L)3,4IS2
OSCs 19-10 Analog ICs; Jieh-Tsorng Wu
Delay Variation Using Interpolation
3R 4R
Vin1
Vin2
IS
IS2
1R 2R
IS1
VaVb
M5 M6
M3 M4
M1 M2VDD
VDD
IS1 + IS2 = Constant
OSCs 19-11 Analog ICs; Jieh-Tsorng Wu
LC-Tuned Delay Stage
mg
Vo
Vi90o
90o
(−H)
R
ωr
ω
ω
|H|
L C R
VDD
ωr =1√LC
Q = ωrRC =R
ωrL
H(s) =Vo(s)
Vi(s)=
gm
(sL)−1 + sC + 1/R= gmR ·
1Q
(sωr
)(
sωr
)2+ 1
Q
(sωr
)+ 1
OSCs 19-12 Analog ICs; Jieh-Tsorng Wu
LC-Tuned Delay Stage
In the frequency domain
H(jω) = gmR ·1
1 + jQ(
ωωr− ωr
ω
) = gmR · A(jω)
• A(jω) is a band-pass function with −3 dB frequencies at ω1 and ω2, and bandwidthB = ω2 −ω1.
ω1 ·ω2 = ω2r B =
ωr
Q= ω2
rRC =R
L
• If ∆ω = ω −ωr ωr , we have
A(jω) ≈ 1
1 + j2Q · ∆ωωr
OSCs 19-13 Analog ICs; Jieh-Tsorng Wu
LC-Tuned Ring Oscillators
V1 V2 V2V1
L C RL C R
M1 M2
L C RCR L
M2M1
VDDVDD VDD
• Oscillation frequency is ωo = ωr = 1/√LC.
• V1 and V2 are 180 out of phase.
• Need gmR > 1 to start oscillation.
• Varactors, such as pn junctions with reverse bias or MOSTs in the accumulationmode, are used for ωo variation.
OSCs 19-14 Analog ICs; Jieh-Tsorng Wu
Colpitts Oscillator
mg
C1
C2
Vo
V1
C1
C2
Vo
C2 mg
C1 C2C1
Vo
C1
C2
VB
s
N
L C R
L C R1 : N
L C R
VDD
OSCs 19-15 Analog ICs; Jieh-Tsorng Wu
Colpitts Oscillator
• The oscillation frequency is
ωo ≈ ωr =
√1
LCp
Cp = C + (C1 ‖ C2) = C +C1C2
C1 + C2
• The loop gain at ωr is
|T (jωr)| =gm
G + gm
N2
· 1N
=gm
G · N + gmN
Want
|T (jωr)| > 1 ⇒ gmR > N +gmR
N
• If C1 C2, i.e., N ∼ 1, oscillation cannot occur.
OSCs 19-16 Analog ICs; Jieh-Tsorng Wu
One-Port Oscillators
L C G f(V)
I
V
V
I
0
0
1L
∫V dt + C
dV
dt+ G · V + f (V ) = 0 ⇒ LC
dV2
dt+ L
d
dt[G · V + f (V )] + V = 0
• For small-signal analysis, let f (V ) = −a · V with a = − df (V )/dV∣∣V =0. Then, we have
LCs2 + L(G − a)s + 1 = 0
s1, s2 = −(G − a
2C
)± j
√1LC−(G − a
2C
)2
= α ± jβ ⇒ V (t) ≈ Aeα cosβt
Need a > G to start oscillation.
OSCs 19-17 Analog ICs; Jieh-Tsorng Wu
The van der Pol Approximation
Let T = t/√LC, we have
d2V
dT 2+
√L
C· ddT
[F (V )] + V = 0 F (V ) = G · V + f (V )
The van der Pol approximation for F (V ) is
Fv(V ) = −a1 · V + b1 · V 3 a1 = a − G
V max
V x
V x
V
F v (V)
V
±Vx = ±√
a1
b1
V − =
√13·a1
b1
ε =
√L
C· a1 =
√L
C· (a − G)
OSCs 19-18 Analog ICs; Jieh-Tsorng Wu
The van der Pol Approximation
For near-sinusoidal oscillations, ε > 0 and ε→ 0.
v(t) =
√43
a1
b1· 1√
1 + e−(t−t0)ε/√LC
cos(
t√LC
)
• At the start of oscillation, e−(t−t0)ε/√LC 1, we have
V (t) = Aeεt/(2√LC) cos
(t√LC
)= AeεT/2 cos T A =
√43
a1
b1· e−εt0/(2
√LC)
• In steady state, t→∞,
V (t) =
√43
a1
b1cos(
t√LC
)= Vmax cos T
Vmax =
√43
a1
b1=
√43· Vx = 1.15Vx = 2V −
OSCs 19-19 Analog ICs; Jieh-Tsorng Wu
A CMOS SONY Oscillator
VB
Io
Vo
IS
IS
VIMVIM
L C G
2
M1 M2f(V)
V
I
0
VDD
VDD V = Vo − VB
I = Io −IS
2
I = f (V ) =k
4V
√4ISk− V 2 VIM =
√2ISk
k = µCox
(W
L
)1,2
OSCs 19-20 Analog ICs; Jieh-Tsorng Wu
Differential CMOS SONY Oscillators
Io
IS
Io
IS
VoVo
M2M2 M1
2LC/2
G/2
M1
L C G CG L
VDDVDD
V = Vo I = Io I = f (V ) =k
4V
√4ISk− V 2 k = µCox
(W
L
)1,2
OSCs 19-21 Analog ICs; Jieh-Tsorng Wu
Single-Transistor Negative Resistance Generator
Ix
Vx
Cx
Vx
Ix
C1
C2
Ix
xR
Vx =(Ix −−IxsC2· gm
)1
sC1+
Ix
sC2⇒
Vx
Ix=
gm
s2C1C2
+1
sC1+
1sC2
Rx = −gm
ω2C1C2
Cx = C1 ‖ C2 =C1C2
C1 + C2
OSCs 19-22 Analog ICs; Jieh-Tsorng Wu
Single-Transistor Negative-Resistance Oscillators
C2
C1
C2
C1 C1
C2
C2
C1VB C1
C2
C2
VB
C1
C1
C2
L
LL
L
L
L
L
VDD VDD
VDD
OSCs 19-23 Analog ICs; Jieh-Tsorng Wu
Piezoelectric Crystals
Co
ωaωs
Circuit Model
R C Lω
+jX
−jX
0
Z(jω) =[R + (jωC)−1 + jωL](jωCo)−1
R + (jωC)−1 + jωL + (jωCo)−1
ωs =1√LC
ωa =1√
L(C‖Co)
ωa
ωs
=
√1 +
C
Co
Q =1
ωsRC=
ωsL
R
OSCs 19-24 Analog ICs; Jieh-Tsorng Wu
Piezoelectric Crystals
• Example: R = 16.3 Ω, C = 0.009 pF, L = 7.036 nH, Co = 2.3 pF; thus fo = 20 MHz,Q = 54245.
• The serial RLC can be transformed into a parallel circuit
Rp = R(1 +Q2
s
)Xp = Xs
(1 +
1
Q2s
)where Xs = ωL − 1
ωCQs =
Xs
R
At ω = ωa, with Qs 1, we have
Xp =1
ωaCo
Rp ≈X
2s
R≈
X2p
R=
1
R(ωaCo)2
• Circuits containing crystals are designed so that the frequency range of interest isbetween ωs and ωa.
OSCs 19-25 Analog ICs; Jieh-Tsorng Wu
Crystal Oscillators
C2
VB
C1
C1
C2
C2
C1
VB
Colpitts Oscillator
LLVDD
VDD
C1C2
VDD
Pierce Oscillator
OSCs 19-26 Analog ICs; Jieh-Tsorng Wu
Relaxation Oscillators (Multivibrators)
TbTa
Tba
Tab
State BState A fo =1
Ta + Tb + Tab + Tba
fo,max ≈1
Tab + Tba
• The two states are created by positive feedback.
• Ta and Tb are usually determined by the charging and discharging of timing capacitors,while Tab and Tba are the transient response of the circuit.
• Comparing with the frequency-tuned oscillators, the relaxation oscillators have widertuning range, predictable waveforms, but poorer spectral purity.
OSCs 19-27 Analog ICs; Jieh-Tsorng Wu
Constant-Current Charge/Discharge Oscillators
VA
VBT1 T2
Vo
VA
VBVo
I1
I2
R
SQ
D x
Schmitt Trigger
D
DC
VDD
T1 =C · (VA − VB)
I1T2 =
C · (VA − VB)
I2 − I1
fo =1
T1 + T2=
I1
C · (VA − VB)
(1 −
I1
I2
)
OSCs 19-28 Analog ICs; Jieh-Tsorng Wu
The Banu Oscillator
IB
Vx Vy
Va
Vb
Vx
Vy
Va
VDD
Vth
Vb
CC
VDD
• Oscillation frequency is fo = 1/(2T ) where T = C · (VDD − Vth)/IB.
• Reference: Banu, M., “MOS Oscillators with Multi-Decade Tuning Range and GHzMaximum Speed,” JSSC, 12/1998, pp. 1386–1393.
The relationship between the filter order, N, and the steepness of the magnituderesponse is
N ≥logδ − logε
logωs
• Good flatness in passband.
• Poor phase linearity.
• Moderate attenuation slope steepness.
Filters 20-19 Analog ICs; Jieh-Tsorng Wu
Equi-Ripple (Chebyshev) Filters
1
1
N=3
N=4
1
1
Chebyshev Inverse Chebyshev
ωωωsωs
|H1(jω)|2 |H2(jω)|2
1/(1 + ε2)
1/(1 + δ2)
Chebyshev = |H1(jω)|2 =1
1 + ε2C2N
(ω)
Inverse Chebyshev = |H2(jω)|2 =ε
2C
2N(1/ω)
1 + ε2C2N
(1/ω)
Filters 20-20 Analog ICs; Jieh-Tsorng Wu
Equi-Ripple (Chebyshev) Filters
The function CN is
CN(ω) = cos[N cos−1(ω)] for ω ≤ 1
= cosh[N cosh−1(ω)] for ω > 1
= 2ωCN−1(ω) − CN−2(ω)
The relationship between the filter order, N, and the steepness of the magnituderesponse is
N ≥cosh−1(δ/ε)
cosh−1 ωs
≈ln(2δ/ε)
ln(ωs +
√ω2
s − 1)
• Good steepness of the attenuation slope.
• Poorer phase linearity and passband flatness than the Butterworth filters.
• Inverse Chebyshev filters have better phase and delay performance.
Filters 20-21 Analog ICs; Jieh-Tsorng Wu
Elliptic (Cauer) Filters
1
1ω
ωs
|H(jω)|2
1/(1 + ε2)
1/(1 + δ2)
|H(jω)|2 =1
1 + ε2R2N
(ω)
Filters 20-22 Analog ICs; Jieh-Tsorng Wu
Elliptic (Cauer) Filters
The function RN is
RN(ω) = k
N/2∏i=1
ω2 − (ωs/ωzi)
2
ω2 −ω2zi
for N even
= kω
(N−1)/2∏i=1
ω2 − (ωs/ωzi)
2
ω2 −ω2zi
for N odd
In the stopband, if ε2R
2N(ω) 1,
20 logδ
ε≈ 20 log |RN(ωs)|
• Best steepness of the attenuation slope.
• Poor phase linearity.
Filters 20-23 Analog ICs; Jieh-Tsorng Wu
Comparison of the Classical Filter Responses
Comparing filters that satisfy the same δ and ε requirements:
• The Cauer filter has the lowest order, while the Butterworth filter has the highest order.
• The Butterworth filter has the best passband performance, and the inverseChebyshev filter is a close second.
• The Cauer filter has the largest pole quality factor; next is the Chebyshev filter,followed by the inverse Chebyshev and the Butterworth filters.
• The Chebyshev filter has the worst group delay variation; next is the inverseChebyshev filter, followed by the Butterworth and the Cauer filters.
• The Butterworth and the Chebyshev are all-pole filter, while the inverse Chebyshevand Cauer filters have finite transmission zeros.
• The inverse Chebyshev filters have low order, modest Q values, good delayperformance, and minimal passband attenuation, making them most attractive.
Filters 20-24 Analog ICs; Jieh-Tsorng Wu
Linear-Phase (Bessel-Thomson) Filters
1
1ω
ωs
|H(jω)|2
1/(1 + ε2)
1/(1 + δ2)
H(s) =bo
D(s)D(s) =
N∑i=0
bisi bi =
(2N − i )!
2N−i i !(N − i )!i = 0,1, · · · , N − 1
D(s) is related to Bessel polynomials.
D(s) = (2N − 1)DN−1 + s2DN−2
Filters 20-25 Analog ICs; Jieh-Tsorng Wu
Linear-Phase (Bessel or Thomson) Filters
• Approximate the linear-phase response.
• Poor steepness of the attenuation slope.
• It is usually more efficient to use a Butterworth, Chebyshev or a Cauer filter cascadedwith an all-pass filter to achieve required gain and linear-phase response.
Filters 20-26 Analog ICs; Jieh-Tsorng Wu
All-Pass Filter (Delay Equalizer) Specifications
1
PB
|H(jω)| (dB)
ωωcL ωcH
jω
σ
H(jω) = |H(jω)|ejφ(ω)
Group Delay = τ(ω) = −dφ(ω)
dω
Filters 20-27 Analog ICs; Jieh-Tsorng Wu
Frequency Transformations
Low-Pass to High-Pass Transformation
HHP(s) = HLP
(1s
)
• For RC active filters, it is an RC-CR transformation.
Low-Pass to Band-Pass Transformation
HBP(s) = HLP
(Q · s
2 + 1s
)
• Q = ωo/B is the quality factor, where ωo is the center frequency, B = ωcH − ωcL isthe passband bandwidth.
• Transformation always results in symmetrical band-pass filters.
Filters 20-28 Analog ICs; Jieh-Tsorng Wu
Frequency Transformations
Low-Pass to Band-Reject Transformation
HBR(s) = HLP
(1Q· s
s2 + 1
)
• Q = ωo/B is the quality factor, where ωo is the center frequency, B = ωsH −ωsL is thepassband bandwidth.
• Transformation always results in symmetrical band-reject filters.
Frequency ScalingH ′(s) = H(
s
a)
• So that ω′c = a ·ωc, ω′s = a ·ωs, ω′o = a ·ωo
Filters 20-29 Analog ICs; Jieh-Tsorng Wu
High-Order Filters
H1 H2 H3 H4
H1 H2 H4H3
H2H1 H3 H4
In Out
Cascade Topology
Follow-the-Leader Feedback (FLF) Topology
F1 F2 F3 F4
In Out
In Out
F2 F4
F3 F5
H5
Leapfrog (LF) Topology
Filters 20-30 Analog ICs; Jieh-Tsorng Wu
High-Order Filters
Cascade Topology:H(s) = H1 · H2 · H3 · H4
Follow-the-Leader Feedback (FLF) Topology:
H(s) =H1H2H3H4
1 + F1H1 + F2H1H2 + F3H1H2H3 + F4H1H2H3H4
Leapfrog Topology:
H(s) =H1H2H3H4H5
D(s)
D(s) = 1 + F2H1H2 + F3H2H3 + F4H4H4 + F5H4H5
+F2F4H1H2H3H4 + F2F5H1H2H4H5 + F3F5H2H3H4H5
Filters 20-31 Analog ICs; Jieh-Tsorng Wu
LC Ladder Filters
RS
RS
V 1
V S
V S
RL
V 2
RL
V 2V 1
I 1
A Fifth-Order Elliptic Low-Pass Filter
Lossless LC Network
Y2
Z3
Y4
Z(n-2)
Y(n-1)
Z(n)Z1
Filters 20-32 Analog ICs; Jieh-Tsorng Wu
LC Ladder Filters
When designed for maximum power transfer, the LC ladder filters are inherentlyinsensitive to component variations, particularly in their passband.
Input Power = P1 = |I1(jω)|2ReZin(jω) =|VS |
2
|RS + Zin(jω)|2ReZin(jω)
Maximum Input Power = P1,max =14
|VS |2
RS
Output Power = P2 =|V2|
2
RL
H(s) =
√4RS
RL
·V2
VS=
N(s)
D(s)|H(jω)|2 =
4RS
RL
·∣∣∣∣V2
VS
∣∣∣∣2
≤ 1
|H(jω)|2 = 1 −∣∣∣∣RS − Zin(jω)
RS + Zin(jω)
∣∣∣∣2
= 1 − |ρ(jω)|2 ρ(s) = ±RS − Zin(s)
(RS + Zin(s))
• ρ(s) is the reflection coefficient.
Filters 20-33 Analog ICs; Jieh-Tsorng Wu
Sensitivity
Let P is a function of x. The sensitivity of P with respect to x is defined as:
SPx =
∂P/P
dx/x=
x
P· ∂P∂x
=∂(ln P )
∂(lnx)
The semirelative sensitivity is defined as
QPx =
∂P
∂x/x= x · ∂P
∂x
• Some useful relationships:
SP1P2x = S
P1x + S
P2x S
P1/P2x = S
P1x − S
P2x SP
x = SPy · S
yx
Filters 20-34 Analog ICs; Jieh-Tsorng Wu
Sensitivity
• Let Y is a function of x1, x2, · · · , xn.
dY =∂Y
∂x1· dx1 +
∂Y
∂x2· dx2 + · · · +
∂Y
∂xn
· dxn
d Y
Y= SY
x1·dx1
x1+ SY
x2·dx2
x2+ · · · + SY
xn·dxn
xn
• Let the forward gain T = T1 · T2, we have
STT2=
T2
T· ∂T∂T2
= 1
With negative feedback factor H , we have
T =T1T2
1 + HT1T2⇒ ST
T2=
T2
T· ∂T∂T2
=1
1 + HT1T2
The T sensitivity is reduced by the loop gain HT1T2
• Any pole or zero shift influences H(s) most strongly in the neighborhood of that poleor zero.
• SHx →∞ at a jω-axis transmission zero zi = jωzi
.
• For frequencies s = jω in the neighborhood of pole with large quality factor, highsensitivities are expected.
• Sensitivities are normally largest at the passband corner.
Filters 20-37 Analog ICs; Jieh-Tsorng Wu
Second-Order Filter Sensitivity
The Biquadratic function is
H(s) =N(s)
D(s)=
a2(s − z1)(s − z2)
(s − p1)(s − p2)=
a2s2 + a1s + a0
s2 + (ωp/Qp)s +ω2p
p1 = −ωp
(1
2Qp
− j
√1 − 1
4Q2p
)p2 = p∗1 = −ωp
(1
2Qp
+ j
√1 − 1
4Q2p
)
The sensitivity of the poles are
Sp1x = S
ωp
x − jS
Qp
x√4Q2
p − 1S
p2x =
(S
p1x
)∗= S
ωp
x + jS
Qp
x√4Q2
p − 1
• The pole is√
4Q2p − 1 ≈ 2Qp times more sensitive to variations in ωp than to variations
in Qp.
Filters 20-38 Analog ICs; Jieh-Tsorng Wu
Second-Order Filter Sensitivity
The transfer function can be expressed as H(jω) = |H(jω)|ejθ(ω), then
SH(jω)x =
∂ lnH(jω)
∂ lnx=
∂ ln |H(jω)|∂ lnx
+ jx∂θ(ω)
∂x= S
|H(jω)|x + jθ(ω)Sθ(ω)
x
Consider only the effects of poles on the passband of H(s)
SH(s)x = − x
D(s)
∂D(s)
∂x= −
(sωp
Qp+ 2ω2
p
)S
ωp
x −sωp
QpS
Qp
x
s2 + (ωp/Qp)s +ω2p
= −
(snQp
+ 2)S
ωp
x −snQpS
Qp
x
s2n + sn/Qp + 1
SH(jω)x = −
[(ωn
Qp
)2+ 2(
1 −ω2n
)]S
ωp
x −(ωn
Qp
)2S
Qp
x
(1 −ω2
n
)2+(ωn/Qp
)2+ j
ωn
Qp
(1 +ω
2n
)S
ωp
x +(
1 −ω2n
)S
Qp
x(1 −ω2
n
)2+(ωn/Qp
)2
sn =s
ωp
ωn =ω
ωp
Filters 20-39 Analog ICs; Jieh-Tsorng Wu
Second-Order Filter Sensitivity
We have
S|H(jω)|x = −
2(
1 −ω2n
)2+(ωn/Qp
)2
(1 −ω2
n
)2+(ωn/Qp
)2· Sωp
x +
(ωn/Qp
)2
(1 −ω2
n
)2+(ωn/Qp
)2· SQp
x
θ(ω)Sθ(ω)x = x
∂θ(ω)
∂x=
(1 +ω
2n
)2 (ωn/Qp
)(1 −ω2
n
)2+(ωn/Qp
)2· Sωp
x +
(1 −ω
2n
)2 (ωn/Qp
)(1 −ω2
n
)2+(ωn/Qp
)2· SQp
x
And
S|H(jω)|x = S
|H |ωp· Sωp
x + S|H |Qp· SQp
x
⇒ S|H |ωp
= −2(
1 −ω2n
)2+(ωn/Qp
)2
(1 −ω2
n
)2+(ωn/Qp
)2S|H |Qp
=
(ωn/Qp
)2
(1 −ω2
n
)2+(ωn/Qp
)2
Filters 20-40 Analog ICs; Jieh-Tsorng Wu
Second-Order Filter Sensitivity
S|H |ωp
S|H |Qp
maxS |H |ωp ≈
Qp
1 + 1/Qp
at ωn ≈ 1 +1
2Qp
minS |H |ωp ≈ −
Qp
1 − 1/Qp
at ωn ≈ 1 − 12Qp
maxS |H |Qp = 1 at ωn = 1
Filters 20-41 Analog ICs; Jieh-Tsorng Wu
Second-Order Filter Sensitivity
• Small variations of ωp are far more important than small change in Qp.
• Since the errors increase with Q, low-Q filters are easier to design with less accuratecomponents than high-Q filters.
• Sensitivities are strong functions of frequency, and the passband edges are verycritical.
Filters 20-42 Analog ICs; Jieh-Tsorng Wu
High-Order Filter Sensitivity
A 6th-order Butterworth bandpass filter
• For cascade design,
H(s) = H1(s)H2(s) · · ·Hn(s)
SH(s)Hj (s) = 1 and S
H(s)x = S
Hj (s)x
The sensitivity of H(s) to x is as large assensitivity of sub-block Hj(s) to x.
• Feedback paths around low-order sectionsin a multiple-feedback (MF) filter topologycan reduce sensitivities in the passband.In the stopbands, where feedback pathslose their effectiveness, MF and cascadesensitivities are approximately the same.
Filters 20-43 Analog ICs; Jieh-Tsorng Wu
Active-RC Filters
Jieh-Tsorng Wu
October 17, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Capacitor Integrators
oV
R CI
Vo
I=
1jωC + G
=1
jωC[1 − j G
ωC
] = 1
jωC[1 − j 1
QI (ω)
]QI(ω) =
ωC
G
The transfer function of an integrator can be expressed as
ID = IL − IN IL = k(VG0 − VT ) × VDS = G × VDS IN = k[g(VD0) − g(VS0)
]• Both ge and go are independent of VG.
• go(VD0) − go(VS0) is very small comparing to IL (e.g., 0.1 percent of it or less).
• ge(VD0) − ge(VS0) can be large and its effect must be eliminated to obtain a linearresistor.
• If only IL is considered, the resistance between VD and VS is
G =ID
VDS
= k(VG0 − VT ) = µCox
W
L(VG0 − VT )
Gm-C Filters 22-4 Analog ICs; Jieh-Tsorng Wu
MOST-C Fully-Balanced Integrators
G
o2V
o1V
V
GV
0Vi2V
i1Vi VV o
I1
I2
C
R
C
C
M2
M1
Vi1 = +Vi
2+ V0 Vi2 = −
Vi
2+ V0 Vo1 = +
Vo
2+ V0 Vo2 = −
Vo
2+ V0
I1 = G ×(+Vi
2
)−[ge
(+Vi
2
)− ge (0)
]−[go
(+Vi
2
)− go (0)
]
I2 = G ×(−Vi
2
)−[ge
(−Vi
2
)− ge (0)
]−[go
(−Vi
2
)− go (0)
]
I1 − I2 = G × Vi − 2go
(Vi
2
)≈ G × Vi G = k(VG − V0 − VT )
Gm-C Filters 22-5 Analog ICs; Jieh-Tsorng Wu
MOST-C Fully-Balanced Integrators
Therefore
Vo(s)
Vi(s)=
I1(s) − I2(s)
Vi(s)·(− 1sC
)= − G
sC
• Even-order nonlinearities are eliminated.
• The common-mode voltage along the differential signal path must be maintained atV0.
• Linearities around 50 dB have been achieved.
Gm-C Filters 22-6 Analog ICs; Jieh-Tsorng Wu
Double MOST-C Differential Integrators
V
V
GBV
GBV
GA
GA
o1V
i2V
i1V
Vo2
I1
I2
C
C
M1
M2
M3
M4
Vi1 = +Vi
2+ V0
Vi2 = −Vi
2+ V0
Vo1 = +Vo
2+ V0
Vo2 = −Vo
2+ V0
GA = k1,2 (VGA − V0 − VT )
GB = k3,4 (VGB − V0 − VT )
I1 = GA ×(+Vi
2
)−[g
(+Vi
2
)− g (0)
]+ GB ×
(−Vi
2
)−[g
(−Vi
2
)− g (0)
]
I2 = GA ×(−Vi
2
)−[g
(−Vi
2
)− g (0)
]+ GB ×
(+Vi
2
)−[g
(+Vi
2
)− g (0)
]
Gm-C Filters 22-7 Analog ICs; Jieh-Tsorng Wu
Double MOST-C Differential Integrators
We have
I1 − I2 = (GA − GB) × ViVo(s)
Vi(s)=
I1(s) − I2(s)
Vi(s)·(− 1sC
)= −
GA − GB
sC
• Both even-order and odd-order nonlinearities are eliminated.
• Differential signals are not required to be fully balanced.
• Around 10 dB linearity improvement over the two-transistor MOST-C integrators.
• Linearity performance is limited by the deviation of the above device model andmismatches among the MOSTs.
• Reference: Ismail, JSSC 2/88, pp. 183–194.
Gm-C Filters 22-8 Analog ICs; Jieh-Tsorng Wu
R-MOST-C Differential Integrators
V i1
V i2
R1
R2
R2
R1
V
V
V
V
M1
M2
CA
CB
CB
CA
M3
M4
C
C
V
V
o1
o2
Gm-C Filters 22-9 Analog ICs; Jieh-Tsorng Wu
R-MOST-C Differential Integrators
Vo
Vi= −
R2/R1
sC[R2
(1 + RM1
R1‖R2‖RM2
)]+ 1
• The dc gain is not adjustable.
• The integrator’s time constant can be varied by changing RM1 and RM2
• At low-frequencies, the linear resistors, R1 and R2, dominate the transfer function,thus reducing distortion. A linearity of 90 dB has been achieved.
• In the criss-cross version, M3 and M4 reduce the effective dc gain and bandwidthof the integrator, enhance the unity-gain frequency sensitivity to componentmismatches, and increase noises.
• Reference: U-K Moon, et al., JSSC 12/93, pp. 1254–1264.
Gm-C Filters 22-10 Analog ICs; Jieh-Tsorng Wu
A MOST-C Tow-Thomas Biquad
R/K
GVGV
GV
GV
GV
MR/K
MRQ
MRQ
MR
MR
MR
MR
bV lViV
GV
GV
VG
M
C
C
C
C
Gm-C Filters 22-11 Analog ICs; Jieh-Tsorng Wu
Transconductors
I
go
o
g
oI
oIoI
iViViV
i
Io
oVi Vi V
oIo I
Ci
iC
Ideal Model Nonideal Model
mG
mG
Io = Gm × Vi
Gm-C Filters 22-12 Analog ICs; Jieh-Tsorng Wu
Transconductor Basic Circuits
iZ
V
i
iZ
i
Voltage Amplifier
Vi1
Vi2
Vo
Lossless IntegratorControlled Resistance
V
iV
o
VoVi1
Vi2
V oV
o
V
C
G
CG
2C
2C
m1G
m1
m1G
m1G
m1
m2
m3G
G
G
m1
m3m1
m2
G
G
G
Zi =1
Gm1Vo =
1Gm3· (Gm1Vi1 − Gm2Vi2)
Vo(s)
Vi(s)= −
Gm
sC
Gm-C Filters 22-13 Analog ICs; Jieh-Tsorng Wu
Gm-C Lossy Integrator
i oV
i
Vi
VoVoV
Vo
V Vi
C
C
m1G
= m2m1G G
m1
m2G
G
m2C
m1GG
m2m1 CG G
Vo(s)
Vi(s)= −
Gm1
sC + Gm2
• Since no feedback for the integrators, they can be wide-band.
• A transconductor’s output current should be linearly related to the input over the entireinput voltage range.
Gm-C Filters 22-14 Analog ICs; Jieh-Tsorng Wu
Fully-Differential Gm-C Integrators
oVVo iV
2C
Vi Vi
2C
Vo
Cp
p
mG
Cp
Cp
mG
CC
mG
C
Vo(s)
Vi(s)= −
Gm
s(C + Cp/2)
• Can use only grounded capacitors.
• The Cp can affect the integration time constant.
• Partially nonlinear Cp can also cause linearity problems.
Gm-C Filters 22-15 Analog ICs; Jieh-Tsorng Wu
Gm-C Opamp Integrators (Miller Integrators)
o
I
I oI
oV
V
o
BiV
oo
BVV
I
Cp
pC
VDD
VSS
VDD
VSS
mG
2C
2C
2C 2C
Vo(s)
Vi(s)= −
Gm
sC
• The effects of parasitic capacitances are reduced.
• The Gm’s output stage can be simplified, since no large voltage swing is required.
• The lower impedances at the Gm’s output nodes make those nodes less sensitive tocapacitive coupling of noise.
Gm-C Filters 22-16 Analog ICs; Jieh-Tsorng Wu
Gyrators
2
L
1L
1 II
VGm2Gm1 2V2V1V
I2
V1 V2
1
1
V2V1
I1V
2
V1
V1 V2
C
Floating Inductor
Grounded Inductor
C
Modelm2 m1G G
m2 m1 m1 m2G G G G
L1 =C
Gm1 · Gm2L2 =
C
Gm1 · Gm2
Gm-C Filters 22-17 Analog ICs; Jieh-Tsorng Wu
Gm-C Simulated Gyrators
V1 V2
Gyrator
V1
1
V1
V1V
Simulated Floating Inductor
Simulated Grounded Inductor
2
V1 V2
V
V
2
m1m2G G m1m2C
GG
m1m2G G m1m2 CGG
m1m2 m1 m2C
G G G G
m1m2 m1 m2CG G G G
Gm-C Filters 22-18 Analog ICs; Jieh-Tsorng Wu
MOST Transconductors
o2
i2
Io1I Io1o2
i2Vi1Vi1V
I
V
VSSVSS
11
1/2 1/2
0.85 I 0.15 ITuningTuning
Gm-C Filters 22-19 Analog ICs; Jieh-Tsorng Wu
MOST Transconductors
Adaptive Source Degeneration
Bias
/
mo
Vi2V
IiVG /
mo GmG
i1
Io1 Io2
VSS
Tuning
0
1
1-1
Bias Offset Linearization
o1I o2I
i2Vi1V
V BV B
VSS
M1 M2
M3 M4
Let M1=M2=M3=M4,
ID =12k (VGS − VT )2
Io1 = Io2 = kVB (Vi1 − Vi2)
Gm-C Filters 22-20 Analog ICs; Jieh-Tsorng Wu
MOST Transconductors with Source Degeneration
I
o2Io1I
CV
i1V’ i2V’
V i2V
a I
a
Vi1 Vi2
V’i1 V’i2
V’i1 V’i2
b
I
o2I
i1
Io1
VSSVSS
V
V
CA
CB
Double-MOST TypeFully Balanced Type
M1 M2
MA
M3 M4M2M1
MB
MA
Gm-C Filters 22-21 Analog ICs; Jieh-Tsorng Wu
MOST Transconductors with Source Degeneration
Let
V ′i1 = +
Vi
2+ V0 V ′
i2 = −Vi
2+ V0 G = k(VC − V0 − Vt)
For the fully balanced differential transconductor
Ia = G × Vi −[ge
(+Vi
2
)− ge
(−Vi
2
)]−[go
(+Vi
2
)− go
(−Vi
2
)]
Io1 − Io2 = 2Ia ≈ 2G × Vi − 2go
(+Vi
2
)≈ 2G × Vi
For the double-MOSFET differential transconductor
Ia = GA × Vi −[g
(+Vi
2
)− g
(−Vi
2
)]Ib = GB × Vi −
[g
(+Vi
2
)− g
(−Vi
2
)]Io1 − Io2 = 2(Ia − Ib) = 2(GA − GB) × Vi
Gm-C Filters 22-22 Analog ICs; Jieh-Tsorng Wu
BJT Transconductors
V
I
OSV
I
Vi1 Vi2
Io1 Io2
o2o1I
o2Io1
OS
i2V
OS
i1
V
Vi1 Vi2
Multi-tanh Doublet
V
VEE
VEEVEE VEE
V i
g m
Q1 Q2
R
Q1Q3
4x 4x1x 1x
Q2Q4
Q2Q1
Total
Q2-Q4
Q1-Q3
VOS = kTq
ln IS1IS2
Gm-C Filters 22-23 Analog ICs; Jieh-Tsorng Wu
Multi-Input Transconductors
V
oB2
o
V
B1Va
Vb
Io
I
B3VVa Vb
Io
Io
Vo
V
V
B4
M8
M10
M7
M9
VSS
mb
ma mb
G
G
G
M4
M6
M3
M5
VDD
G
ma
Io = Gma · Va + Gmb · Vb
• Need only one output common-mode feedback.
• Reference: Edited by Y.P. Tsividis and J.O. Voorman, “Integrated Continuous-TimeFilters”, IEEE Press, 1993.
Gm-C Filters 22-24 Analog ICs; Jieh-Tsorng Wu
Transconductor’s Imperfections
g oo
oV
oI
iV ViV
g
Voi
Ci iC C
Nonideal Model
m1G
C
Io = Gm(s) × Vi Gm(jω) =Gm
1 + jω/ω2
≈ Gme−jφ φ = tan−1 ω
ω2
For the Gm-C integrator
Vo
Vi=
Gm
1 + s/ω2
× 1sC + go
=Gm
sC(
1 + ωo
ω2
)+ go
(1 + s2
ωoω2
) ωo =go
C
Gm-C Filters 22-25 Analog ICs; Jieh-Tsorng Wu
The Effect of Non-Zero go on Gyrators
V
Vgo
i
Vi
og
1L
og
iRs
mG
mG
mGmG C
C
L =C
G2m
Rs =go
G2m
Gm-C Filters 22-26 Analog ICs; Jieh-Tsorng Wu
The Effect of Phase Shift on Gyrators
V
iL
Vi
1i
V
G
mG
m
pRmGmG C
C
If
Gm(jω) = Gme−jφ φ = tan−1
(ω
ω2
)≈ ω
ω2 1
We have
L =C
G2m
1Rp
≈ −2G2
m
ωC·φ ≈ −
2G2m
ω2C= − 2
ω2L
Gm-C Filters 22-27 Analog ICs; Jieh-Tsorng Wu
Gm-C First-Order Filters
i2o
V
1sτVi Vo
=
= =
VoVi1
Vi2
Vi1 Vm1
C
Gm3G
Gm1 Gm2Gm4Gm3 Gm5
1
m2C m3
m4
m5G
G
G
GGm1
α1s + α0
H(s) = −(
Gm1Vi1
sC + Gm2· Gm3 + Gm4Vi2
)· 1Gm5
= −sCGm4Vi2 + (Gm1Gm3Vi1 + Gm2Gm4Vi2)
(sC + Gm2) · Gm5
• The output requires another buffer to prevent loading effects.
• If C2Gm1Gm3 = C1Gm2Gm4, it is a band-reject biquad.
• If C1Gm2Gm4 = 2C2Gm1Gm3 and Gm4 = Gm5, it is an allpass biquad.
• There is one parasitic pole in the biquad.
Gm-C Filters 22-31 Analog ICs; Jieh-Tsorng Wu
Gm-C First-Oder Filters Using Miller Integrators
ViV
1sτVi Vo
iV o
o
V
Gm2
2CX
2C
CA
CX
m2GX
1
Gm1
2C
2CA
A
m1G
α1s + α0
Gm-C Filters 22-32 Analog ICs; Jieh-Tsorng Wu
Gm-C First-Oder Filters Using Miller Integrators
Without the Miller Integrator
Vo
Vi=
α1s + α0
s +ωo
=s(
CX
CA+CX
)+(
Gm1CA+CX
)s +(
Gm2CA+CX
)Gm1 = α0(CA + CX ) Gm2 = ωo(CA + CX ) CX = CA
α1
1 − α1where 0 ≤ α1 < 1
With the Miller Integrator
Vo
Vi=
α1s + α0
s +ωo
=s(CX
CA
)+(Gm1CA
)s +(Gm2CA
)
• The use of feed-in capacitors can simplify design, but requires inputs of low sourceimpedance.
Gm-C Filters 22-33 Analog ICs; Jieh-Tsorng Wu
Gm-C Second-Oder Filters Using Miller Integrators
s1Vi
1sτ Vo
iVi
1
oV
τ
V
2CA
2CA 2CB
2C
Gm3Gm4
2CX
2CX
B
1/Q
Gm1 Gm2
Gm5
α0
α1 + α2s
Gm-C Filters 22-34 Analog ICs; Jieh-Tsorng Wu
Gm-C Second-Oder Filters Using Miller Integrators
The transfer function is
Vo
Vi=
α2s2 + α1s + αo
s2 +(ωp
Q
)+ω2
p
=s
2(CX
CB
)+ s(Gm5CB
)+(Gm2Gm4CACB
)s2 + s
(Gm3CB
)+(Gm1Gm2CACB
)
ThusCX = α2CB
and
Gm1 = ωpCA Gm2 = ωpCB Gm3 =ωpCB
QGm4 =
α0CA
ωp
Gm5 = α1CB
Gm-C Filters 22-35 Analog ICs; Jieh-Tsorng Wu
Ladder Filter Using Simulated Gyrators
C2
o
iV
iV
V
C2
V
V
i
C2
o
V
o
C2
RS RLC1L2
C3
m2m2
C1 C3
mi mS mLG G G m1 m1G G G G
C
m1 m1 m2
C3C1
mimLm2mS
GG G G G G G
C
Single-Ended Implementation
Fully Differential Implementation
Gm-C Filters 22-36 Analog ICs; Jieh-Tsorng Wu
Ladder Filter Using Simulated Gyrators
• Inductors are replaced with Gm-C gyrators.
• Floating capacitors are required.
• Finite go of the transconductors results in lossy inductors and capacitor, i.e., Qdegradation; while phase shift causes Q enhancement.
• The Q-control automatic tuning circuits may be required.
Gm-C Filters 22-37 Analog ICs; Jieh-Tsorng Wu
Ladder Filter Using Signal-Flow Graph
RL
V 1
RSV in
V 2V 0
V 1
V 4
V 5V 3
V in V out
I 0 I 2 I 4 V 5V 3
GmS
V 0
V 1
V 2 V 4 V 6
V outV 5V 3V in
GmL
C1L2
C3 C5L4
I 6
1/(sL L
V 6
S1/R 1/(sL2) -1/(sC 3) 4) -1/(sC 5) 1/R-1/(sC )1
V out
C1 C2 C3 C4 C5
Gm-C Filters 22-38 Analog ICs; Jieh-Tsorng Wu
Ladder Filter Using Signal-Flow Graph
• Floating capacitors are not necessary.
• Finite go of the transconductors results in lossy inductors and capacitor, i.e., Qdegradation; while phase shift causes Q enhancement.
• Signal-level scaling is possible.
Gm-C Filters 22-39 Analog ICs; Jieh-Tsorng Wu
Gm-C Simulation of Ladder Branches (I)
Shunt Branch
1I 3I
C4
L
V
1V1V
C10R
L4 V
3
Series Branch
2
L
3
C1
V1 V3
I2
L C3
2
2
0R
C1
mi1
mi2m0
C3 C4
C2
G
GG
Gm-C Filters 22-40 Analog ICs; Jieh-Tsorng Wu
Gm-C Simulation of Ladder Branches (II)
V
1V1V
3
C3
mi1
mi2m0
C1
C4
C2
G
GG
Gm-C Filters 22-41 Analog ICs; Jieh-Tsorng Wu
Gm-C Simulation of Ladder Branches
The branch characteristics are
I2 = (V1 − V3) · Y (s) = (V1 − V3) · 1
R0 + sL1 +1
sC2+ 1
sC3+1
sL4
V2 = (I1 − I3) · Z(s) = (I1 − I3) · 1
G0 + sC1 +1
sL2+ 1
sL3+1
sC4
The Gm-C circuit’s transfer function is
V2 = (Gmi1 · V1 − Gmi2 · V3) · 1
Gm0 + sC1 +1
sC2+ 1
sC3+1
sC4
• Method 2 usually uses more transconductors than method 1, but may haveadvantages in terms of sensitivity to and compensation for parasitic effects.
• For better matching, use identical transconductors whenever possible.
Gm-C Filters 22-42 Analog ICs; Jieh-Tsorng Wu
Gm-C Resonators
V o
V i
V o
I i
C1
C2
m2 m3
m4
C1 RL
m1G
G G
G
Gm-C Filters 22-43 Analog ICs; Jieh-Tsorng Wu
Gm-C Resonators
• The inductor L is simulated by Gm2, Gm3, and C2. The resistor R is simulated by Gm4.
• The resonant frequency and the quality factor are
ωo =
√1
LC1=
√Gm2Gm3
C1C2Q = ωoRC1 =
√C1
C2×
√√√√Gm2Gm3
G2m4
The voltage gain at the resonant frequency is
Avo =vo
vi= Gm1R =
Gm1
Gm4
• Reference: Silva-Martinez, et al., JSSC 12/92, pp. 1843–1853.
Gm-C Filters 22-44 Analog ICs; Jieh-Tsorng Wu
Gm-C Quadrature Oscillators
1CGGL D
2C
V oV o
m2
m3 m4
m1GG
G G
I
V
L C
• The combination of Gm1, Gm2 and C1 simulates an inductor.
• The oscillation frequency is ωo =√Gm1Gm2/(C1C2).
• The oscillation condition is Gm4 = Gm3. In many cases, Gm3 and Gm4 are not required.
• The nonlinear resistor is used to control the output amplitude.
• Reference: Rodriguez-Vazquez, Transactions on Circuits and Systems, 2/90,pp. 198–211.
Gm-C Filters 22-45 Analog ICs; Jieh-Tsorng Wu
On-Chip Tuning Strategies
Direct Tuning
Indirect Tuning
LPF
S outS in
ref
LPF
S
cntrlU
S in
cntrl
S out
S ref
Filter to be Tuned (Slave)
Reference Circuit (Master)
Control Circuit
Filter B to be Tuned
Control Circuit
Filter A to be Tuned
U
Gm-C Filters 22-46 Analog ICs; Jieh-Tsorng Wu
Separate Frequency and Q Control
LPF
Ref Ckt 2
Control Ckt Control Ckt LPF
S in S out
S rf S rQ
Filter to be Tuned
QF
Ref Ckt 1
UU
Freq Tuning Loop Q Tuning Loop
Gm-C Filters 22-47 Analog ICs; Jieh-Tsorng Wu
Gm Tuning
R
CV
C
V
RV
Rext
1C
CVR
1
V
mG
Rext
Gm
• VC is automatically adjusted so that
Gm =1
Rext
• C1 is an integrating capacitor used to maintain loop stability.
Gm-C Filters 22-48 Analog ICs; Jieh-Tsorng Wu
Frequency Tuning Using Switched Capacitors
V R
CI
V F
C1
R1
I BI B
Cm
CI
V F
C1
R1
Gm
Cm
2
1 1
2
Gm
N
2
1
1
2
Gm =1
Req
= fsCm
⇒Gm
Cm
= fs
NIB ·1Gm
· 1Req
= IB
⇒Gm
Cm
= Nfs
Gm-C Filters 22-49 Analog ICs; Jieh-Tsorng Wu
Frequency Tuning Using Response Detection
Rb
Cb
DetectorPeak
DetectorPeak
Ra
Ca
MOST-C Filter
R1R2
V
V
1
2
Tuning System
C
R
V F
Vr sin(ωrt + θ)
Gm-C Filters 22-50 Analog ICs; Jieh-Tsorng Wu
Frequency Tuning Using Response Detection
For this amplitude-response detection scheme
V1 = Vr ·1
ωrRCV2 = Vr ·
R2
R1 + R2
The feedback adjusts VF so that V1 = V2, thus
R · C =1ωr
·(
1 +R1
R2
)
• The above tuning system is a magnitude locked loop (MLL).
• Usually use ωrRC 1 to place ωr in the filter stopband.
• Phase-response detection scheme can also be used.
• The reference circuit can be any filter.
Gm-C Filters 22-51 Analog ICs; Jieh-Tsorng Wu
Frequency Tuning Using Phase-Locked Loop
Filter
Low-PassPhase-FreqDetector
FV
reff
C
mm
Variable-Frequency Oscillator
C
f oC
mGG
G
Gm-C Main Filter
Gm-C Filters 22-52 Analog ICs; Jieh-Tsorng Wu
Frequency Tuning Using Phase-Locked Loop
The phase-locked loop (PLL) forces
fref = fo =1
2π·Gm
C⇒
Gm
C= 2πfref
• For best matching between the reference VFO and the main filter, it is best to choosefref at the upper passband edge. However, the reference signal may leak into the mainfilter’s output.
• If fref moves away from the upper passband edge, the matching will be poorer, but animproved immunity to the reference signal results.
• If the VFO is sensitive to supply variation, any power-supply noise can inject jitter intoVF .
Gm-C Filters 22-53 Analog ICs; Jieh-Tsorng Wu
Q-Factor Tuning Using MLL
PeakDetBiquad
Bandpass
PeakDet
Q d
V ref
SlaveFilter
V i V o
V Q
Hbq(s) =ωps
s2 +ωp
Qps +ω2
p
Vref = A sinωrt
• At s = jωr = jωp, the MLL forces Hbq(jωp) = Qp = Qd .
• For high Q biquad, mismatch between ωr and ωp results in large Q-tuning error.
• Distortion in Vref can also cause error.
Gm-C Filters 22-54 Analog ICs; Jieh-Tsorng Wu
Q-Factor Tuning Using LMS
BiquadBandpass
Q d
1
V Q
V i V o
V ref
SlaveFilter
Hbq(s) =ωps
s2 +ωp
Qps +ω2
p
Vref = A sinωrt
dVQ(t)
dt= µ ·
[Vref(t) − Vbq(t)
]· Vbq(t)
The modified continuous-time least-mean-squares (LMS) algorithm will force
[Vref(t) − Vbq(t)
]· Vbq(t) = Vref(t) · Vbq(t) − V 2
bq(t) = 0
Gm-C Filters 22-55 Analog ICs; Jieh-Tsorng Wu
Q-Factor Tuning Using LMS
If ωr = ωp,
Vbq(t) =Qp
Qd
· A sinωrt = B · sinωrt B =Qp
Qd
· A
LMS ⇒ A · B2
=B · B
2⇒ A = B ⇒ Qp = Qd
If ωr = ωp,
Vbq(t) =Qp
Qd
cosφ · A sin (ωrt +φ) = B · sin (ωrt +φ) B =Qp
Qd
cosφ · A
LMS ⇒ A · B · cosφ2
=B · B
2⇒ A cosφ = B ⇒ Qp = Qd
• Insensitive to mismatch between ωr and ωp.
Gm-C Filters 22-56 Analog ICs; Jieh-Tsorng Wu
Q-Factor Tuning Using LMS
• Require no peak detector.
• The scheme is also insensitive to Vref waveform shape.
• Square wave can be used for Vref(t).
• Reference: J.-M. Stevenson, et al., An Accurate Quality Factor Tuning Scheme for IFand High-Q Continuous-Time Filters, JSSC 12/1998, pp. 1970–1978.
Gm-C Filters 22-57 Analog ICs; Jieh-Tsorng Wu
Switched-Capacitor Filters
Jieh-Tsorng Wu
October 23, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Switched-Capacitor Equivalent Resistor
V1 V2
eqR
Ieq
V V2
C
V1 V2φ φ1
φ
1
fs
φ
Ts
1
2
2
C
Ieq =(∆Q
∆t
)=
C · V1 − C · V2
Ts= C · (V1 − V2) · fs Ts =
1fs
Geq =1
Req
=Ieq
V1 − V2= C · fs
SC Filters 23-2 Analog ICs; Jieh-Tsorng Wu
Switched-Capacitor Integrators
1
oViV sfiV
2
Vo
C2
C
1R
C
Vo
Vi= − 1
sR1C2= −1
s·Geq1
C2= −1
s·(fs ·
C1
C2
)
• Consist of analog switches, capacitors and opamps.
• Discrete-time (or sampled-data) analog filters.
• Time constant is determined by capacitance ratio and switching frequency.
SC Filters 23-3 Analog ICs; Jieh-Tsorng Wu
SC Integrator Analysis
sT
φ1
φ2
1C
C2
V2C1C
oVV
z 1
o
i
φ1
φ2
aφ1
aφ2
V
a
Vi
2Q
1Q n n+1n-1n+1/2n-1/2
CLK
21
Vo(z)
Vi(z)= −
C1
C2× z
−1
1 − z−1
SC Filters 23-4 Analog ICs; Jieh-Tsorng Wu
SC Integrator Analysis
At cycle n, i.e., t = nTs, we have Q1(n) = C1Vi(n) and Q2(n) = C2Vo(n)
• At the unit-gain frequency ωi , where∣∣∣H(ejωiTs)
∣∣∣ = 1, we have
−m(ωi ) ≈ θ(ωi) ≈ 1/Ao if ωiTs/2 1
• In most applications, the magnitude error m(ω) has negligible effect, but the phaseerror θ(ω) can be detrimental in narrowband (high-Q) filters.
SC Filters 23-14 Analog ICs; Jieh-Tsorng Wu
Effects of Opamp’s DC Offset
Vi
V
2C
o
OS
CV
11
2 2
1
Vo(z) = −C1
C2
1
1 − z−1· Vi(z) +
C1
C2
1
1 − z−1· VOS + VOS
• The VOS to Vo transfer function is also an integration.
• When the entire filter is considered, the VOS may cause finite dc level shift in this andother integrators.
SC Filters 23-15 Analog ICs; Jieh-Tsorng Wu
An Offset Auto-Zeroing Scheme
φ1
φ
C
OS
Vi
C
V
C
o3
φ
2
1
2
3
V11
2 3
3
3
2
• During the φ3 auto-zeroing mode, opamp’s offset voltage is stored in C3.
SC Filters 23-16 Analog ICs; Jieh-Tsorng Wu
Effects of Opamp’s Finite Settling Time
C φ1
φ2
Vo
1C
2
A
oVVi
t slew
t settle
1
1
2 2
1
T
• Let tslew = 0, A(s) = ωu/s, T1 = Ts/2, ωi is the unit-gain frequency of the integrator,and ωiTs 1. At ω = ωi , the magnitude error and phase error of the integrator are
m(ωi) ≈ θ(ωi) ≈ −ωiTse−ωuTs/2
• Want ωu ≥ 5 · ωs. However, to avoid unnecessary noise aliasing, ωu should not betoo much larger than necessary.
SC Filters 23-17 Analog ICs; Jieh-Tsorng Wu
An SC Integrator with CDS
φ1
φ2
t1 t2 t3
C
C2 C2
A
OSV
OS
C’
o
V
Vo
i1
C
VOS
C1 C1 C’2C’2
V
2
2V
V
o
o
1
2 2
1 2
φ1 = 1 φ2 = 1
SC Filters 23-18 Analog ICs; Jieh-Tsorng Wu
An SC Integrator with CDS
Consider the VOS effect only. Let
Vi = 0 Ao =∞ and ∆VOS(t) = VOS(t) − VOS(t − Ts/2)
At t = t2
Vo(t2) = Vo(t1) + VOS(t2) +
(1 +
C′2
C2
)∆VOS(t2)
At t = t3
Vo(t3) = Vo(t2) − VOS(t2) +(
1 +C1
C2
)∆VOS(t3)
= Vo(t1) + ∆VOS(t2) +(
1 +C1
C2
)∆VOS(t3)
SC Filters 23-19 Analog ICs; Jieh-Tsorng Wu
An SC Integrator with CDS
2 2C’
C2 C2
1 C
ViV
aVo
CV
a
1 C’Vo
AoAo
φ1 = 1 φ2 = 1
Consider the finite dc gain effect only. Let VOS = 0, and
• For the SC biquad, it is important that the two-integrator loop have a single delayaround the loop. A delay-free loop may have an excessive settling time behavior,while two delays around the loop cause difficulties in designing high-Q circuit.
SC Filters 23-46 Analog ICs; Jieh-Tsorng Wu
Time-Staggered SC Stages
Cascaded SC Stages
1
1
1 1
1
12
2
1
2
2
1
2
2
2
1
2
2
1
2
11
Staggered Cascaded Stages
1
1
1
12
2
1
2
2
1
2
2
2
1 1
2 1
2 1
2
2
1
SC Filters 23-47 Analog ICs; Jieh-Tsorng Wu
Capacitor Scaling
31
C
4Q
3Q
2V
1V
4C
C
2
o
C
AC
iQV
2 1
2 1
21
21
For each switching cycleQi = C1V1 + C2V2
∆Vo = −Qi
CA
Q3 = C3Vo Q4 = C4Vo
SC Filters 23-48 Analog ICs; Jieh-Tsorng Wu
Output Capacitor Scaling
If C′A = kCA, C′3 = kC3, C′4 = kC4, C1 and C2 unchanged, then
Q′i= C1V1 + C2V2 = Qi
∆V ′o = −Q′i
C′A
= −Qi
kCA
=∆Vo
k
Q′3 = C′3V′o = kC3
Vo
k= Q3 Q′4 = Q4
• If the values of all capacitors (including feedback capacitors) connected or switchedto the output terminal of an opamp in an SCF are multiplied by the same constant k,then the output voltage of this opamp will be divided by k; all other opamp outputvoltages remain unchanged. This follows since the described changes leave allcharges flowing to and from the affected opamp unchanged.
• The output capacitor scaling technique can be used to achieve optimum scaling formaximum dynamic range.
SC Filters 23-49 Analog ICs; Jieh-Tsorng Wu
Input Capacitor Scaling
If C′A = kCA, C′1 = kC1, C′2 = kC2, C3 and C4 unchanged, then
Q′i= C′1V1 + C′2V2 = kC1V1 + kC2V2 = kQi
∆V ′o = −Q′i
C′A
= −kQi
kCA
= ∆Vo
Q′3 = C3V′o = C3Vo = Q3 Q′4 = Q4
• If the values of all capacitors (including feedback capacitors) connected or switchedto the inverting input terminal of an opamp are multiplied by the same constant, thenall voltages in the SCF remain unchanged. This is true since all voltages are affectedonly by the ratios of these capacitances.
• The input capacitor scaling technique can be used to achieve optimum scaling forminimum capacitance.
SC Filters 23-50 Analog ICs; Jieh-Tsorng Wu
An All-Pole Low-Pass Ladder Filter
RL
V 1
RSV in
V 2V 0
V 1
V 4
V 5V 3
V in V out
V in V 2
V 1
V 4
V outV 5
S C11+sR
SR
I 0 I 2 I 4 V 5V 3
C1L2
C3 C5L4
I 6
1/(sL L
V 6
S1/R 1/(sL2) -1/(sC 3) 4) -1/(sC 5) 1/R-1/(sC )1
S1/R
L C51+sR
LR
V out
SC Filters 23-51 Analog ICs; Jieh-Tsorng Wu
An All-Pole Low-Pass SC Ladder Filter
2
1
2
1
C
C
C
LC
21
SC
V in
V 3 V 5
C
V 1
V 4V 2
V out
C1
V out
C1RS
RS
V 1
V in
V 2
V 5
V 4
V 3
L2 L4
C3
C5
C 2
1
C3
1
2
1
2
SC CC2 4
CC C
1
1
2
2
1 2 1
2 1 2
1
1 1
R CL 5
11
1 11
SC Filters 23-52 Analog ICs; Jieh-Tsorng Wu
SC Ladder Filter Using Signal-Flow Graph
iKK
V1 1V 1oV1
iVo11
1
2
2
C = 1Noninverting FE Integrator
1
2 2
1 1
C = 1Inverting BE Integrator
HBE (z) = −K · 1
1 − z−1HFE (z) = +K · z
−1
1 − z−1
• HBE (z) is a Backward-Euler (BE) integrator. HFE (z) is a Forward-Euler (FE) integrator.
• The phase errors of the integrators are cancelled in the ladder topology, while themagnitude errors can cause deviations in the frequency response when ωTs 1 isno longer true.
• The SC ladder filters are inherently time-staggering.
SC Filters 23-53 Analog ICs; Jieh-Tsorng Wu
SC Ladder Filters Design Methodology
It is possible to realize the SC ladder filters with exact frequency response, using onlythe BE and FE integrators. The design procedures involves bilinear transformationprewarping and frequency-dependent impedance scaling.
λ =s′Ts
2=
z1/2 − z
−1/2
z1/2 + z−1/2= tanh
sTs
2
γ =12
(z1/2 − z−1/2
)= sinh
sTs
2µ =
12
(z1/2 + z−1/2
)= cosh
sTs
2
⇒ λ =γ
µµ2 − γ2 = 1 z1/2 = µ + γ
• λ↔ z is the bilinear (BL) transformation.
• γ ↔ z is the lossless discrete (LD) transformation.
• The design goal is to implement H(z = e
sTs)
with H(γ). H(γ) can then be realized
with SC integrators.
SC Filters 23-54 Analog ICs; Jieh-Tsorng Wu
SC Ladder Filters Design Procedures
1. Prewarp the filter specifications from ω to ω′ with bilinear transformation.
ω′ =2Ts
tanωTs
2
2. Find H(s′). Renormalize H(s′) into H(λ) by setting s′Ts/2 = λ.
3. Realized H(λ) as an LC ladder filter in λ domain.
4. Scale the impedance level,
Y (γ) = µY (λ) Z(γ) = Z(λ)/µ
to obtain the γ-domain LC ladder circuit.
5. Implement the γ-domain circuit with SC circuits.
SC Filters 23-55 Analog ICs; Jieh-Tsorng Wu
Nyquist-Rate Digital-to-Analog Converters
Jieh-Tsorng Wu
July 16, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
A/D and D/A Interfaces
fs
fs
fs
DigitalProcessor
A/DInterface
D/AInterface
y(t)x(t) x(n) y(n)
WorldAnalog
D/A Deglitcher Inverse-Sinc / Low-PassFilter
y(n) y(t)
Converter
Digital-to-Analog Interface
FilterLow-Pass DecoderQuantizerSampling
Circuit
x(t) x(n)
Analog-to-Digital Interface
DACs 24-2 Analog ICs; Jieh-Tsorng Wu
Continuous-to-Discrete Conversion
DACTimeDiscrete
ProcessingPrefilter
c (t)
Analog
d (t) ycx
Ts
Ts
c
y
x
T
(t)
2Ts3Ts
(t)
s
AnalogPostfilter
Sampling
y(n)x(n)
0
A
t0
2π0 4π
Ax(n)
0n
1 2 3
Ω
ω
Ωb Ωs 2Ωs
Xc(jΩ)
X(ejω)
DACs 24-3 Analog ICs; Jieh-Tsorng Wu
Discrete-to-Continuous Conversion
0
1
Ts
d (t)
T
y
2Ts3Ts
s s3Ts2T
t0
A
0
A
t0
y (t)c
Ω
Ω
Ω
Ωs
Ωs
Ωs
2Ωs
2Ωs
2Ωs
Yd (jΩ)
Yc(jΩ)
sinc(π ΩΩs
)
DACs 24-4 Analog ICs; Jieh-Tsorng Wu
Discrete-to-Continuous Conversion
The digital-to-analog converter (DAC) usually performs the discrete-to-continuoussample-and-hold translation, i.e.,
yd (t) =∞∑
n=−∞y(n) · (t − nTs) where (t) =
1 if 0 < t < Ts0 otherwise
The continuous-time Fourier transform (CTFT) of yd (t) can be expressed as
Yd (jΩ) = Yd (z)|z=ejΩTs × Hda(jΩ) = Yd(ejω)∣∣
ω=ΩTs× Hda(jΩ)
The discrete-to-continuous sample-and-hold transfer function is
Hda(s) =1 − e
−sTs
sHda(jΩ) = e−jπΩ/Ωs · Ts · sinc
(πΩ
Ωs
)
Ωs = 2πfs =2πTs
sinc(x) =sinx
x
DACs 24-5 Analog ICs; Jieh-Tsorng Wu
Imperfections in Discrete-to-Continuous Conversion
The D/A conversion of y(n) can be expressed as:
yd (t) =∞∑
n=−∞y(n) · C[t − nTs + ε]
• The y(n)→ y(n) conversion may contains gain error, offset, and nonlinearity.
• C(t) has transient behavior. Its pulse width can be larger than Ts.
• C(t) may contain y(n) dependency.
– A return-to-zero C(t) can reduce the y(n) dependency.
• The timing jitter ε can be random or deterministic.
DACs 24-6 Analog ICs; Jieh-Tsorng Wu
D/A Transfer Characteristic
bN-1 b1 b0
Ao
AFS
AFS
Ao
Din000 100
2
111
D/A
(Analog Output)
(Digital Input)
0
AF S = Full-Scale Output
∆ = LSB = Step Size =AF S
2N
Ao = ∆ × Din
= ∆ ×[bN−12N−1 + · · · + b121 + b020]
= AF S ×[bN−12−1 + · · · + b12−(N−1) + b02−N
]
• In some applications, relationship between Din and Ao can be nonlinear.
• Din may use other coding scheme such as offset binary or 2’s complement.
DACs 24-7 Analog ICs; Jieh-Tsorng Wu
D/A Transfer Characteristic
Din
00
Nonmonotonic Offset Gain Error
Din
Ao Ao
Din
Ao
0
AOS
Ideal Ideal
Offset Error =AOS
∆AOS = Ao|Din=0
Gain Error =Ao,max − AOS
∆ · (2N − 1)=
Ao,max − AOS
AF S · (1 − 2−N)
DACs 24-8 Analog ICs; Jieh-Tsorng Wu
D/A Nonlinearity
Din
Aoo
0
Large INLLow DNL
0
DNL=-1LSB
0Din
Ao
Din
A
DNL
INL
• Measure of deviation from straight line with offset and gain error corrected.
• Differential nonlinearity (DNL): Maximum deviation of the analog output step fromthe ideal value of 1 LSB (= ∆).
• Integral nonlinearity (INL): Maximum deviation of the analog output from the idealvalue.
DACs 24-9 Analog ICs; Jieh-Tsorng Wu
D/A Performance Metrics — Static Characteristics
• Resolution: number of bits (N), analog 1 LSB step (∆).
• Offset error.
• Gain error.
• Integral nonlinearity (INL).
• Differential nonlinearity (DNL).
• Monotonicity.
– Monotonicity can be assumed if the DNL > −1 LSB.
• Stability.
– Variation with time, temperature, and supply voltage.
DACs 24-10 Analog ICs; Jieh-Tsorng Wu
D/A Performance Metrics — Dynamic Characteristics
• Sampling rate.
• Settling time.
– Settling time is the time taken by the D/A output to settle within some specifiederror band (typically ±1
2 LSB).– The settling time is primarily dominated by the settling of the MSB contribution.
• Glitch impulse area (glitch energy).
– Glitches is the output transient spikes during the conversion process.– Glitches are caused by the unequal delays in switching various signal sources
within the converter.
• Dynamic range: SNRmax, SFDR, SINAD.
DACs 24-11 Analog ICs; Jieh-Tsorng Wu
Dynamic Range
N-Bit DACN-Bit y(t)
Measured
Input Level Relative to Full Scale
dB
Ideal
0
(dB)
if i2f i3f
sf
SINAD
f
dBm/Hzy(t) Power Spectrum
SFDR
Probability Density Function (pdf)
e/2
y(k)x(k)
/2
Quantizer
e(k)
y(k)x(k)
DACs 24-12 Analog ICs; Jieh-Tsorng Wu
Dynamic Range
e(k) is a quantization noise due to the quantization process.
When the input’s amplitude A = AF S/2, the SNR reaches its maximum value.
AF S = 2N∆ Ps =18· 22N∆2 SNRmax = 22N × 3
2= N × 6.02 dB + 1.76 dB
DACs 24-13 Analog ICs; Jieh-Tsorng Wu
Dynamic Range
• The ratio between fs and fi should be irrational.
• In the discrete-time domain, noise power of e(k) is assumed to be uniformlydistributed between −Ωs/2 and +Ωs/2. The power density is ∆
2/(12Ωs).
• The spurious free dynamic range (SFDR) is the ratio of the fundamental signalcomponent to the largest distortion component when A = AF S/2.
• The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of thefundamental signal to the total power of noise and distortion when A = AF S/2.
• The total harmonic distortion (THD) is the ratio of the total power of the 2nd and higherharmonic components to the power of the fundamental signal.
• In finding the total noise power, the noise bandwidth need to be specified.
DACs 24-14 Analog ICs; Jieh-Tsorng Wu
Resistor-String DACs with Digital Decoding
oV
refV inD
N1
of
2D
eco
der
R
R
R
N
• Inherently monotonic.
• DNL depend on local matching of neighboring R’s.
• INL depends on global matching of the R-string.
• No resistive load at Vo.
• The worst-case time constant occurs a themidpoint of the R-string.
• Large capacitive loading at Vo.
DACs 24-15 Analog ICs; Jieh-Tsorng Wu
Folded R-String DACs with Digital Decoding
oV
inD
refV
1 of 2 N-M Decoder
1 o
f 2
MD
eco
der
M
N-M N
(MS
Bs)
DACs 24-16 Analog ICs; Jieh-Tsorng Wu
R-String DACs with Binary-Tree Decoding
Vref
Vo
R
R
R
R
R
R
R
R
00b b 1 1b b 2 2b b
• Require no digital decoder.
• Speed is limited by the delay throughthe resistor string as well as thedelay through the switch network.
• Latches are often used to synchronize bN−1, bN−2, . . . .
• Ro of the current sources can cause nonlinearity.
Io
in = 0111 Din = 1000D
Glitch
t
DACs 24-21 Analog ICs; Jieh-Tsorng Wu
Binary-Weighted R-2R Networks
I2I4I8I
BV
I
2R 2R 2R 2R
2RRRR
8 I 4 I 2 I 1 I 1 I
16 I
16 I
x2x8 x4 x1 x1
VEE
R RR2R 2R 2R 2R 2R
• No wide-range scaling of resistors.
• BJT emitter-area scaling can be confined to the first few MSBs; and the voltage dropsin the emitter resistors should dominate the VBE (on) mismatches of the less significantbits.
DACs 24-22 Analog ICs; Jieh-Tsorng Wu
Equally-Weighted Current-Steering DACs
V B
1 2
III
I
Din
-1N2
B
o
BV V
Binary- to-Thermometer DecoderN
• Inherently monotonic.
• Glitches are reduced. Synchronizing latches may be still required.
DACs 24-23 Analog ICs; Jieh-Tsorng Wu
The Matrix Floorplan
N
M
Io
in
Ri
D
jC
DecoderRi
Cj
Local
Ro
w D
eco
der
Column Decoder
MSBs
LSBs
• Rj is a 2M − 1 thermometer code, and Cj is a 2N−M − 1 thermometer code.
• One example of the local decoding is S = Ri+1 + Ri · Cj .
• INL may exhibit the gradient of the unit cell’s variations.
• INL can be dithered by jumping selection of unit cells.
DACs 24-24 Analog ICs; Jieh-Tsorng Wu
A Current Cell Example
tM3
SEL
SEL
CLK
M2M1V1
V
Io1 Io2
VB1V2
Va
2
V1
VSS
C
LocalDecoderi+1R
iR
j
• The current switch MOSTs, M1 and M2, are in the triode region when fully turned on.
• To minimize voltage fluctuation at Va, the inverters are sized so that the cross-overvoltage of the V1 and V2 transient waveforms can turn on both M1 and M2.
• Reference: C-H Lin and K Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,”JSSC, 12/1998, pp. 1948–1958.
DACs 24-25 Analog ICs; Jieh-Tsorng Wu
Charge-Redistribution DACs
1
1
2
o
b
b
V
b
Vo
ref
2
V
V
b bb
b b
222
ref
2 2 2
2
C 2 C 1C 0C
N-1 C 2 C 1C 0C
NC
12 0
2 1 0
N-1
N-1
N-1 CpC
DACs 24-26 Analog ICs; Jieh-Tsorng Wu
Charge-Redistribution DACs
During φ1 = 1,Cap Bottom Plate @ GND Vo = 0
During φ2 = 1,
bi =
1 → Cap Bottom Plate @Vref0 → Cap Bottom Plate @GND
Vo = Vref ×C
2NC + Cp
×N−1∑i=0
bi2i
• Binary-weighted or equally-weighted capacitor array.
• Cp is top plate parasitic capacitance, and introduces a gain error.
• Opamp can be used to provide voltage gain and mitigate the effects of Cp.
• DACs at resolutions of 10 bits or above usually requires some kind of trimming orcalibration.
DACs 24-27 Analog ICs; Jieh-Tsorng Wu
Segmented DAC Architecture
M-Bit DAC
L-Bit DAC
Din
A
N
Ao
AM
L L
M Din =N−1∑i=0
bi2i =
M−1∑i=0
bi+L2i+L +L−1∑j=0
bj2j
AM = ∆M ×M−1∑i=0
bi+L2i AL = ∆L ×L−1∑j=0
bj2j
N = M + L ∆M = 2L × ∆L
Ao = AM + AL = ∆L ×M−1∑i=0
bi+L2i+L + ∆L ×L−1∑j=0
bj2j = ∆L ×
N−1∑i=0
bi2i
• The M-DAC need to have ±∆L/2 accuracy.
• Signal path delay mismatch between the M-DAC and the L-DAC can cause glitch.
• Can have more than two segments.
DACs 24-28 Analog ICs; Jieh-Tsorng Wu
A 10-Bit Segmented Current-Steering DAC
Ro
w D
eco
der
Ro
w D
eco
der
Ro
w D
eco
der
Column Decoder Column Decoder
Column Decoder Column Decoder
Ro
w D
eco
der
Io
Io
B7-B9
B7-B9
8 x 8
8 x 8
8 x 8
8 x 8
B7-B9
B7-B9
B4-B6B4-B6 B0-B3
B4-B6B4-B6
DACs 24-29 Analog ICs; Jieh-Tsorng Wu
A 10-Bit Segmented Current-Steering DAC
• Segmented 6-2-2 architecture with common-centroid layout.
• Each current cell in the matrix contains 4 LSB current.
• Reference: J. Bastos, et. al., “A 12-Bit Intrinsic Accuracy High-Speed CMOS DAC,”JSSC 12/1998, pp. 1959–1969.
DACs 24-30 Analog ICs; Jieh-Tsorng Wu
A Segmented Current-Steering DAC
LM
C
N
I
Din
BV BV BV
o
VI I I4X 1X1X2X
L-DAC Binary DecoderM-DAC Thermometer Decoder
• Greatly reduces area for large N while ensuring monotonicity (at least for MSBs).
• The L-DAC can be a binary-weighted DAC if its glitches can be tolerated.
• Reference: H. Schouwenaar, et al., JSSC 12/88, pp. 1290–1297.
DACs 24-31 Analog ICs; Jieh-Tsorng Wu
Dynamically-Matched Current Sources
IB1
Cbr
MS1
Iref
VB1MS1D
MC1
M4
Out
M3
M2M1
B1I
Iref
OutIoIref
Out
V
Iref
Iref
Cbr
B2
C Cs C Css s
VSS
sVSS
VSS
VSS
sC
S1M1
Calibration
S1M1
Operation
Switch Array
C
DACs 24-32 Analog ICs; Jieh-Tsorng Wu
Dynamically-Matched Current Sources
• The bias voltage for the current sources is stored in each individual Cs. The voltageon Cs is refreshed periodically by means of calibration.
• A spare current source can be added to facilitate uninterrupted operation.
• Cs can be just the Cgs of M1.
• The switching error of MS1 as well as gm1 must be minimized.
• By adding M2 with a constant current, gm1 can be reduced.
• 16-bit resolution can be achieved using this technique.
• Reference: D. Groeneveld, et al., JSSC 12/89, pp. 1517–1522.
DACs 24-33 Analog ICs; Jieh-Tsorng Wu
A Segmented Charge-Redistribution DAC
M-DAC
ib
V
V refV
222
ref
L-DAC
jb
Vx o
0C2 C1C
L
C
M
C C
Din =N−1∑i=0
bi2i N = M + L Vx =
Vref
2L·L−1∑j=0
bj2j
Vo =Vref
2M·M−1∑i=0
bi+L2i +1
2M· Vx =
Vref
2M+L·
M−1∑
i=0
bi+L2i+L +L−1∑j=0
bj2j
=
Vref
2N·N−1∑i=0
bi2i
DACs 24-34 Analog ICs; Jieh-Tsorng Wu
A Capacitor-Resistor Hybrid DAC
M
M-DAC
L-DAC
b
22
oV
22
2
Vref
b refV
2
L
2 CC0C C
j
1 0CM-1
MC
i
Vo =Vref
2M×
M−1∑i=0
bi+L2i +1
2M×Vref
2L×
L−1∑j=0
bj2j =
Vref
2N×
N−1∑i=0
bi2i N = M + L
DACs 24-35 Analog ICs; Jieh-Tsorng Wu
A Resistor-Capacitor Hybrid DAC
1
2
1
L-DAC
M
M-DAC
L
2V
b
oV
2
V
ref
2
V
22
b
L-1
j
C2 1C 0CC
i
L C
V1 = ∆M ×M−1∑i=0
bi+L2i V2 = V1 + ∆M ∆M =Vref
2MN = M + L
DACs 24-36 Analog ICs; Jieh-Tsorng Wu
A Resistor-Capacitor Hybrid DAC
During φ1 = 1,Cap Bottom Plate @ GND Vo = 0
During φ2 = 1,
bi =
1 → Cap Bottom Plate @V2
0 → Cap Bottom Plate @V1
Vo = V1 +∆M
2L×
L−1∑j=0
bj2j =
Vref
2M×
M−1∑i=0
bi+L2i +Vref
2M+L×
L−1∑j=0
bj2j =
Vref
2N×
N−1∑i=0
bi2i
• The capacitor array interpolates the voltages between V1 and V2.
• Reference: J.-W. Yang, et al., JSSC 10/89, pp. 1458–1461.
DACs 24-37 Analog ICs; Jieh-Tsorng Wu
Nyquist-Rate Analog-to-Digital Converters
Jieh-Tsorng Wu
November 13, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
A/D and D/A Interfaces
fs
fs
fs
DigitalProcessor
A/DInterface
D/AInterface
y(t)x(t) x(n) y(n)
WorldAnalog
D/A Deglitcher Inverse-Sinc / Low-PassFilter
y(n) y(t)
Converter
Digital-to-Analog Interface
FilterLow-Pass DecoderQuantizerSampling
Circuit
x(t) x(n)
Analog-to-Digital Interface
ADCs 25-2 Analog ICs; Jieh-Tsorng Wu
Continuous-to-Discrete Conversion
DACTimeDiscrete
ProcessingPrefilter
c (t)
Analog
d (t) ycx
Ts
Ts
c
y
x
T
(t)
2Ts3Ts
(t)
s
AnalogPostfilter
Sampling
y(n)x(n)
0
A
t0
2π0 4π
Ax(n)
0n
1 2 3
Ω
ω
Ωb Ωs 2Ωs
Xc(jΩ)
X(ejω)
ADCs 25-3 Analog ICs; Jieh-Tsorng Wu
A/D Quantization Characteristic
N-1 b 0
A i
A
b
1/2 i
1/2
A i
Do
b 1
Quantizer
(Analog Input)
(Digital Output)Quantization Error Q
100
111
000/ 2A FS A FS
Ai,tran = ∆ ×N−1∑i=0
bi2i − 1
2∆
AFS = Full-Scale Output ∆ = LSB = Step Size =AF S
2N
ADCs 25-4 Analog ICs; Jieh-Tsorng Wu
Imperfections in A/D Quantization Characteristic
NonlinearityGain ErrorOffset
A i
Do
A
o o
A ii
DIdeal Ideal IdealD
• Differential nonlinearity (DNL) : Maximum deviation in step width (width betweentransitions) from the ideal value of 1 LSB (= ∆).
• Integral nonlinearity (INL) : Maximum deviation of the step midpoints from the idealstep midpoints. Or the maximum deviation of the transition points from ideal.
• If DNL = −1 LSB⇒ missing code.
ADCs 25-5 Analog ICs; Jieh-Tsorng Wu
Quantization Noise
e
sf
/2
QuantizerN-Bit
/2
Probability Density Function (pdf)x(k)
y(k)x(t)
x(k) y(k)
e(k)
e(k) is a quantization noise due to the quantization process.
When the input’s amplitude A = AF S/2, the SNR reaches its maximum value.
AF S = 2N∆ Ps =18· 22N∆2 SNRmax = 22N × 3
2= N × 6.02 dB + 1.76 dB
• The ratio between fs and fi should be irrational.
• In the discrete-time domain, noise power of e(k) is assumed to be uniformlydistributed between −Ωs/2 and +Ωs/2. The power density is ∆
2/(12Ωs).
ADCs 25-7 Analog ICs; Jieh-Tsorng Wu
Sampling-Time Uncertainty (Aperture Jitter)
t
V
fs
kTs
tx(t) x(k)
x(k) = x (kTs + ∆t) Ts =1fs
For a full-scale sinusoidal input
x(t) =12AF S sin(2πfit) AF S = 2N∆
∆V ≈ dx
dt× ∆t < AF S · πfi × ∆t <
12∆ ⇒ ∆t <
1
2N· 12πfi
ADCs 25-8 Analog ICs; Jieh-Tsorng Wu
Sampling-Time Uncertainty (Aperture Jitter)
Let x(t) = 12AF S sin (2πfit) and ∆t be a random variable, then
x(k) = x (kTs + ∆t) ≈ 12AF S sin(2πfikTs) +
dx(t)
dt
∣∣∣∣t=kTs
× ∆t
≈ 12AF S sin(2πfikTs) + AF Sπfi cos(2πfikTs) × ∆t
x2(k) =18A2F S
+12A2F S
π2f 2i× ∆t2 = Ps + Pn
The signal-to-noise ratio of x(k) is
SNR =Ps
Pn=
1
4π2f 2i· ∆t2
= −20 log (2πfi · ∆trms) dB
• If fi = 1 MHz, N = 14, SNR = 86 dB, want ∆trms < 8.0 psec.
• If fi = 100 MHz, N = 10, SNR = 62 dB, want ∆trms < 1.26 psec.
ADCs 25-9 Analog ICs; Jieh-Tsorng Wu
DFT Nonlinearity Test of ADCs
fif
dBm/Hzy(t) Power Spectrum
i
SFDR
fs
2f i3f
y(k)
Quantizer
x(k)DFTx(t) N-Bit
45
50
55
60
-15-20 -5-10-25
10 Bit
9 Bit
8 Bit
SINAD (dB)
040
Input Level Relative to Full Scale (dB)
ADCs 25-10 Analog ICs; Jieh-Tsorng Wu
DFT Nonlinearity Test of ADCs
• The ratio between fs and fi should be irrational.
• In the discrete-time domain, noise power of e(k) is assumed to be uniformlydistributed between −Ωs/2 and +Ωs/2. The power density is ∆
2/(12Ωs).
• The spurious free dynamic range (SFDR) is the ratio of the fundamental signalcomponent to the largest distortion component when A = AF S/2.
• The signal-to-noise plus distortion ratio (SINAD) is the ratio of power of thefundamental signal to the total power of noise and distortion when A = AF S/2.
• In finding the total noise power, the noise bandwidth need to be specified.
ADCs 25-11 Analog ICs; Jieh-Tsorng Wu
Code Density Test of ADCs
t
fs
x(t)
W(i)
QuantizerD
o
o
D
iA
N-Bitx(k)x(t) Histogram
y(k)
H(i)
ADCs 25-12 Analog ICs; Jieh-Tsorng Wu
Code Density Test of ADCs
Let Nt be the total number of samples, H(i ) the number of counts in the i -th Do, and P (i )the ideal probability for the i -the Do. We have
W (i )
∆=(Ai+1,tran − Ai,tran
)· 1∆
=H(i )
Nt
· 1P (i )
• For high precision, sinusoidal waveform is usually for the input. The probability densityp(V ) for A sin(ωt) is
p(V ) =1
π√A2 − V 2
• To test a 12-bit ADC, for 99 percent confidence and 0.10 bit precision, 4.2 millionsamples are needed.
• Reference: Doernberg, JSSC 12/84, pp. 820–827.
ADCs 25-13 Analog ICs; Jieh-Tsorng Wu
Serial (Integrating) Architectures
x
iV
fV
RCiV
RCrefV
TT
VrefVx Logic
Control
1 2
c
Do
Counter
R1
C1
S2
S1
t
ADCs 25-14 Analog ICs; Jieh-Tsorng Wu
Serial (Integrating) Architectures
The output isDo
fc= T2 = T1 ·
Vi
Vref
• Linear search of possible subregions.
• Integrating types: single slope, dual slope, quad-slope.
• Low conversion rate. Requires 2 × 2N clock cycles for a full-scale conversion.
• The input is integrated in the T1 period, resulting in a filer transfer function of
|H(f )| =∣∣∣∣sin(πT1f )
πT1f
∣∣∣∣
ADCs 25-15 Analog ICs; Jieh-Tsorng Wu
Parallel (Flash) Architectures
N221
V
-2 2
oD
refV
N-1
i
2N-1( ) - to - N Encoder
N
ADCs 25-16 Analog ICs; Jieh-Tsorng Wu
Parallel (Flash) Architectures
• All subregions are examined simultaneously. One comparator per subregion.
• Using 2N−1 comparators, the input is simultaneously compared with 2N−1 referencevoltages derived from resistor string.
• High speed. Requires only one comparison cycle per conversion.
• Large size and power dissipation for large N.
• Design issues: input capacitive loading, clock jitter and dispersion, slew-dependentsampling point, nonlinear input capacitance, resistor-string dc and ac bowing,substrate and power-supply noises, kickback noises, sparkles in thermometer code.
• Gray encoding is often used as an intermediate step between thermometer and binarycodes.
ADCs 25-17 Analog ICs; Jieh-Tsorng Wu
Successive Approximation Architectures
N
Do
Vi
Vref
VDA
FS
CLK
DA
V
V
N-1 =1 b =1N-3b
=1=0N-2 b N-4
V
Control
b
i
Logic
DAC 1/2 3/4 5/8 7/16
t
ADCs 25-18 Analog ICs; Jieh-Tsorng Wu
Successive Approximation Architectures
• Binary search of possible subregions.
• Fraction of VF S corresponding to each bit is successively (starting with MSB) addedto fraction corresponding to already determined bits and sum is compared to input.
• N comparisons per conversion.
• Requires a high-speed DAC with precision on the order of the converter itself.
• Excellent trade-off between accuracy and speed.
ADCs 25-19 Analog ICs; Jieh-Tsorng Wu
Charge-Redistribution ADC
2
S
SSSSS
S
i
V
V
22 2
1
2
refrefV
xV
2
pC
C1 C0A C0BC2
x
LSBMSB
N-1 2 1 0A 0B
i
00 CC1C2CN-1 CCN-1
Ctot =N−1∑i=1
2iCi + C0A + C0B = 2NC
ADCs 25-20 Analog ICs; Jieh-Tsorng Wu
Charge-Redistribution ADCs
Sample Mode
• Sx → GND. Vx = 0.
• S0A, S0B, S1, S2, · · · , SN−1, Si → Vi .
Hold Mode
• Sx open.
• S0A, S1, S2, · · · , SN−1→ GND.
• S0B → −12Vref , sets transition offset to 1
2∆.
Vx = −Vi −C0B
Ctot
·Vref
2= −Vi −
12·Vref
2N∆ =
Vref
2N
ADCs 25-21 Analog ICs; Jieh-Tsorng Wu
Charge-Redistribution ADCs
Redistribution Mode
• Si → Vref .
• Test bits one at a time in succession, beginning with bN−1.
• If Vx < 0, bi = 1, Si → Vref .If Vx > 0, bi = 0, Si → GND.
The effect of parasitic capacitance, CP
• The voltage on the summing node becomes V′x = Vx ·
Ctot
Ctot+Cp.
• Cp has no effect on the A/D quantization characteristic, if the comparator is ideal.
• CP does attenuate Vx, thus requiring higher comparator gain.
ADCs 25-23 Analog ICs; Jieh-Tsorng Wu
C-R ADCs Using Input O ffset Storage Technique
S
OSV
xV
x
A
Capacitor Array
• Non-zero comparator offset can be cancelled by referencing Vx to the offset, ratherthan GND during sampling.
ADCs 25-24 Analog ICs; Jieh-Tsorng Wu
Self-Calibrating Charge-Redistribution ADCs
M-12 12 02
x
C
S
CC
x
Do
C
xVV
20
V
ControlApproximation
Successive
x
M-1 1 0 0C
Calibration DACL-DAC
ControlCalibration
RegisterData
EN-i
(b) Switch(a) Initialize
CC C C
<
=
>
A B A B
C C
C C
C C
A B
A B
A B
V Vref ref
Calibration Basic Concept
M-DAC
t
ADCs 25-25 Analog ICs; Jieh-Tsorng Wu
Self-Calibrating Charge-Redistribution ADCs
• The error voltage Vx, thus the capacitor mismatch, can be digitized by the CalibrationDAC.
• During the calibration, the capacitor mismatches in CM−1, CM−2, · · · , C0 are measuredsequentially, and stored in the data register.
• During the normal operation, the calibration DAC generate a correction voltage thatcompensates the error voltage caused by the mismatches in the capacitor array
• The binary-weighted capacitor array has an accuracy of about 10 bits. With self-calibration, 16-bit resolution is possible.
During normal operation, the Vx generated by the M-DAC is
Vx = Vref
M−1∑0
(bi+L ·
Ci
Ctot
)
The Vx is corrected by the C-DAC as
V cx = Vx +
M−1∑i=0
(bi+L · Ei) = Vref
M−1∑0
(bi+L ·
Ci
Ctot
)− Vref
M−1∑i=0
(bi+L ·
∆Ci
Ctot
)
= Vref
M−1∑i=0
(bi+L ·
Ci − ∆Ci
Ctot
)
=Vref
2M
M−1∑i=0
(bi+L · 2i
)
ADCs 25-30 Analog ICs; Jieh-Tsorng Wu
Quantized-Feedforward (Subranging) Architectures
DjAj )(
jA j+1A
jD
jG
da
(+2)adA(+1)adA(-1)adA
1D
oD
D
PStage
P2D
21StageStage
0
0
ADC
MSBs LSBs
Encoder
A i
jA
j+1A
DAC
ADCs 25-31 Analog ICs; Jieh-Tsorng Wu
Quantized-Feedforward (Subranging) Architectures
The relationship between Aj and Aj+1 is
Aj+1 =[Aj − Ada
j(Dj)]· Gj ⇒ Aj = Ada
j(Dj) +
Aj+1
Gj
The input Ai can be expressed as
Ai = Ada1 +
Ada2
G1+
Ada3
G1G2+ · · · +
AdaP
G1G2 · · ·GP−1+
AP+1
G1G2 · · ·GP
• If Adaj (Dj) and Gj are known, Ai can be computed from D1, D2, · · · , DP .
• The term, Q = AP+1/(G1G2 · · ·GP ), is the conversion error (quantization error).
• Aadj has no effect on the A/D result.
• Gj may include sample-and-hole function for pipeline or cyclic operation.
ADCs 25-32 Analog ICs; Jieh-Tsorng Wu
Quantized-Feedforward (Subranging) Architectures
If the Gj amplifier has dc offset, i.e.,
Aj+1 =[Aj − Ada
j(Dj) − Aos
j
]· Gj ⇒ Aj = Ada
j(Dj) + Aos
j+Aj+1
Gj
The input Ai can be expressed as
Ai = Ada1 +
Ada2
G1+
Ada3
G1G2+ · · · +
AdaP
G1G2 · · ·GP−1+
AP+1
G1G2 · · ·GP
+ Aos
The entire system has an dc offset of
Aos = Aos1 +
Aos2
G1+
Aos3
G1G2+ · · · +
AosP
G1G2 · · ·GP−1
• Ref: E. Soenen and R. Geiger, “An Architecture and An Algorithm for Fully DigitalCorrection of Monolithic Pipelined ADC’s,” IEEE CAS II, pp. 143–153, March 1995.
ADCs 25-33 Analog ICs; Jieh-Tsorng Wu
Quantized-Feedforward Minimal Design
A jA j
A j+1 A j+1+1
0
-1
G = 2
ADC
+1
-1ADC
-1/2
+1/2
0
G = 4
DAC -1 +1DAC +1-1 0
+1/2
-1/2
0
G = G1 = G2 = · · · = GP = integer ∆A =2G
Q =AP+1
G1G2 · · ·GP
<1
GP
Effective Number of Bit = N = log21
Qmax
= P × log2 G
• There are M = G − 1 comparators in the ADC. G is preferred to be power of 2.
• Dj has M + 1 different values, and the DAC has corresponding M + 1 different outputvalues.
ADCs 25-34 Analog ICs; Jieh-Tsorng Wu
Over-Range in the Minimal Design
Assume nonideal ADC, DAC, and G, as
Aadj
= Aadj
+ εadj
Adaj
= Adaj
+ εdaj
Gj = Gj ×(
1 + εgj
)
Then we have
Aj+1 =[Aj − Ada
j(Dj) + (εad
j− εda
j)]· Gj =
[Aj − Ada
j(Dj )]· Gj + OR
The over range, OR, is
OR =[Aj − Ada
j(Dj)]ε
gjGj + (εad
j− εda
j) · Gj ≤ ε
gj+ (εad
j− εda
j) · Gj
• Nonideal ADC, DAC, and G, can cause Aj+1 in minimal design stretching over thenominal input range of the j + 1 stage.
ADCs 25-35 Analog ICs; Jieh-Tsorng Wu
Quantized-Feedforward Redundant Design
A j A j
A j+1 A j+1+1
-1
-1/2
+1/2
0
Minimal+2
+1
Minimal+1
DAC
-3/4
-1/4
+1/4
+3/4
ADC DAC ADC+1-1 0 -1 0
• To increase the nominal input range, one can increase M, the number of comparatorsin the ADCs, and the corresponding output levels in the DACs.
• The minimal+2 design provides an over-range capability of ±∆A. The minimal+1design provides an over-range capability of ±∆A/2.
• It is also possible to avoid the over-range phenomenon by decreasing Gj .
ADCs 25-36 Analog ICs; Jieh-Tsorng Wu
Digital Encoding for the Quantized-Feedforward Architecture
Table
P+1
D1
1C
G1d
2A AA
3
3
C
Table
D
2Stage
P
P
Gd2
3
C
Table
D
Stage
2C
Table
2D
2Stage
P1Stage
iA
oD
Ai = Ada1 +
Ada2
G1+
Ada3
G1G2+ · · · +
AdaP
G1G2 · · ·GP−1+ Q
(Ai − Q) · Gd1 G
d2 · · ·G
dP−1
=
(((Ada
1
)Gd
1 + Ada2
Gd1
G1
)Gd
2 + Ada3
Gd1 G
d2
G1G2
)Gd
3 + · · · + AdaP
Gd1 G
d2 · · ·G
dP−1
G1G2 · · ·GP−1
ADCs 25-37 Analog ICs; Jieh-Tsorng Wu
Digital Encoding for the Quantized-Feedforward Architecture
Let
Cj = Adaj
(Dj ) ·G
d1 G
d2 · · ·G
dj−1
G1G2 · · ·Gj−1
The digital output can be obtained by
Do =((
(C1)Gd1 + C2
)Gd
2 + · · · + CP−1
)Gd
P−1 + CP
• Nonlinear A/D conversion occurs, if
Cj = Adaj
(Dj) ·G
d1 G
d2 · · ·G
dj−1
G1G2 · · · Gj−1
ADCs 25-38 Analog ICs; Jieh-Tsorng Wu
A Radix-2 1.5 Bit SC Pipeline Stage
Vj
1
1
2Vr x D j
2
1Vj+1
Vj
Vr x D j
Vj+1
Vj+1
A j
Vr0.25Vr0.25Vr0.75 Vr0.75
A j+1
Vr0.25
Vr0.5
Vr0.5
Vr0.25
D j
Vr0.25 Vr0.25
= −1, 0, +1D j
Conversion Phase 2
Conversioin Phase 1
C
0
0 0
1
1
DACADC
Minimal+1
C
C
f
g C
C
C
Cf
g
g
f
L
Encoder
ADCs 25-39 Analog ICs; Jieh-Tsorng Wu
A Radix-2 1.5 Bit SC Pipeline Stage
During phase 2
Vj+1 = Vj +C
g
Cf(Vj − Vr × Dj) =
(1 +
Cg
Cf
)(Vj −
Vr
1 + Cf/Cg× Dj
)
= 2 ×(Vj −
Vr
2× Dj
)if Cf = Cg
• The full range of the input/output is ±0.5Vr .
• The pipeline stage has input over-range capability of ±0.25Vr .
ADCs 25-40 Analog ICs; Jieh-Tsorng Wu
Multi-Bit Switched-Capacitor Pipeline Stage
Vj
g0
g1
C
1jD
0jDx
1f
rV
C
xrV
C
BankComparator
2
1j+1V
1
D
2
2
j
1
Dj = D0j· 20 + D1
j· 21 + · · ·DK
j· 2K−1 Dk
j∈ −1,0,+1
Cf
20=
Cg0
20=
Cg1
21= · · · = C
g(K−1)
2N−1= C
Vj+1 = Gj ×(Vj − ∆V × Dj
)Gj = 1 +
Cg0 + C
g1 + · · · + Cg(K−1)
Cf= 2K ∆V =
Vr
2K
ADCs 25-41 Analog ICs; Jieh-Tsorng Wu
Switched-Capacitor Pipelined ADCs
The SC stage has a voltage gain of
G = 1 +C
g
CfCg = Cg0 + Cg1 + Cg2 + · · ·
The settling time requirement can be expressed as
Ts =C
f + CL
Gm
(1 +
Cg
Cf+
Ci
Cf
)· ln 2y+1 ⇒ Gm =
Cf + C
L
Ts
(G +
Ci
Cf
)· (y + 1) ln 2
Other constraints are
Total Power ∝ Gm,1 + Gm,2 + · · · + Gm,P
Total Input Referred Thermal Noise Power = Pθ ∼ kT
[1
Cs1
+1
(G1)2Cs2
+1
(G1G2)2Cs3
· · ·]
ADCs 25-42 Analog ICs; Jieh-Tsorng Wu
Switched-Capacitor Pipelined ADCs
• Gm is the opamp’s transconductance.
• Ci is the opamp’s input capacitance.
• Csj = C
fj + C
g
jis the j -stage sampling capacitances.
• CL includes C
sj+1 and input loading of the comparator bank in the j + 1 stage.
• y (bits) is the resolution requirement of the j stage.
• Use capacitor scaling, α = Csj /C
sj+1, total power dissipation can be minimized while
maintaining noise performance. It can be shown that αopt ∼ G.
• Increasing G (and M) per stage generally reduces total power dissipation.
• Reference: D. Cline and P. Gray, “A Power Optimized 13-b 5Ms/s Pipelined ADC,”JSSC, March 1996, pp. 294–303.
ADCs 25-43 Analog ICs; Jieh-Tsorng Wu
Single-Stage Calibration and Digital Correction
0
1
CAL
c
ADC
Ajda
A
0
1
CAL
jA
jG
cD
jD
j+1A
zD
Z
DACADC
The signal Aj+1 is quantized the following Z-ADC with
Aj+1 = Gj ·[Aj − Ada
j(Dj) − Aos
j
]=
G
G· Dz + Qos + Q
• G/G is the gain error, Qos is the offset, and Q is the quantization error.
ADCs 25-44 Analog ICs; Jieh-Tsorng Wu
Single-Stage Calibration and Digital Correction
During calibration, Aj is disabled and Adaj (Dc) is quantized by measuring
Gj ·[Ac − Aos
]=
G
G· Dz1 + Qos + Q1
Gj ·[Ac − Ada
j(Dc) − Aos
]=
G
G· Dz2 + Qos + Q2
Subtracting the above two equations, we have
Gj · Adaj
(Dc) =G
G· (Dz1 − Dz2) + Q1 −Q2 =
G
G· Dz(Dc) + 2Qc(Dc) Dc ∈ Dj
⇒ Adaj
(Dc) =GjG
GjG· Tj(Dc) +
2Qc(Dc)
Gj
Tj(Dc) =Dz(Dc)
Gj
Dc ∈ Dj
ADCs 25-45 Analog ICs; Jieh-Tsorng Wu
Single-Stage Calibration and Digital Correction
The combined ADC with j-Stage and Z-ADC has the following characteristic:
Aj = Adaj
(Dj) + Aosj+Aj+1
Gj
=GjG
GjG· Tj(Dj) +
2Qc(Dj)
Gj
+ Aosj+Aj+1
Gj
=GjG
GjG
[Tj(Dj) +
Dz
Gj
]+
(Aosj+Q
os
Gj
)+
2Qc(Dj) +Q
Gj
=G′
G′· D′z + Q′os +Q′
Digital Output = D′z = Tj(Dj) +Dz
Gj
Gain Error =G′
G′=
GjG
GjG
Offset = Q′os = Aosj+Q
os
Gj
Quantization Error = Q′ =2Qc(Dj)
Gj
+Q
Gj
• Nonideal Adaj and Gj have no effect on the A/D linearity.
ADCs 25-46 Analog ICs; Jieh-Tsorng Wu
Multi-Stage Calibration and Digital Correction
DP-1D1
1T
G1d
X
x
xTTP-1T
P-1
Table
D
Stage
P
P
P
Table
AP+1
GdP-1 Gd
P
StageAP
D
Stage
T
Table
2A
2
Table
2D
2Stage
1Stage
Table
D
i Q xA
o
Assume the stage X ADC has a characteristic of
AP+1 =Gx
Gx
· Tx + Qosx + Qx
• Calibration is performed stage-by-stage, from Stage P to Stage 1.
ADCs 25-47 Analog ICs; Jieh-Tsorng Wu
Multi-Stage Calibration and Digital Correction
Use the X ADC to calibrate stage P . Then, the P + X ADC can be expressed as
AP =GPGx
GP Gx
[TP +
Tx
GP
]+
(AosP+Q
osx
GP
)+
2Qcx,P + Qx
GP
Use the P + X ADC to calibrate stage (P − 1). Then, the (P − 1) + P + X ADC can beexpressed as
AP−1 =GP−1GPGx
GP−1GP Gx
[TP−1 +
TP
GP−1+
Tx
GP−1GP
]
+
(AosP−1 +
AosP
GP−1
+Q
osx
GP−1GP
)+
2Qcx,P−1 + 2Qc
x,P +Qx
GP−1GP
Repeat the calibration procedures for stage (P − 2), (P − 3), . . . , 2, and 1.
ADCs 25-48 Analog ICs; Jieh-Tsorng Wu
Multi-Stage Calibration and Digital Correction
The full calibrated ADC can be expressed as
Ai =GT
GT
[T1 +
T2
G1+ · · · +
TP
G1G2 · · ·GP−1+
Tx
G1G2 · · ·GP
]+Qos
T+QT
where
GT
GT
=G1G2 · · ·GPGx
G1G2 · · · GP Gx
QosT
= Aos1 +
Aos2
G1
+ · · · +A
osP
G1G2 · · · GP−1
+Q
osx
G1G2 + · · · GP
QT =2Qc
x,1 + 2Qcx,2 + · · · + 2Qc
x,P + Qx
G1G2 · · · GP
≤(2P + 1) × |Qx|max
G1G2 · · · GP
ADCs 25-49 Analog ICs; Jieh-Tsorng Wu
Multi-Stage Calibration and Digital Correction
• The scaling factor GT/GT and offset QosT can be determined by quantizing two known
input, e.g., Ai = 0 and Ai = Aref .
• The effects of noise can be suppressed by averaging a number of successivemeasurements during calibration.
• During j stage calibration, to avoid overloading the Aj+1 port, different Adaj (Dc)
measurement may need different Ac value.
• On the circuit level, the effectiveness of calibration is limited by noises, interferences,nonlinear Gj , and amplifier transient behavior.
ADCs 25-50 Analog ICs; Jieh-Tsorng Wu
Calibration of A Radix-2 1.5 Bit SC Pipeline Stage
Vj
1
1
2Vr x D j
2
1Vj+1
Vc Vj+1
Vj+1
Vr x Dc
Vr0.25 Vr0.25
= −1, 0, +1D j
C
C
f
g
Calibration Phase 1
C
C
g
f
CC
Cf
g
Calibration Phase 2
L
Encoder
• To calibrate Adaj (Dj = 1). Obtain Dz1 by letting Vc = 0.25Vr and Dc = 0, and obtain Dz2
by letting Vc = 0.25Vr and Dc = 1. Then Tj(Dj = 1) = (Dz1 − Dz2)/Gj .
• To calibrate Adaj (Dj = −1). Obtain Dz1 by letting Vf = −0.25Vr and Dc = 0, and obtain
Dz2 by letting Vc = −0.25Vr and Dc = −1. Then Tj(Dj = −1) = (Dz1 − Dz2)/Gj .
ADCs 25-51 Analog ICs; Jieh-Tsorng Wu
A Radix-2 Cyclic ADCs
jD
Vi
VR VR
j+1 VjVx 2S/H
Vj+1 = 2 × Vj − Dj × VR = 2 ×(Vj + Dj ·
VR
2
)Dj ∈ +1,−1
• Start with j = 1 and V1 = Vi .
• For each cycle, j is increased by 1.
ADCs 25-52 Analog ICs; Jieh-Tsorng Wu
A Radix-2 Switched-Capacitor Cyclic ADC
S2
S1Vi
C1
1A
C6
S4
2
VR C3C5
2
C S6
S3 4
Dj
C
3A
S5
A
C1 = C2 = C3 = C4 = C
C5 = 2C
Dj ∈ 1,0
Vi = VR ×
N∑
j=1
(Dj · 2−j
)− 1
2
ADCs 25-53 Analog ICs; Jieh-Tsorng Wu
A Radix-2 Switched-Capacitor Cyclic ADC
Dj+1
j-Cycle (2)j-Cycle (1)
Input Sampling (2)Input Sampling (1)
C1
1A
C6
C3C5
3A
D1
C2
C1
A
1A
C6
3
V
4C C
V
x RVj
C3C5
5
2
3A
Dx RVjD
3
Vi
3
3C
A
2A
C
1
6
A
C
j
2A
1
2A
A
5C
6
C
A
C
2
C1
C
1 j+1
ADCs 25-54 Analog ICs; Jieh-Tsorng Wu
A CMOS Subranging Flash ADC — Dingwall
M-ADC
Comparator BankL-ADC
RV
KV KV
iV
Comparator Bank
11
2
3 1
1
3 1
1
3 1
1
3 1
1
1
2
1
1
2
1
ADCs 25-55 Analog ICs; Jieh-Tsorng Wu
A CMOS Subranging Flash ADC — Dingwall
• Two-Stage quantized-feedforward architecture.
– The first-stage M-ADC has 2M − 1 comparators, and G1 = 1.– The second-stage L-ADC has 2L − 1 comparators.– For minimal design, Do has N = M + L bits.
• The S/H and the subtractor function is embedded in every comparator. Require noadditional subtractor or DAC.
• Comparators in both M-ADC and L-ADC need to have N-bit accuracy.
• The input range of the L-ADC can be extended to prevent over-loading. The accuracyrequirement for the M-ADC can then be relaxed.
• Reference: A. Dingwall, et. al., “An 8-MHz CMOS Subranging 8-Bit A/D Converter,”JSSC 12/1985, pp. 1138–1143.
• The voltage ranges are Cin+ − Cin− = [−2↔ +2] and Fin+ − Fin− = [0↔ +2].
• The absolute-value processing reduces the number of switches in the AMUXs by half.In addition, the settling time of the AMUX outputs is also reduced due to the reductionin output voltage swing and output capacitive loading.
• The interpolation scheme can reduce the number of “taps” from the reference ladderand reduce the number of preamplifiers. It also attenuates front-end sources of DNL,such as mismatches in the input sampling switches and resistor mismatch in thereference ladder.
• Reference: B. Brandt, et. al., “A 75-mW, 10-b 20-MSPS CMOS Subranging ADC,”JSSC 12/1999, pp. 1788–1795.
ADCs 25-59 Analog ICs; Jieh-Tsorng Wu
Flash Quantization Architecture
7530 1
Thermometer Code
11111111
11111110
11111100
11111000
11110000
11100000
11000000
10000000
00000000
7
6
5
Vi
VRB VRT
oDN
V2 V4 V6V0
V0 V6
Vi
V2 V4
4
3
2
4
1
6
1
2
0
0 2 3 4 5 6 7
Thermometer-to-Binary Encoder
ADCs 25-60 Analog ICs; Jieh-Tsorng Wu
Resistor-String Interpolation
Thermometer Code
11111111
11111110
11111100
11111000
11110000
11100000
11000000
10000000
00000000
7
6
5
4
3
2
1
0
Thermometer-to-Binary Encoder
7
Vi
VRB6543210
60 42
VRT
oDN
V2 V4 V6V0
V0 V6
Vi
V2 V4
ADCs 25-61 Analog ICs; Jieh-Tsorng Wu
Folding
0000
0001
0011
0111
1111
1110
1100
1000
0000
Circular Code
7
6
5
4
3
2
1
0
NCircular-to-Binary Encoder
Vi
VRTVRB
0 65 3 7
oD
4
8
V2V1V0 V3
V0 V1 V2 V3
Vi
7654
1 2
0 1 2 3
ADCs 25-62 Analog ICs; Jieh-Tsorng Wu
Interpolation and Folding
• The number of latch comparators is reduced by folding, while the number of foldingblocks is reduced by interpolation.
• The interpolation can reduce the input capacitances for Vi , VRT , and VRB, since thenumber of the preamplifers is reduced.
• The interpolation can improve the DNL, due to the redistribution of mismatch errors.
• The interpolation technique can also be used with other types of signals, such ascurrents and charges.
• The folding circuit need only to be accurate near the zero-crossing points.
ADCs 25-63 Analog ICs; Jieh-Tsorng Wu
Averaging Preamplifiers
I
R R R R
R RRR
I I
VSS VSS VSS
VDDVDD VDD
• The outputs are connected by interpolating resistor string.
• Gain is determined by R × I .
• Speed is determined by R × C.
ADCs 25-64 Analog ICs; Jieh-Tsorng Wu
Effects of Averaging
Input and Reference R-String
m = 5
Input Range
I o
Vi
Averaging R-String
• Differential nonlinearity (DNL) improves with m.
• Integral nonlinearity (INL) improves with√m.
ADCs 25-65 Analog ICs; Jieh-Tsorng Wu
Bending at the Edges Due to Averaging
Vi
Do
Averaging R-String
Input and Reference R-String
Use Resistor-Ring to Mitigate Edge Effect
ADCs 25-66 Analog ICs; Jieh-Tsorng Wu
Cascaded Folding
Vi
Dc
Input and Reference R-String
Averaging Resistor Ring and 3X Folding
Averaging Resistor Ring and 3X Folding
M-ADC
• Too many folding in one stage can cause gain-loss.
• Require odd number of single-stage folding to maintain continuity.
ADCs 25-67 Analog ICs; Jieh-Tsorng Wu
Differential Preamplifier
M7
M2M1
oV
M6M5 M4M3
BNV
Vi
VSS
VDD
Adm = gm1 ·1
gm3 − gm5
Acm =gm1
1 + 2gm1ro7· 1gm3 + gm5
• Additional common-mode feedback is not required.
ADCs 25-68 Analog ICs; Jieh-Tsorng Wu
A CMOS 10-Bit Folding ADC — Bult
• Reference: K. Bult, et. all, “An Embedded 240-mW 10-b 50-MS/s CMOS ADC in1-mm2,” JSSC 12/1997, pp. 1887–1895.
ADCs 25-69 Analog ICs; Jieh-Tsorng Wu
Time-Interleaved Architectures
φ
φ
1
φ
φ2
Nt
φφ
m
S/H21
Do
A i
S/H
m
S/H
cT
m
N N
Multiplexer
ADC ADC
1
N
ADC
2
• The equivalent sampling rate is m/Tc.
• Clock phase as well as clock jitter need to satisfy N-bit accuracy.
• Any mismatch among the converter characteristics, including offset and gain, canappear as noises and/or spurious tones in Do.
ADCs 25-70 Analog ICs; Jieh-Tsorng Wu
Oversampling Converters
Jieh-Tsorng Wu
July 16, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Sampling and Quantization
e(k)f s
f Bf B
S e (f)
f s /2f s /2
Quantizer
N−Bit
x(k)
x(k) y(k)
e(k)
x(t)
/2 /2
pdf of e(k)
0f
y(k)D(z)
D(z)
| D(f) |
e(k) is a quantization noise due to the quantization process. With an ideal quantizer withstep size ∆, The pdf of e(k) is assumed to be uniformly distributed over −∆/2 and +∆/2.
• In practice, the first accumulation is often clipped at ±2, and the second effectively±4.
Oversampling 26-13 Analog ICs; Jieh-Tsorng Wu
Overloading in a Second-Order ∆Σ Modulator
• D/A levels are ±0.5,±1.5, and ±2.5.
• ∆ is the same for allthree cases.
• For large x, the input to the quantizer can be so large that |e| > ∆/2. The excessnoise can degrade the SNR of y .
• In the two-level case (1-bit quantization), the comparator is theoretically overloadedfor all conditions, except zero input with zero initial conditions.
Oversampling 26-14 Analog ICs; Jieh-Tsorng Wu
Oversampling ADCs
Sampling
x c (t)
x c (t)
yp (n)y(n)x(n)
AliasingAnti−
Filter Modulator∆Σ Digital
Low−PassFilter
Decimation Filtersf
0t
0 sss2T 4T 6T
y (n)b
L
0 2π
x(n)
0n
1 2 3 4 5 6
Ω
ω
Ωb Ωs
Xc(jΩ)
X(ejω)
Oversampling 26-15 Analog ICs; Jieh-Tsorng Wu
Oversampling ADCs
yp (n)
0 2π
0 2π 4π
0n
0n
1 2 3 4 5 6
321
y (n)b
y(n)
0 2π
n
ω
ω
ω
Y(ejω)
Yp
(ejω)
Yb
(ejω)
Oversampling 26-16 Analog ICs; Jieh-Tsorng Wu
Oversampling DACs
D/A
(n)xp
x b (n)
Digital
FilterAnalog
yc (t)y (t)y(n)
Modulator∆Σ
Filter
InterpolationLow−Pass
x(n)
00n
321
(n)xb
2π
0 2π 4π0
x (t)p
1 2 3 4 5 6n
d
L
sf
ω
ω
Xb
(ejω)
Xp
(ejω)
Oversampling 26-17 Analog ICs; Jieh-Tsorng Wu
Oversampling DACs
s2T s4T s6T
0n
x(n)
1 2 3 4 5 6 0 2π
0 2π
0
t
d (t)y
0
n
y(n)
Ω
ω
ω
X(ejω)
Y(ejω)
Ωb Ωs
Yd (jΩ)
Oversampling 26-18 Analog ICs; Jieh-Tsorng Wu
Oversampling DACs
s2T s4T s6T
0 2π
0t
0
c (t)y
0
t
d (t)y
0
n
y(n)
Ω
Ω
ω
Y(ejω)
Ωb
Ωb
Ωs
Ωs
Yd (jΩ)
Yc(jΩ)
Oversampling 26-19 Analog ICs; Jieh-Tsorng Wu
General Single-Stage ∆Σ Modulator
y(k)x(k) G(z)
F(z)
Y (z) =G(z)
1 + F (z)G(z)· X (z) +
11 + F (z)G(z)
· E (z) = STF (z) · X (z) +NTF (z) · E (z)
• OSR is typically between 16 and 256.
• The loop gain, L(z) = F (z)G(z), need to be high in the band of interest.
• The poles L(z) are the zeros of NTF (z).
• Both STF (z) and NTF (z) generally share the same poles, the roots of 1 + L(z) = 0.
Oversampling 26-20 Analog ICs; Jieh-Tsorng Wu
General Single-Stage Error-Feedback Coder
y(k)x(k)
e(k)N(z) − 1
Y (z) = X (z) + N(z) · E (z)
• A slight coefficient error can degrade noise-shaping significantly.
• Not suitable for analog modulators, only appropriate for digital modulators.
Oversampling 26-21 Analog ICs; Jieh-Tsorng Wu
Single-Stage High-Order Modulators
z 1z 1
1 z 1z 1
1 z 1z 1
1
5a
z 1z 1
1z 1z 1
1x(k)
aaaa 1 2 3 4
1 2
y(k)
c c
• An Nth-order noise-shaping modulator improves the SNR by (6N + 3) dB/octave, orequivalently, (N + 0.5) bits/octave.
Oversampling 26-22 Analog ICs; Jieh-Tsorng Wu
Single-Stage High-Order Modulators
If c1 = c2 = 0,
L(z) = G(z) =a1
(z − 1)1+
a2
(z − 1)2+
a3
(z − 1)3+ · · ·
NTF (z) =1
1 + L(z)=
(z − 1)n
D(z)STF (z) = 1 − NTF (z)
• L(z) has all its poles at z = 1 (or f = 0).
• NTF (z) has all its zeros at z = 1 (or f = 0).
• Butterworth high-pass filters are often used for NTF (z).
• STF (z) contains peaking at high frequencies.
If c1 = 0 and c2 = 0, the poles of L(z) can be moved away from z = 1 along the unitcircle.
Oversampling 26-23 Analog ICs; Jieh-Tsorng Wu
Single-Stage High-Order Modulators
z 1z 1
1 z 1z 1
z 1z 1
1z 1z 1
c 1
z 1z 1
1
c 2
1b b 2 b 4 b 5b 3
a 1 a 2 a 3 a 4 a 5
1 1
y(k)
x(k)
Oversampling 26-24 Analog ICs; Jieh-Tsorng Wu
Single-Stage High-Order Modulators
If c1 = c2 = 0,
L(z) =a1
(z − 1)n−0+
a2
(z − 1)n−1+
a3
(z − 1)n−2+ · · ·
G(z) =b1
(z − 1)n−0+
b2
(z − 1)n−1+
b3
(z − 1)n−2+ · · ·
NTF (z) =1
1 + L(z)=
(z − 1)n
D(z)STF (z) =
b1 + b2(z − 1) + b3(z − 1)2 + · · ·D(z)
• The numerator of STF (z) is arbitrary, but has an order that is one less than D(z).
• The STF (z) does not contain significant peaking.
• Each integrator output contain significant amounts of the input signal as well asfiltered quantization noise.
If c1 = 0 and c2 = 0, the poles of L(z) can be moved away from z = 1 along the unitcircle.
Oversampling 26-25 Analog ICs; Jieh-Tsorng Wu
Stability of Single-Stage High-Order Modulators
αG(z)
F(z)
e(k)
Quantizer
x(k)
Re(z)
Im(z)
y(k)
Y (z) =αG(z)
1 + αG(z)F (z)· X (z) +
11 + αG(z)F (z)
· E (z)
• A modulator is called stable, if the input to the quantizer does not become overloaded,i.e., e(k) ≤ ±∆/2.
• All high-order modulators (N > 2) are conditionally stable.
• Modulators with multi-bit quantizer and DAC exhibit improved stability.
Oversampling 26-26 Analog ICs; Jieh-Tsorng Wu
Stability of Single-Stage High-Order Modulators
For single-stage modulators with one-bit quantizer and DAC:
• As a general rule of thumb, stability can be achieved by keeping∣∣∣NTF
(ejω)∣∣∣ ≤ 1.5.
• A modulator can be made more stable by placing the poles closer to the zeros inNTF (z). But, the SNR is also degraded since the out-of-band gain of NTF (z) is alsoreduced.
• Stability is also related to the input signal level. Typically want 50–80% of ∆ for stableinput range.
• “Signal overload” and “power on” may cause a conditionally stable modulator tooscillator. Need additional mechanism to detect instability and force the loopbecoming stable.
• In above examples, e is periodic and nowhere near white. Different initial states justshift the sequence and the values of e.
• For bounded input |u| < 1, x is rational⇔ y is periodic.
• Low-frequency tones cannot be filtered out by the following decimation filter.
• Tones also exists in higher-order modulators. The tones might not lie at a singlefrequency but instead be short-term periodic patterns.
• Nearly all types of modulators can produce very high-powered tones near fs/2. Clocknoise near this frequency can couple and demodulate these tones down into thebaseband.
• For ac input, strong peaks and dips in the output noise power may be seen for certaininput frequencies and amplitudes.
Oversampling 26-33 Analog ICs; Jieh-Tsorng Wu
Noise-Shaped Dithering for Single-Stage Modulators
x(k) G(z)
F(z)
y(k)
d(k)
• d (k) is a pseudo-random noise. It is usually generated by a PN sequence generator.
• The power d (k) must be comparable to that of e(k). The pdf of d (k) usually spansmore than ∆/2.
• d (k) may require 3–8 quantization levels for effective dithering.
Oversampling 26-34 Analog ICs; Jieh-Tsorng Wu
Noise-Shaped Dithering for Multi-Stage Cascaded Modulators
1z
2 (k)d
D/A
1z 1 1z 1 1z
z 1
y (k)2
1 1z
1z
D/A
y1 (k)
1 (k)e
x(k)
(k)d 1
y(k)
Y1 = z−1X +(1 − z−1)2
E1 +(1 − z−1)3
D1 Y2 = z−1E1 +(1 − z−1)E2 +
(1 − z−1)D2
Y = z−1Y1 −(1 − z−1)2
Y2 = z−2X + z−1 (1 − z−1)3D1 −
(1 − z−1)3
D2
Oversampling 26-35 Analog ICs; Jieh-Tsorng Wu
Multi-Bit ∆Σ Modulator
x(k) G(z)
F(z)
A/D Converter
y(k)
D/A
n(k)
e(k)
x(k) G(z)
F(z)
y(k)
D/A Converter
D/A y(t)
n(t)
e(k)
Oversampling 26-36 Analog ICs; Jieh-Tsorng Wu
Multi-Bit ∆Σ Modulator
For the A/D converter
Y (z) =G(z)
1 + F (z)G(z)X (z) +
11 + F (z)G(z)
E (z) − F (z)G(z)
1 + F (z)G(z)N(z)
≈ STF (z)X (z) +NTF (z)E (z) − N(z)
• Out-of-band noise is reduced. Requirements for the analog circuitry are less severe.
• Since they have better stability, more aggressive noise transfer functions may beused.
• The DAC linearity errors are not shaped. The DAC must be nearly as linear as thecomplete converter.
Oversampling 26-37 Analog ICs; Jieh-Tsorng Wu
Multi-Bit DAC — Dynamic Element Matching
Unit Elements
A o
A oAnalogOutput1
2
M
MRandomizer
v
0 1 2 3 4
v
Oversampling 26-38 Analog ICs; Jieh-Tsorng Wu
Multi-Bit DAC — Dynamic Element Matching
freq
Signal Signal
nfreq
n
Random ScramblingNo Scrambling
• For any value of v , the averaged error in Ao is zero.
• Whitens the mismatch noise.
• The randomizer may consists of a thermometer-type encoder, a random-numbergenerator, and a switchbox. Butterfly structure is often used to simplified theswitchbox design.
• Reference: Ian Galton, “A Rigorous Error Analysis of D/A Conversion with DynamicElement Matching,” Tran. on Circuits and Systems–II, pp. 763–772, 12/95.
Oversampling 26-39 Analog ICs; Jieh-Tsorng Wu
Multi-Bit DAC — Data-Weighted Averaging
A oAnalogOutput1
2
M
MDWASelector
v(k)
freq
Signaln
DWA Scrambling
v(1)=3 v(2)=4 v(3)=2
Oversampling 26-40 Analog ICs; Jieh-Tsorng Wu
Multi-Bit DAC — Data-Weighted Averaging
• Once every element in the array has been used, the cumulative error is zero. Theerrors induced by the use of each element are averaged out as soon as possible.
• Reference: R. Baird and T. Fiez, “Linearity Enhancement of Multibit ∆Σ A/D andD/A Converters Using Data Weighted Averaging,” Tran. on Circuits and Systems–II,pp. 753–762, 12/95.
Oversampling 26-41 Analog ICs; Jieh-Tsorng Wu
Multi-Bit DAC — Noise-Shaped Scrambler
A oAnalo gOutpu t
Unit Elements
1
2
3
4
Therm.Code
v(k)
Swapper Cells
• Each swapper tries to equalize the activity of each of its outputs. Each output fromthe scramble is a first-order noise-shaped sequence.
• Reference: R. Adams, et al, “A 113dB SNR Oversampling DAC with SegmentedNoise-Shaped Scrambling,” ISSCC, pp. 62–63, 2/98.
Oversampling 26-42 Analog ICs; Jieh-Tsorng Wu
General Mismatch-Shaping DAC
min()
QuantizerVector
M Unit Elements A o
H2 (z) − 1
su
Element Selection Logic
se
sy
sv
v
M
Mde
sx
Oversampling 26-43 Analog ICs; Jieh-Tsorng Wu
General Mismatch-Shaping DAC
• The element selection logic (ESL) is a collection of M digital ∆Σ modulators, eachpossessing a NTF (z) equal to H2(z), implemented with the error feedback structureand supplied with a common input.
• The vector quantizer uses information in the sy vector to select which v elements toenable. Want to minimize se = sv − sy .
• The sy = sx −min(sx ) · [11 · · · 1] function is a shifting operation which set the minimumcomponent in sy to zero. The purpose is to reduce the magnitude of sy vector, in amanner that does not disturb the noise-shaping property of the selection logic.
Oversampling 26-44 Analog ICs; Jieh-Tsorng Wu
General Mismatch-Shaping DAC
Let de = [e1, e2, · · · , eM] be the DAC error vector.
• By definition, de · [0]T = 0 and de · [1]T = 0, where [0] = [00 · · ·0] and [1] = [11 · · ·1].
• de · (sv1 + sv2)T = de · sv T1 + de · sv T
2
• de · sv T + de · svT= 0
For the error-feedback structure, we have
SV(z) = SU(z) · [1] + H2(z) · SE(z)
Oversampling 26-45 Analog ICs; Jieh-Tsorng Wu
General Mismatch-Shaping DAC
The vector quantizer obeysSV(z) · [1]T = V (z)
The analog output is
Ao(z) = SV(z) · ([1] + DE)T
= SV(z) · [1]T + SV(z) · DET
= V (z) + SU(z) · [1] · DET + H2(z) · SE(z) · DET
= V (z) + H2(z)(
SE(z) · DET)
Oversampling 26-46 Analog ICs; Jieh-Tsorng Wu
General Mismatch-Shaping DAC — First-Order Example
• For the single-stage design, δ1 = 0.001, δ2 = 0.00001, then N = 6250. For thetwo-stage design, δ1 = 0.001/2, δ2 = 0.00001, then N1 = 291 and N2 = 205.
• Practical considerations sometimes lead to the conclusion that a two-stage design isbest.
• For most cases, the choice of 2 : 1 for the last stage is both the theoretically bestoption as well as the most practical one.
Oversampling 26-54 Analog ICs; Jieh-Tsorng Wu
sinc k Filters
z 1 z 1f s
x(n)z 1
f s
/M2π /M4π /M8π
sinc
1f s
x(n)
f s
f s
x(n)
f s
x(n)
f s
f s /M
y(m)
z 1 z 1
z 1 z 1
z 1 z 1
1 2 M−1
/M
y(m)M
sinc
0 πω
1
/M
y(m)sinc sinc
2 k
z M/M
y(m)
M
z M M
M
Oversampling 26-55 Analog ICs; Jieh-Tsorng Wu
sinc k Filters
The sinc filter transfer function is
H1(z) =1M
M−1∑i=0
z−1 =1M
(1 − z
−M
1 − z−1
)
H1
(ejω)=
1M·sin(ωM/2)
sin(ω/2)=
sinc(ωM/2)
sinc(ω/2)sinc(x) =
sin(x)x
The sinck filter transfer function is
H(z) = [H1(z)]k =1
Mk
(1 − z
−M
1 − z−1
)k
=1
Mk·(
1
1 − z−1
)k·(1 − z−M
)k
• The integrator-differentiator architecture is inherently stable, when 2’s-complementarithmetic is used due to its wrap-around characteristic.
Oversampling 26-56 Analog ICs; Jieh-Tsorng Wu
Phase-Locked Loops
Jieh-Tsorng Wu
July 16, 2002
A
1896
E S National Chiao-Tung UniversityDepartment of Electronics Engineering
Phase-Locked Loops (PLLs)
A Vi c
oAFilter
PhaseDetector
LoopVFO
Ai = g1 (ωit + θi) Ao = g2 (ωot + θo) ωo = ωoo + Kc · Vc
• g1 and g2 are periodic functions with 2π period.
• When the loop is locked, the frequency of the VCO is exactly equal to the averagefrequency of the input.
• The loop filter is a low-pass filter that suppresses high-frequency signal componentsin the phase difference.
PLLs 27-2 Analog ICs; Jieh-Tsorng Wu
Phase-Locked Loops (PLLs)
Applications:
• Automatic frequency control.
• Frequency and phase demodulation.
• Data and clock recovery.
• Frequency synthesis.
References:
• Roland E. Best, “Phase-Locked Loops,”, 2nd Edition, McGraw-Hill, Inc., 1993.
• Dan H. Wolaver, “Phase-Locked Loop Circuit Design,” Prentice-Hall, Inc., 1991.
• Floyd M. Gardner, “Phaselock Techniques,” 2nd Edition, John Wiley & Sons, 1979.
• SNR is the signal-to-noise ratio, and can be expressed as
SNR ≡V
2s /2
n2
PLLs 27-13 Analog ICs; Jieh-Tsorng Wu
Phase Noise
PowerSpectralDensity
Freq
Ps
Pssb
L(fm)
fo
fm
v(t) = Vs sin [2πfot + θn(t)]
PLLs 27-14 Analog ICs; Jieh-Tsorng Wu
Phase Noise
• The phase noise L(fm), usually in dBc, is the ratio of the single-sideband (SSB) powerin a 1-Hz bandwidth fm Hz away from the carrier to the total signal power, i.e.,
L(fm) ≡Ps
Pssb
• Let Sθn(f ) be the power spectral density of θn(t) in frequency domain, it can be shown
For a 2nd-order PLL with active filter, F (0)→∞, thus ∆ωH →∞.
PLLs 27-20 Analog ICs; Jieh-Tsorng Wu
PLL Tracking Performance — Pull-Out Range
The pull-out range ∆ωPO is the frequency-step limit below which the PLL does not skipcycles but remains in lock.
• For a sinusoidal PD
∆ωPO = 1.8ωn(ζ + 1) for 0.5 < ζ < 1.4
PLLs 27-21 Analog ICs; Jieh-Tsorng Wu
Noisy PLL Tracking Performance
Define the SNR of a PLL as
SNRL ≡1
2θ2n,o
• As a rule of thumb, SNRL > 6 dB is required for stable operation.
For low SNRL, the VFO phase occasionally slips one or more cycles as compared to theinput. Define TAV as the average time between cycle slips.
• For a 1st-order loop TAV ≈ π4BL
e4SNRL, where BL is the PLL noise bandwidth.
• For a 2nd-order loop with ζ = 0.707 TAV ≈ 1BLeπSNRL.
• The slips of a 1st-order loop are almost always single, isolated events.
• The slips in a 2nd-order loop tend to bunch in bursts.
PLLs 27-22 Analog ICs; Jieh-Tsorng Wu
PLL Acquisition Behavior
i VoV F(s)Phase
Detector
VFOLoop Filter
• The process of bringing a PLL into lock is called acquisition.
• Acquisition is inherently a nonlinear phenomenon.
• An nth-order PLL contains n integrators (VFO, capacitors, . . . ). With each integratorthere is associated a state variable of the loop: phase, frequency, frequency rate,and so on. To force the loop into lock, it is necessary to bring each of the statevariables close to the corresponding parameters of the input signal. Therefore, weshould speak of phase acquisition, frequency acquisition, and so forth.
PLLs 27-23 Analog ICs; Jieh-Tsorng Wu
Phase Acquisition of a First-Order Loop
ViVd
VoPhase
Detector
VCO
θe
θeKoKd
∆ωKoKd− sinθe
Vd = Kd · sinθe ωo = ωoo + Ko · Vd θe = θi − θo
θe = θi − θo = ωit −ωoot −∫ t
0KoKd sinθedt − θo(0)
⇒dθe
dt= θe = ∆ω − KoKd sinθe ∆ω = ωi −ωoo
• The loop is locked when θe = 0.
• There is no cycle skipping in the acquisition process.
PLLs 27-24 Analog ICs; Jieh-Tsorng Wu
Phase Acquisition of a Second-Order Loop
The lock-in range, ∆ωL, is the frequency range over which the PLL can acquire lockwithout cycle slipping.
By practical considerations, the lock-in process of a higher-order loop isso fast that it can be approximated bythe phase acquisition process of a 1st-order loop with gain K = KoKdF (∞).
log f
log |F (j f )|
F (∞) = τ2τ1
• For a PLL with with sinusoidal PD,
Lock-In Range = ∆ωL ≈ KoKdF (∞) = 2ζωn Lock-In Time = TL ≈1ωn
PLLs 27-25 Analog ICs; Jieh-Tsorng Wu
Frequency Acquisition — The Pull-In Process
The pull-in range, ∆ωP , is themaximum initial frequencyoffset for the pull-in processto occur.
t
∆ω
ωi
ωo
Tp
• For a 2nd-order PLL,
Pull-In Range = ∆ωP ≈8π
√ζωnKoKd −ω2
n ≈8π
√ζωnKoKd if KoKd ωn
Pull-In Time = Tp ≈∆ω
2
2ζω3n
PLLs 27-26 Analog ICs; Jieh-Tsorng Wu
Aided Frequency Acquisition — Frequency Sweeping
Vi LoopFilter
PhaseDetector
DetectorLock Sweep
Generator
VFO
• Use sweep to bring the VFO close to the frequency of locking.
PLLs 27-27 Analog ICs; Jieh-Tsorng Wu
Aided Frequency Acquisition — Loop Filter Switching
Vi PhaseDetector
DetectorLock
VFO
Low R if unlocked; High R if locked
Loop Filter
Low R
High R
• The frequency pull-in can be painfully slow in a narrowband loop. Sometimes, a widerloop bandwidth is preferred.
PLLs 27-28 Analog ICs; Jieh-Tsorng Wu
Aided Frequency Acquisition — Dual Loops
iV LP
LP
Detector Filter 1
Filter 2
Phase
VFO
DetectorFrequency
• Contains a phase-locked loop (PLL) and a frequency-locked loop (FLL).
• The FLL should dominate during frequency acquisition.
• The PLL should dominant when the phase is locked.
PLLs 27-29 Analog ICs; Jieh-Tsorng Wu
Digital Phase-Locked Loops (DPLLs)
oVViVd VcF(s)
1/N
PD
Loop Filter
VFO
Frequency Divider
To calculate loop dynamics, combine the VFO and the frequency divider as a new VFO.
ωo = ωoo + Ko · Vd ⇒ ω′o =ω
N=
ωoo
N+Ko
N· Vd = ω′oo + K ′o · Vd
ω′oo =ωoo
NK ′o =
Ko
Nθ′o =
θo
N
• θi and θo are not available except during the rising and falling transitions.
PLLs 27-30 Analog ICs; Jieh-Tsorng Wu
XOR Phase Detector
u1
u2
Q
u1
u2Q
0
u1
u2
Q
u1
u2
Q
Averaged Q
θeπ2
π−π2
−π
• The PD characteristic is strongly dependent on the duty-cycle of u1 and u2.
PLLs 27-31 Analog ICs; Jieh-Tsorng Wu
Edge-Triggered Set-Reset Phase Detector
S
RQ
u1
u2
Q
u1
u2
Q
u2
u1u1
u2
Q
Frequency Discrimination Capability
0
Averaged Q
u1
u2
Q
u1
u2
Q
θeπ 2π−π−2π
PLLs 27-32 Analog ICs; Jieh-Tsorng Wu
Edge-Triggered Set-Reset Phase Detector
• The PD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.
• If f1 f2 or f1 f2, the PD has frequency discrimination capability, which canimprove frequency acquisition speed of the PLL.
• However, when f1 ≈ f2, the frequency-sensitive behavior is lost, and the PLL relys onthe pull-in process for frequency acquisition.
PLLs 27-33 Analog ICs; Jieh-Tsorng Wu
Sequential Phase-Frequency Detector (PFD)
RQD
u1
u2
UP
0
u1
u2
UP
Averaged (UP-DW)
RD Q
1
1
u1
u2
UP
DNDN
DN
θe
π 2π−π−2π
PLLs 27-34 Analog ICs; Jieh-Tsorng Wu
Sequential Phase-Frequency Detector (PFD)
• The PFD is edge-sensitive, the duty-cycle of u1 and u2 is irrelevant.
• The PFD can discriminate the frequency difference for even the smallest f1 − f2.
• A PLL with the PFD can have infinite pull-in range. The frequency acquisition aidprovided by the PFD is akin to frequency sweeping.
• When using the PFD, a missing transition or an extra one in either u1 or u2 can causea large error signal to appear. The effects will propagate for more than one cycle.Great caution is required to use the PFD in a noisy environment.
PLLs 27-35 Analog ICs; Jieh-Tsorng Wu
Charge-Pump Phase-Locked Loops
ViVo
Vc
IP
IP
IeUP
PFD
R
C
VFO
DN
u1
u2
The “on” time of either UP or DN is tp = |θe|/ωi for each period 1/fi of the input signal.The average error current Ie over a cycle is
Ie = IP ×tp
Ti= IP ×
θe
2πωi = 2πfi =
2πTi
PLLs 27-36 Analog ICs; Jieh-Tsorng Wu
Charge-Pump Phase-Locked Loops
The voltage Vc can be expressed as
Vc(s) = Ie(s)(R +
1sC
)= θe(s) ×
IP
2π
(R +
1sC
)Vc(s)
θe(s)= KdF (s) =
IP
2π
(R +
1sC
)
The VFO has the following characteristic:
ωo = ωoo + Ko · Vc ⇔ fo = foo + K ′o · Vc K ′o =Ko
2π
Using the continuous-time approximation, we have
θe(s)
θi(s)= He(s) =
s2
s2 + 2ζωns +ω2n
θo(s)
θi(s)= H(s) = 1 − He(s)
ωn =(K ′o ×
IP
C
)1/2
ζ =12
[K ′o × (IP R) × (RC)
]1/2
PLLs 27-37 Analog ICs; Jieh-Tsorng Wu
Charge-Pump Phase-Locked Loops
• The PLL behaves as a 2nd-order loop with active lag-lead filter.
• Discrete-time model can be used for more accurate analysis. Reference: Hein, z-Domain Model for Discrete-Time PLLs, Trans. CAS, 11/88, pp. 1393–1400.
• During the pump interval tp, a voltage step of IP R occurs at the VFO input. Thisgranularity effect may be intolerable in some systems.
• The voltage step IP R may overload the VFO, making the previous linear analysisinvalid.
• The granularity effect can be mitigated with an additional capacitor Cp in parallel withthe earlier RC network, thus forming a 3rd-order PLL.
• The dead zone is caused by the slowness of the S1 and S2 switches.
PLLs 27-39 Analog ICs; Jieh-Tsorng Wu
PFD and Charge-Pump Filter
• When θe falls in the dead zone, the PFD’s conversion gain is decreased, causing areduction in ωn and ζ , and the degradation of θo phase noise.
• The dead zone can be eliminated by allowing UP and DN to be activatedsimultaneously for a short time even if the phase difference is zero. Then, anymismatch between IP 1 and IP 2 can cause a phase offset and consequently spursin the output spectrum.
• The finite output impedance of the IP 1 and IP 2 current sources can also cause phaseoffset.
• Charge sharing in the S1 and S2 switches can also cause glitches at Vc.
PLLs 27-40 Analog ICs; Jieh-Tsorng Wu
PFD with Delayed Reset
DN
UP
u2
u1
Delay
PLLs 27-41 Analog ICs; Jieh-Tsorng Wu
Third-Order Charge-Pump PLLs
IP
IP
Ie VcUP
DN 0R1
C1C2
ωωz
ωtωp
|L(jω)| (dB)
The loop filter transfer function is
Vc(s)
θe(s)= KdF (s) =
IP
2π
[(R1 +
1sC1
)‖ 1sC2
]=
IP
2πs(C1 + C2)×
sR1C1 + 1
sR1(C1‖C2) + 1
ωz =1
R1C1ωp =
1
R1(C1‖C2)
PLLs 27-42 Analog ICs; Jieh-Tsorng Wu
Third-Order Charge-Pump PLLs
The loop gain of the 3-order PLL is
L(s) =Ko
s× KdF (s) =
K′oIP
s2(C1 + C2)×
s/ωz + 1
s/ωp + 1
Let ωt/ωz = α > 1 and ωp/ωt = β > 1, then
ωt ≈K′oIP
(C1 + C2)ωz
= K ′o · IP R1 ·C1
C1 + C2
R1 =1
K ′oIP·ωt C1 = K ′oIP ·
α
ω2t
C2 = K ′oIP ·1
β ·ω2t
• α = 4 and β = 4 gives a phase margin ≈ 60.
PLLs 27-43 Analog ICs; Jieh-Tsorng Wu
Multi-Path Charge-Pump Filter
V aV b
V c
Ca
Rb Cb
V c
V a
V b
Ie1
Ie2
ωωz ωt ωp
Ie1 = IP 1 ×θe
2πIe1 = IP 2 ×
θe
2π
PLLs 27-44 Analog ICs; Jieh-Tsorng Wu
Multi-Path Charge-Pump Filter
The loop filter transfer function is
Vc(s)
θe(s)= KdF (s) =
IP 1
2π· 1Ca
+IP 2
2π
(Rb‖
1sCb
)=
IP 1
2πsCa
×sRb
(Cb + Ca ·
IP 2IP 1
)+ 1
sRbCb + 1
1ωz
= Rb
(Cb + Ca ·
IP 2
IP 1
)≈ RbCa ·
IP 2
IP 1
1ωp
= RbCb
The loop’s unity-gain frequency is
ωt ≈K′oIP 1
Caωz
= K ′o · IP 2Rb
• ωz, ωp, and ωt, can be set using smaller capacitors and resistors.
• Reference: J. Craninckx and M. Steyaert, A Fully Integrated CMOS DCS-1800Frequency Synthesizer, JSSC, 12/98, pp. 2054–2065.