7710HS–AVR–07/2013 Features • High Performance, Low Power AVR ® 8-bit Microcontroller • Advanced RISC Architecture – 129 Powerful Instructions - Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 1 MIPS throughput per MHz – On-chip 2-cycle Multiplier • Data and Non-Volatile Program Memory – 16K Bytes Flash of In-System Programmable Program Memory • Endurance: 10,000 Write/Erase Cycles – Optional Boot Code Section with Independent Lock Bits • In-System Programming by On-chip Boot Program • True Read-While-Write Operation – 512 Bytes of In-System Programmable EEPROM • Endurance: 100,000 Write/Erase Cycles – 1024 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security • On Chip Debug Interface (debugWIRE) • Peripheral Features – Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement • Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time • Variable PWM duty Cycle and Frequency • Synchronous Update of all PWM Registers • Auto Stop Function for Event Driven PFC Implementation • Less than 25Hz Step Width at 150kHz Output Frequency • PSC2 with four Output Pins and Output Matrix – One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture Mode – One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture Mode – Programmable Serial USART • Standard UART mode • 16/17 bit Biphase Mode for DALI Communications – Master/Slave SPI Serial Interface – 10-bit ADC • Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs • Programmable Gain (5x, 10x, 20x, 40x on Differential Channels) • Internal Reference Voltage – 10-bit DAC – Two or three Analog Comparator with Resistor-Array to Adjust Comparison Voltage – 4 External Interrupts – Programmable Watchdog Timer with Separate On-Chip Oscillator • Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in Bit-programmable I/O Space (4 bytes) – In-System Programmable via SPI Port – Internal Calibrated RC Oscillator (8 MHz) – On-chip PLL for fast PWM (32 MHz, 64 MHz) and CPU (16 MHz) • Operating Voltage: 2.7V - 5.5V • Extended Operating Temperature: – -40°C to +105°C Atmel 8-bit Microcontroller with 16K Bytes In-System Programmable Flash AT90PWM216 /AT90PWM316 Summary
This document is posted to help you gain knowledge. Please leave a comment to let me know what you think about it! Share it to your friends and learn new things together.
Transcript
7710HS–AVR–07/2013
Features• High Performance, Low Power AVR® 8-bit Microcontroller• Advanced RISC Architecture
– 129 Powerful Instructions - Most Single Clock Cycle Execution– 32 x 8 General Purpose Working Registers– Fully Static Operation– Up to 1 MIPS throughput per MHz– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory– 16K Bytes Flash of In-System Programmable Program Memory
– 1024 Bytes Internal SRAM – Programming Lock for Flash Program and EEPROM Data Security
• On Chip Debug Interface (debugWIRE)• Peripheral Features
– Two or three 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution Enhancement• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time • Variable PWM duty Cycle and Frequency• Synchronous Update of all PWM Registers• Auto Stop Function for Event Driven PFC Implementation• Less than 25Hz Step Width at 150kHz Output Frequency• PSC2 with four Output Pins and Output Matrix
– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture Mode– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare Mode and Capture
Mode– Programmable Serial USART
• Standard UART mode • 16/17 bit Biphase Mode for DALI Communications
– Master/Slave SPI Serial Interface– 10-bit ADC
• Up To 11 Single Ended Channels and 2 Fully Differential ADC Channel Pairs• Programmable Gain (5x, 10x, 20x, 40x on Differential Channels)• Internal Reference Voltage
– 10-bit DAC– Two or three Analog Comparator with Resistor-Array to Adjust Comparison Voltage– 4 External Interrupts – Programmable Watchdog Timer with Separate On-Chip Oscillator
• Special Microcontroller Features– Low Power Idle, Noise Reduction, and Power Down Modes– Power On Reset and Programmable Brown Out Detection– Flag Array in Bit-programmable I/O Space (4 bytes)– In-System Programmable via SPI Port– Internal Calibrated RC Oscillator (8 MHz)– On-chip PLL for fast PWM (32 MHz, 64 MHz) and CPU (16 MHz)
1. DisclaimerTypical values contained in this datasheet are based on simulations and characterization of other AVR microcon-trollers manufactured on the same process technology. Min and Max values will be available after the device ischaracterized.
2. Pin Configurations
Figure 2-1. SOIC 24-pin Package
Product Package 12 bit PWM with deadtimeADC Input
ADC Diff
Analog Comparator Application
AT90PWM216 SO24 2 x 2 8 1 2 One fluorescent ballast
AT90PWM316SO32, QFN32
3 x 2 11 2 3HID ballast, fluorescent ballast, Motor control
2.1 Pin Descriptions Table 2-1. Pin out description
S024 Pin Number
SO32 Pin Number
QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function
7 9 5 GND Power Ground: 0V reference
18 24 20 AGND Power Analog Ground: 0V reference for analog part
6 8 4 VCC power Power Supply:
17 23 19 AVCC PowerAnalog Power Supply: This is the power supply voltage for analog part
For a normal use this pin must be connected.
19 25 21 AREF PowerAnalog Reference: reference for analog converter. This is the reference voltage of the A/D converter. As output, can be used by external analog
Notes: 1. PSCOUT10 & PSCOUT11 are not present on 24 pins package
2. D2A (DAC Output) not available on AT90PWM261 (SOIC 24-pins)
3. OverviewThe AT90PWM216/316 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC architec-ture. By executing powerful instructions in a single clock cycle, the AT90PWM216/316 achieves throughputsapproaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processingspeed.
1 1 29 PD0 I/O
PSCOUT00 output(1)
XCK (UART Transfer Clock)
SS_A (Alternate SPI Slave Select)
3 4 32 PD1 I/OPSCIN0 (PSC 0 Digital Input)
CLKO (System Clock Output)
4 5 1 PD2 I/O
PSCIN2 (PSC 2 Digital Input)
OC1A (Timer 1 Output Compare A)
MISO_A (Programming & alternate SPI Master In Slave Out)
5 6 2 PD3 I/O
TXD (Dali/UART Tx data)
OC0A (Timer 0 Output Compare A)
SS (SPI Slave Select)
MOSI_A (Programming & alternate Master Out SPI Slave In)
QFN32 Pin Number Mnemonic Type Name, Function & Alternate Function
7AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
3.1 Block Diagram
Figure 3-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers aredirectly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in onesingle instruction executed in one clock cycle. The resulting architecture is more code efficient while achievingthroughputs up to ten times faster than conventional CISC microcontrollers.
The AT90PWM216/316 provides the following features: 16K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 1024 bytes SRAM, 53 general purpose I/O lines, 32 general purposeworking registers, three Power Stage Controllers, two flexible Timer/Counters with compare modes and PWM, oneUSART with DALI mode, an 11-channel 10-bit ADC with two differential input stage with programmable gain, a 10-bit DAC, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, an On-chip Debug systemand four software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt system to con-tinue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all otherchip functions until the next interrupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and allI/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Res-
16Kx8 FlashProgramMemory
InstructionRegister
InstructionDecoder
ProgramCounter
Control Lines
32 x 8GeneralPurpose
Registrers
ALU
Statusand Control
I/O Lines
EEPROM512 bytes
Data Bus 8-bit
DataSRAM1024 bytes
Dire
ct A
ddre
ssin
g
Indi
rect
Add
ress
ing
InterruptUnit
SPIUnit
WatchdogTimer
3 AnalogComparators
DAC
ADC
PSC 2/1/0
Timer 1
Timer 0
DALI USART
8AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
onator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with lowpower consumption.
The device is manufactured using the Atmel high-density nonvolatile memory technology. The On-chip ISP Flashallows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can useany interface to download the application program in the application Flash memory. Software in the Boot Flashsection will continue to run while the Application Flash section is updated, providing true Read-While-Write opera-tion. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the AtmelAT90PWM216/316 is a powerful microcontroller that provides a highly flexible and cost effective solution to manyembedded control applications.
The AT90PWM216/316 AVR is supported with a full suite of program and system development tools including: Ccompilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.
Note: AT90PWM216 device is available in SOIC 24-pin Package and does not have the D2A (DAC Output) brought out to I/0 pins.
3.2 Pin Descriptions
3.2.1 VCC
Digital supply voltage.
3.2.2 GND
Ground.
3.2.3 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buf-fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that areexternally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when areset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the AT90PWM216/316 as listed on page 63.
3.2.4 Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buf-fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that areexternally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when areset condition becomes active, even if the clock is not running.
Port C is not available on 24 pins package.
Port C also serves the functions of special features of the AT90PWM316 as listed on page 65.
3.2.5 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buf-fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that areexternally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when areset condition becomes active, even if the clock is not running.
Port D also serves the functions of various special features of the AT90PWM216/316 as listed on page 68.
9AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
3.2.6 Port E (PE2..0) RESET/ XTAL1/XTAL2
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buf-fers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that areexternally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when areset condition becomes active, even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 dif-fer from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin for longer than theminimum pulse length will generate a Reset, even if the clock is not running. The minimum pulse length is given inTable 8-1 on page 41. Shorter pulses are not guaranteed to generate a Reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier andinput to the internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting Oscillator amplifier.
The various special features of Port E are elaborated in “Alternate Functions of Port E” on page 71 and “Clock Sys-tems and their Distribution” on page 25.
3.2.7 AVCC
AVCC is the supply voltage pin for the A/D Converter. It should be externally connected to VCC, even if the ADC isnot used. If the ADC is used, it should be connected to VCC through a low-pass filter.
3.2.8 AREF
This is the analog reference pin for the A/D Converter.
3.3 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Thesecode examples assume that the part specific header file is included before compilation. Be aware that not all Ccompiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent.Please confirm with the C compiler documentation for more details.
10AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
4. Register SummaryAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
13AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM216/316 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
Note: This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
Note: Parts numbers are for shipping in sticks (SO) or in trays (QFN). These devices can also be supplied in Tape and Reel. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
7. Package Information
Speed (MHz) Power Supply Ordering Code Package Operation Range
16 2.7 - 5.5V AT90PWM316-16SU SO32Extended (-40C to
105C)
16 2.7 - 5.5V AT90PWM316-16MU QFN32Extended (-40C to
105C)
16 2.7 - 5.5V AT90PWM216-16SU SO24Extended (-40C to
105C)
Package Type
SO24 24-Lead, Small Outline Package
SO32 32-Lead, Small Outline Package
QFN32 32-Lead, Quad Flat No lead
18AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
7.1 SO24
19AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
7.2 SO32
20AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
7.3 QFN32
21AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
22AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
8. Errata AT90PWM216/316
8.1 Revision C• DAC Driver linearity above 3.6V
1. DAC Driver linearity above 3.6V
With 5V VCC, the DAC driver linearity is poor when DAC output level is above VCC-1V. At 5V, DAC output for1023 will be around 5V - 40mV.
Work around:
Use, when Vcc=5V, VREF below VCC-1V
Or, when VREF=VCC=5V, do not uses codes above 800.
8.2 Revision B• DAC Driver linearity above 3.6V
• PSC OCRxx Register update according to PLOCK2 usage
1. DAC Driver linearity above 3.6V
With 5V VCC, the DAC driver linearity is poor when DAC output level is above VCC-1V. At 5V, DAC output for1023 will be around 5V - 40mV.
Work around:
Use, when Vcc=5V, VREF below VCC-1V
Or, when VREF=VCC=5V, do not uses codes above 800.
2. PSC OCRxx Register update according to PLOCK2 usage
If the PSC is clocked from PLL, and if PLOCK2 bit is changed at the same time as PSC end of cycle occurs,and if OCRxx registers contents have been changed, then the updated OCRxx registers contents are notpredictable.
The cause is a synchronization issue between two registers in two different clock domains (PLL clock whichclocks PSC and CPU clock).
Workaround:
Enable the PSC end of cycle interrupt.
At the beginning of PSC EOC interrupt vector, change PLOCK value (OCRxx registers can be updated outsidethe interrupt vector).
This process guarantees that UPDATE and PLOCK actions will not occur at the same moment.
23AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
8.3 Revision A• DAC Driver linearity above 3.6V
• PSC OCRxx Register update according to PLOCK2 usage
1. DAC Driver linearity above 3.6V
With 5V VCC, the DAC driver linearity is poor when DAC output level is above VCC-1V. At 5V, DAC output for1023 will be around 5V - 40mV.
Work around:
Use, when Vcc=5V, VREF below VCC-1V
Or, when VREF=VCC=5V, do not uses codes above 800.
2. PSC OCRxx Register update according to PLOCK2 usage
If the PSC is clocked from PLL, and if PLOCK2 bit is changed at the same time as PSC end of cycle occurs,and if OCRxx registers contents have been changed, then the updated OCRxx registers contents are notpredictable.
The cause is a synchronization issue between two registers in two different clock domains (PLL clock whichclocks PSC and CPU clock).
Workaround:
Enable the PSC end of cycle interrupt.
At the beginning of PSC EOC interrupt vector, change PLOCK value (OCRxx registers can be updated outsidethe interrupt vector).
This process guarantees that UPDATE and PLOCK actions will not occur at the same moment.
24AT90PWM216/316 [DATASHEET]7710HS–AVR–07/2013
9. Datasheet Revision History for AT90PWM216/316Please note that the referring page numbers in this section are referred to this document. The referring revision inthis section are referring to the document revision.
9.1 Rev. 7710H – 07/2013
9.2 Rev. 7710G – 03/2013
1. Removed “1. History” chapter.
2. Errata:
“Revision C” on page 23: Errata added.
“Revision B” on page 23: Errata added.
“Revision A” on page 24: Errata updated.
1. Applied the Atmel new brand template that includes new logo and new addresses.
2. Added note to the MLF/QFN package: The Center GND PADDLE has to be connected to GND.
3. Updated the Figure 2-1 on page 3. Pin 18 changed to AGND instead of GND.
4. Updated the Figure 2-2 on page 4. Pin 24 changed to AGND instead of GND.
5. Added note to the MLF/QFN package: The Center GND PADDLE has to be connected to GND.
6. Updated Figure 5-2 on page 18.
7. Updated Table 6-2 on page 26.
8. Updated “MCU Control Register – MCUCR” on page 62. Added link for Bit 4: “Configuring the Pin” on page 57.
9. Corrected “typos” in “Overview” on page 122.
10. Updated “Features” on page 122. Correct feature is: Abnormality protection function, emergency input to force all outputs to low level.
11. Updated “Center Aligned Mode” on page 130. The label PSCn00 and PSCn01 are incorrect and are respectively replaced by PSCn0 and PSCn1.
12. Updated the formula of “The waveform frequency is defined by the following equation” in “Normal Mode” on page 134.
13. Updated the formula of fAVERAGE in “Enhanced Mode” on page 135.
14. Updated “Input Mode Operation” on page 140. Added a link to the Table 15-6.
15. Updated “PSC Synchronization” on page 151. The correct content: If the PSCn has its PARUNn bit set, then it can start at the same time as PSCn-1.
16. Updated “PSC 1 Control Register – PCTL1” on page 158. Bit 4 and Bit 3 linked to “PSC Input Configuration” on page 139.
17. Updated content description of Bit 1 and Bit 3 in “PSC 2 Synchro and Output Configuration – PSOC2” on page 154.
18. Updated “Output Compare SA Register – OCRnSAH and OCRnSAL” on page 155 and “Output Compare RB Register – OCRnRBH and OCRnRBL” on page 155. The registers are R/W and not only W.
19.
20. Updated “Overview” on page 215. Removed “or CLKi/O/2” from the overview description.
2. Updated “Absolute Maximum Ratings*” on page 283
22. Updated “Analog Comparator Status Register – ACSR” on page 219. Added Bit 3 - CLKPLL
23. Updated “Amplifier” on page 239. The correct content: “The ADC starting is done by setting the ADSC (ADC Start conversion) bit in the ADCSRA register”.
24. Updated Figure 20-15 on page 240 and Figure 20-16 on page 241. Changed CKADC to CKADC2.
25. Updated “PSC Output Behavior During Reset” on page 266. If PSCRV fuse equals 0 (programmed), the selected PSC outputs will be forced to high state. If PSCRV fuse equals 1 (unprogrammed), the selected PSC outputs will be forced to low state.
26. Updated “Electrical Characteristics” on page 283. Added “DAC Characteristics” on page 290.
27. Updated the Table 25-1 on page 285. Replaced -40C - 85C with -40C to 105C
28. Updated Table 25-5 on page 289. Replaced VINT parameter by AREF. Min and Max values updated.
1. Updated Table 8-1 on page 41. Added VPOR and VCCR in the table.
2. Updated Table 8-2 on page 42. Added min and max values for 101 and 010.
2. Inserted a footnote “AT90PWM216 device is available in SOIC 24-pin Package and does not have the D2A (DAC Output) brought out to I/0 pins.” on page 9.
3. Updated “Idle Mode” on page 35 by removing the reference to ACD.
4. Updated “Voltage Reference Enable Signals and Start-up Time” on page 44. Removed reference to ACBG.
4. Updated Table 15-14 on page 157; Table 15-15 on page 158 and Table 15-16 on page 159
5. Removed reference to the ACCKDIV from “Analog Comparator” on page 215 and from “Register Summary” on page 11.
6. Updated “ADC Prescaler Selection” on page 237.
7. Updated Table 25-5 on page 289 with Max and Min value for Internal Voltage Reference
8. Removed AC2SADE bit from “Register Summary” on page 11.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.