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An Operative Comparison of Two DVR Topologies based on a Matrix Converter without Energy Storage

José M. Lozano, Miguel A. Hernández-FigueroaDICIS of Guanajuato University

Ctra. Salamanca-Valle de Santiago Km 3.5+1.8 Km.36885 Salamanca, México.

jm.lozano[mahf]@ugto.mx

Juan M. RamírezCINVESTAV-IPN Guadalajara Campus

Av. del Bosque 1145, 45019Zapopan, México.

[email protected]

Abstract —In this paper, the operation of two DVR topologiesbased on a matrix converter and without energy storage areanalyzed and compared. By incorporating the AC-AC energyconversion technology and eliminating the energy storage devicethe topologies proposed represents attractive alternatives due totheir relatively low cost, maintenance requirements andcomplexity. Through the systems analysis and the simulationsresults obtained, the topology with the input terminals connectedon the load side presents the best performance in voltagecompensation applications.

Keywords-Matrix converter; dynamic voltage restorer; power quality.

I. I NTRODUCTION

OLTAGES in power distribution systems are commonlyaffected by disturbances. According to the CanadianElectric Associate (CEA) and the Electric Power Research

Institute (EPRI), among various power quality problems themajority of events are associated with either a voltage sag or a

voltage swell [1-2]. Such events are a common reason for failures in production plants, sensitive loads malfunctions, andeconomic losses [3]. Many solutions to these problems have

been published in recent years. The existing methods includetap changers, FACTS devices such as the distributionSTATCOM (D-STATCOM), the Unified Power QualityController (UPQC), and the Dynamic Voltage Restorer (DVR)[4-7]. The series compensation device DVR was introducedfor voltage sag mitigation and has been adopted as a commonsolution to the problem. The DVR’s operating principle is toinject the “missing” voltage in series with the supply in order to maintain an undisturbed load voltage, Fig. 1. Since the firstDVR introduced in 1994, several topologies have beendeveloped, along with different control methods and with

harmonic compensation purposes [8-9]. Most of the DVR topologies presented in the literature [10] can be classifiedwithin two categories: ( i) using stored energy (batteries,capacitors, flywheel, etc.) to supply the delivered power and,(ii) having no significant internal energy storage. In the latter case, the energy is taken from the faulted grid supply. Thesetopologies share one same specific characteristic: the dc-link.

In order to eliminate the drawbacks imposed by the use of dc-link passive elements some researchers have focused their efforts to the topologies based on ac/ac power converters,

which results in reduced maintenance requirements andimproved power density [11-13]. DVR topologies with energystorage are highly favored to compensate deep level voltagesags in sensitive loads within a wide power factor range.However, this type of systems has significant drawbacksregarding complexity and overall cost (energy storage and

power converter).

DVR converter

Gridsupply

SensitiveLoad

voltage sag injected voltage restored voltage

Energystorage

Fig. 1. Principle of operation of the dynamic Voltage Restorer

Among the existing DVR topologies with energy storagein ac form, various different types of switching power converters have been employed, being the matrix converter anattractive option. This paper is aimed to show an operativecomparison of two DVR topologies that takes advantage of thematrix converter operating characteristics, being able tocompensate balanced and unbalanced voltage fluctuations aswell as deep-level voltage sags. Among of the advantages of the proposed systems is the dc-link passive components, andac energy storage devices elimination. The paper is organizedas follows: the matrix converter modulation strategy iscovered in Section II; the DRV topologies proposed arerevised in Section III; numerical simulations via detailed

computer model are presented and conclusions are presentedin Section IV and Section V, respectively.

II. MATRIX CONVERTER MODULATION

Although matrix converter was initially introduced as anAC Driver, due to its advantages may be used in voltagecompensation applications. The main matrix converter disadvantages are the limited voltage transfer ratio and theconverter’s sensitivity to disturbances in the input voltages. In[14], it has been demonstrated that through the instantaneous

V

This work was supported by DAIP of Guanajuato University under grant187/11.



value measurement of two line-to-line input voltages, it is possible to produce balanced and sinusoidal output voltages,even under unbalanced input voltages.

The matrix converter’s configuration considered for theDVRs topologies analyzed in this paper, is shown in Fig. 2. Itconsists of nine bi-directional switches arranged in threegroups, each being associated with an output line. This bi-directional switches arrangement connects any of the input

lines to any of the output lines.

a

b

c

u v w

av

bv

cv

ui vi wi

Matrix Converter

Fig. 2. Direct Matrix Converter Topology

A. Modified Direct Space Vector Modulation (Modified DSVM) for unbalanced and distorted voltage supplyThe modulation technique used in this paper is the one

presented in [14], which performs the power conversiondirectly from ac to ac and is capable to cope with distortedinput voltages. As can be seen in Fig. 3 and Fig. 4, the DSVMtechnique uses a combination of two adjacent fixed vectorsand a zero-vector to produce the reference vector. The

proportion between the two adjacent vectors gives thedirection and the zero-vector duty cycle determines themagnitude of the reference vector. The input current ( )i n ref I

vector and the line-to-line output voltage vector ( )o ut r ef U arethe reference vectors.

The four basic equations that satisfy, at the same time, therequirements of the reference vectors , can be expressed asfollows:

( ( II II out I

I out ref out mU mU U +='

)( (1)

( ( IV IV out III

III out ref out mU mU U +=

'')( (2)

( ( IV IV in II

II inref in m I m I I +='

)( (3)

( ( III III in I

I inref in m I m I I +=''

)( (4)

'( )o ut r ef U ,

''( )out ref U are the voltage vector components of the

reference vector ( )out ref U . , , j j

inout jm U I are the duty cycle, theoutput voltage vector, and the input current vector,

respectively, related to the four switching configurations for each switching period ( j = I, II, III, IV ).

outl(ref)U

III

S4, S17, S21

S7, S11, S24

S9, S10, S23

S5, S18, S19'

outl(ref)U

outl(ref)∠ U

''

outl(ref)U

IVI

II

VIV

S3, S13, S26

S2, S15, S25

Fig. 3. Output-voltage’s fixed vectors

U inp

in∠ I

in(ref)I

6/

in

S18, S24, S26

S9, S21, S25

S5, S11, S13

S15, S17, S23

S3, S7, S19

S2, S4, S10 I IIII

IV

V VI

inl U

inl ∠ U

Fig. 4. Input-current’s fixed vectors

With reference to the case shown in Figs. 3-4, solving (1)-(4), the corresponding duty cycles become,

in

ref inref out

in

ref out I

I 33

U

U

U

32

mθ

π π

cos

coscos )()()(

⎟ ⎠ ⎞

⎜⎝ ⎛

∠+⎟ ⎠ ⎞

⎜⎝ ⎛

−∠

= (5)

in

ref inref out

in

ref out II

I 33

U

U

U

32

mθ

π π

cos

coscos )()()(

⎟ ⎠ ⎞

⎜⎝ ⎛

∠−⎟ ⎠ ⎞

⎜⎝ ⎛

−∠

= (6)

in

ref inref out

in

ref out III

I 33

U

U

U

32

mθ

π π

cos

coscos )()()(

⎟ ⎠ ⎞

⎜⎝ ⎛

∠+⎟ ⎠ ⎞

⎜⎝ ⎛

+∠

= (7)

in

ref inref out

in

ref out IV

I 33U

U

U

32

mθ

π π

cos

coscos )()()( ⎟ ⎠ ⎞

⎜⎝ ⎛

∠−⎟ ⎠ ⎞

⎜⎝ ⎛

+∠

= (8)

The scheme described by (5)-(8) is based on theassumption that the supply voltages are balanced withoutharmonics. In case of unbalanced and/or distorted supplyvoltages, is necessary to modify the duty cycles relations, byincorporating the characteristics of the supply voltages into thecomputation and adjusting the calculated duty ratios



accordingly. Table 1 exemplifies the compensated duty cycles by considering a unity power factor at the converter inputterminals, and K i (i = I, IV) is the sector in which the inputcurrent vector is located. This compensation method is simpleto implement and has a fast dynamic response.

TABLE I. D UTY CYCLES WHEN K I = I AND IV

K i = I and IV

( ))()(sin)()(

t vt v3U

U 1m abbcout 2

in

ref out K I

I −⎟ ⎠ ⎞

⎜⎝ ⎛

−−= α π (9)

( )( ))()(sin)()(

t vt vU

U 1m abbcout 2

in

ref out K II

I −−= α (10)

( )( ))()(sin)()(

t vt vU

U 1m bccaout 2

in

ref out K III

I −−= α (11)

( ))()(sin)()(

t vt v3U

U 1m bccaout 2

in

ref out K IV

I −⎟ ⎠ ⎞

⎜⎝ ⎛

−−= α π (12)

III. DVR S TOPOLOGIES ANALYSIS Conceptually, the DVR operates to maintain the load

supply voltage at rated value. When the DVR injects a voltage,it exchanges active and reactive power with the electric system.To supply active power, the DVR requires a source of energy.Similarly to the DC-link based topologies [10], in the case of DVRs with ac/ac converters, there are two types of system to

be considered. The first one has not significant energy storage.DVR topologies without external energy storage devicesassume that a part of the supply voltage remains during thesag, and this residual supply can be used to generate theenergy required to maintain full load power at rated voltage.Hence, the ability to compensate deep voltage sags will belimited by the input voltage. For instance, in [15] a VeSC-

based DVR with this topology is proposed to mitigatesymmetric voltage sags.

The second type of configuration uses stored energy tofeed the required power. Topologies that store energy have animproved performance compared with the no-energy storagesolution but the cost is higher. In [12] a matrix converter-

based DVR using flywheel energy storage is proposed for deep-level symmetric sags.

Considering the previous aspects, a DVR topology shouldfulfill the next requirements:

1) The device must have the ability to compensate deep-level symmetric voltage sags and unbalanced voltage

variations.2) It must provide voltage harmonic compensationcapabilities with minimal effect to the sagcompensation performance.

3) Minimization of cost and operational complexity.

Since in the case of no energy storage deviceconfigurations the energy is taken from the supply system inac form, the best option for the line interface inverter is toemploy an itegrated ac-ac converter. Moreover, to accomplishasymmetric and harmonic voltage compensation, the ac-ac

matrix converter operating with the modified SVM techniquerepresents a very attractive solution, which leads to the

proposed schemes in this paper.

A. Matrix converter-based DVR: Input Terminals Connected on the supply Side (Topology 1).

The configuration presented in Fig. 5, was developed with the purpose of compensate balance and unbalance voltage

variations as well as harmonic distortion on the supply systemvoltages. Since no energy storage device is used, the energyrequired for compensation is taken from the incoming supply.This approach has the disadvantage of drawing more currentfrom the line during the fault, and hence the upstream loadswill see a higher voltage drop. However, if the DVR isconnected to a strong grid the necessary power to the load can

be endured by increasing the input current and injecting themissing voltage with the converter. Even when saving isobtained on the energy storage system, the ability tocompensate deep-level voltage sags is limited as the maindisadvantage of matrix converter is the limited voltage transfer ratio.

During voltage sags, the input voltage of the matrixconverter drops proportionally to the sag, hence the maximuminjected voltage become,

32injV a≈ (13)

where injV is the injected voltage in pu and a is a voltage sagfactor defined as the ratio between the voltage during the sagand the load rated voltage.

Thus, the ability to compensate for symmetric voltage sagswill be theoretically limited up to 0.45 pu voltage drops.

B. Matrix converter-based DVR: Input Terminals Connected on the load Side (Topology 2).

The second DVR topology presents a matrix converter connected in shunt with the load, Fig. 6. This topology,according to previous analysis realized to DC-link DVR configurations, represents a good alternative for voltagecompensation due to its good performance and relatively lowcost. In this configuration, the voltage on the matrix converter input terminals can be held almost constant at the load ratedlevel by injecting sufficient voltage which increases DVR compensation capability.

Hence,

i load s injV V V V ≈ ≈ + (14)where:

Matrix converter input voltages

Load voltages

System voltages

Injected voltages

i

load

s

inj

V

V

V

V

=

=

=

=



Fig. 5. AC/AC DVR without energy storage devices

The current rating of the power system increases because itsupplies current into the matrix converter as well as into theload. Thus, the main disadvantages of this solution are thelarge currents in the supply system and the negative grideffects caused by the harmonic distorted currents drawn by theconverter. On the other hand, in the presence of a voltage sagevent, the compensation process can be seen as anaccumulative process in which as long as the matrix converter keeps injecting voltage, the available voltage for compensationgrows until the load reaches its rated value. Thus, even with asevere sag condition in the supply voltage, the converter theoretically can inject as much as 80 % of nominal voltage bythe proper control structure.

It is well known that one of the most attractive advantagesof matrix converter is the quality of the input current signals.This characteristic, along with the compensation process andthe proper control structure can overcome the maindisadvantages of the topology, besides the matrix converter limited voltage ratio.

C. Controller Design.

The objective of the DVR’s controller is to control the loadvoltages through the injection of the right compensationvoltages, ensuring a good transient response. A closed loopcontrol was used for testing both systems. Fig. 7 exhibits thecontrol loop structure which was developed in rotating d-q reference frame. The primary control structure is based on a

combination of supply voltage feed-forward and a PI-basedload voltage feed-back control branch. The feed-forwardcomponent provides the required transient response at the

beginning of the disturbance and reduces the overvoltage dropacross the filter inductor and other parameters such as thetransformer. Therefore, a closed-loop load voltage feed-back is added, and is implemented in the d-q frame to minimize anysteady state error in the fundamental component.

The DVR is synchronized to the grid supply with a phase-locked loop (PLL). A relativey slow PLL is used to limit

influence from harmonics and non-symmetrical input voltagesand also to maintain a smooth output voltage even during the

phase jump presented during the disturbances [7].

As shown in Fig. 7, the voltage at PCC, v pcc , is measuredand transformed to a rotating d-q reference frame. The actualstate of the supply voltages v pcc(d-q) is used for voltagedisturbance detection and for load voltage referencegeneration. After a disturbance is detected, the difference

between the voltage reference vref(d-q) and measured voltagev pcc(d-q) is utilized to determine the reference DVR injectionvoltage. Considering a coupling transformer with a unityvoltage ratio, the DVR injected voltages would beapproximately the matrix converter output voltages. Thetransformed load voltage vload(d-q) is compared with the voltagereference vref(d-q) and the error is fed to a PI-based voltagecontroller. Outputs from both main control ranches arecombined to generate the compensation references to theDVR, vdvr ,ref(d-q), which are then transformed into αβ coordinates in order to implement the modified SVMtechnique. In the modulation technique utilized for controllingthe matrix converter, the main control variables are | ( )outl ref U |

and | inl U | corresponding to the magnitudes of the DVR injected voltage reference and the supply system voltage Park vectors, respectively . The limiter block in the controller isemployed to avoid DVR false operations. The modifiedDSVM scheme incorporates the characteristics of the supplyvoltages into the computation of the duty cycles. The onlyrestriction that needs to be verified in the modulation scheme

proposed is established by (15).

( )3

2outl ref inl U U < (15)

In Fig. 8, is illustrated this restriction for the balanced andunbalanced conditions.




abc

-

-

d-q

abc

-

-

d-q

PLL S

Generation

supplyvabc( )

PI

d-q

-

K f

ModifiedSVM

IGBT

Gate Signals

S

Limiter

load vabc( )

(feed-back)

(feed-forward)

Gain

ref(d-q)V

dvr,ref,(d-q)v

Line-to-line voltages

( )outl ref U

( )inl ref U


in

9V

4⋅

S18S5

β

α

Fixed Vectors

Input Voltage LocusMaximum balanced outputVoltage LocusZero Vectors (S1, S14, S27)

S2S15S25

S19S7S11

S24

S9S10

S23

S3S13S26

S21S17

S4

( )Uoutl t

in

3V

2⋅ S18

S5

β

α

S2S15S25

S19S7S11

S24

S9S10S23

S3

S13S26

S21S17

S4

( )a ( )b

Fig. 8 (a) Voltage vectors for balanced input voltage condition. (b) Voltagevectors for unbalanced conditions (sag of 50% on phase b).

IV. SIMULATON RESULTS

The time-domain performance of the two DVR topologies,Figs. 5-6, is verified by detailed numerical simulation using

PSCAD software. The system key parameters for bothtopologies are given in Tables 2 and 3. The matrix converter-

based DVRs are evaluated under different abnormalconditions in the supply voltages. Three different tests have

been carried out for each topology.

TABLE II. L IST OF PARAMETERS TOPOLOGY 1

Parameter ValueCif: Input Filter Capacitor 10 µFR if : Input Filter Resistance 50 Ω Lif : Input Filter Inductor 2.1 mHCof : Output Filter Capacitor 4.7 µFLof : Output Filter Inductor 25 mHR of : Output Filter Resistance 100 Ω

Lload : Load Inductor 213 mHR load: Load Resistor 109.1 Ω

TABLE III. L IST OF PARAMETERS TOPOLOGY 2

Parameter ValueCif: Input Filter Capacitor 50 µFR if : Input Filter Resistance 20 Ω Lif : Input Filter Inductor 5.2 mHCof : Output Filter Capacitor 4.7 µFLof : Output Filter Inductor 2.2 mHLload : Load Inductor 213 mHR load : Load Resistor 109.1 Ω

A. Symmetric Sag

In the first study case a 50% three-phase voltage sag in thesupply voltage is simulated. Voltage waveforms during thedisturbance are plotted in the abc reference frame for bothtopologies, Figs. 9-10. These results are in good accordancewith the theoretical investigation; as it can be observed in Fig.9, the DVR Topology 1 can not compensate adequately thedisturbance because the sag’s magnitude is beyond itscapabilities; therefore, the voltage in the load stays below its



rated value during the fault. On the other hand, DVR Topology 2 presents not problem to generate the requiredvoltages to compensate the voltage variation and is able tomaintain the voltage load almost undisturbed during the sag

period.

Fig. 9. Symmetric sag condition: Voltage waveforms. Topology 1

Fig. 10. Symmetric sag condition: Voltage waveforms. Topology 2

B. Unbalanced disturbance

In this case, the DVRs performance is evaluated under anunbalanced voltage variation. For this test, voltage sags of 20% and 40% in phases b and c are considered. Furtheremore,a 17% voltage swell is applied on phase a. The DVR Topology1 is able to reduce the percent of imbalance from 22.17% to0.42% approximately, which demonstrates the effectiveness of the proposed topology response for unbalance test, Fig. 11. Inthis case, the matrix converter generates a set of unbalancedvoltages to achieve the compensation, which provokes adistortion in the currents drawn by the converter andconsequently the system currents are distorted as well.

The control algorithm in the DVR Topology 2 hasaccomplished to reduce the imbalance percent to 1.1%, Fig.12. Besides, the supplied system currents show a higher harmonic content compared to the Topology 1 because of theharmonics generated in the currents drawn by the matrix

converter. However this condition does not affect the overall performance.

C. Distorted Condition

Fotr the last test condition, a 5 th harmonic component isadded into phases a and c, an a 7 th harmonic component into

phase b. The magnitudes of the harmonics added are 0.2 times

the fundamental component in each phase. The response of voltage compensator, Topology 1, is illustrated in Fig. 13.Again the matrix converter does not have difficulties tosynthesize the required voltages for compensation. In the inputvoltages the low order harmonics are appreciated, but they nolonger appear on the aoutput voltages. The THD = 20% onevery input phase-voltage is redued to approximately 5% onthe output voltages. The performance of topology 2 under thiscondition is similar to the one developed by topology 1, Fig.14, being the main difference the quality of the currentsdemanded to the supply system. In Table 4, the load voltagesand system currents’ THD, calculated during each test arequoted.

V. CONCLUSIONS

Some comments can be made through the system analysisand the simulation results obtained. Although in general terms,

both topologies present good abilities to compensate for symmetric and asymmetric voltage sags, as well as for voltageharmonics suppression, some main differences can be stated.From the operative point of view, topology 2 has generallyhigh performance. Namely, its compensation process make itsuitable to compensate very deep-level voltage sags and toharmonic filtering applications because it can maintain theload voltages undisturbed and the system currents with arelatively low THD. However, its operation is critically

dependant on the design of the input and output filters anddemands a large amount of energy from the system during theoccurrence of a disturbance, which can increase the controlcomplexity and the cost of the overall system.

On the other hand, even when topology 1 exhibits limitedcompensation capabilities, particularly for deep voltage sags,it has no significant drawbacks regarding complexity andconverter ratings. These operative characteristics can set it upas a good alternative, depending on the application.

TABLE IV. S UMMARY OF LOAD VOLTAGES AND SYSTEM CURRENTS ’ THDPER PHASE ON BOTH TOPOLOGIES

Topology 1 Topology 2Condition 1 Ph. a Ph. b Ph. c Ph. a Ph. b Ph. c

Vload THD % 1.87 1.88 1.88 3.76 3.77 3.75Isyst THD % 7.3 7.34 7.32 14.8 14.2 14.1Condition 2

Vload THD % 2.37 2.54 3.05 3.42 3.85 4.91Isyst THD % 25.2 19.8 16.9 27.1 24.8 33Condition 3

Vload THD % 4.75 4.8 4.98 2.98 3.21 3.02Isyst THD % 36.6 45.4 41.6 22.4 32.5 27.8



Fig. 11. Unbalanced disturbance: Voltage waveforms. Topology 1

Fig. 13. Distorted condition: Voltage waveforms. Topology 1

ACKNOWLEDGMENT

Authors want to thank to the DAIP (Dirección de Apoyo alPosgrado) of Guanajuato University under grant 187/11.

R EFERENCES [1] D.O. Koval and M. B. Hughes, “Canadian national power quality

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[2] D.D. Sabin, “An assessment of distribution system power quality,”Elect. Power Res. Inst., Palo Alto, CA, Rep. TR-106294-V2, May 1996.

[3] Electric Power Research Institute (EPRI), “Power Quality in commercial buildings,” BR-105018, 1995.

[4] F.Q. Yousef-Zai, D. O’Kelly, “Solid-state on-load transformer tapchanger,” IEE Proceedings Electric Power Applications , vol. 143, no. 6,

pp. 481-491, 1996.[5] N.G. Hingorani, “Introducing CUSTOM POWER,” Spectrum, IEEE Jun

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[7] J.G. Nielsen, M. Newman, H. Nielsen, and F. Blaabjerg, “ Control andtesting of a dynamic voltage restorer (DVR) at medium voltage level,”IEEE Trans. Power Electron., vol. 19, no. 3, pp. 806-813, May 2004.

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[9] M. J. Newman, D. G. Holmes, J. G. Nielsen, and F. Blaabjerg: “Adynamic voltage restorer (DVR) with selective harmonic compensationat medium voltage level,” in Conf. Rec. IEEE-IAS Annu. Meeting , vol. 2,2003, pp. 1228-1235.

Fig. 12. Unbalanced disturbance: Voltage waveforms. Topology 2

Fig. 14. Distorted condition: Voltage waveforms. Topology 2

[10] John Godsk Nielsen and Frede Blaabjerg: “A Detailed Comparison of System Topologies for Dynamic Voltage Restorers ,” IEEE Trans. on

Ind. Applicat,. vol. 41 , pp. 1272-1280, Sep / Oct. 2005.[11] J. Perez, V. Cardenas, L. Moran, C. Nuñez, “Single-Phase AC-AC

converter operating as a dynamic voltage restorer (DVR),” IEEEIndustrial Electronics, IECON 2006 -32 nd Annual Conference on, Nov2006, pp. 1938-1943.

[12] B. Wang and G. Venkataramanan, “Dynamic Voltage Restorer utilizinga matrix converter and flywheel energy storage”, IEEE Transactions onIndustry Applications, Jan-Feb 2009, vol. 45, pp. 222-231.

[13] P. Gamboa, J. F. Silva, S. Ferreira Pinto and E. Margato: “PredictiveOptimal Matrix Converter Control for Dynamic Voltage Restorer withFlywheel Energy Storage”, 2009.

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IEEE Power Engineering Society General Meeting (PES-GM), SanFrancisco, California, 2005

Jose M. Lozano obtained his BS in Electrical Engineering from

Universidad de Guanajuato, México in 2003; M. Sc. and Ph. D. in ElectricalEngineering from CINVESTAV-México in 2006 and 2010 respectively. He joined the department of Electrical Engineering of Guanajuato University in2010, where he is currently a full time professor. His primary area of interestis in FACTS devices.

Juan M. Ramírez obtained his BS in Electrical Engineering fromUniversidad de Guanajuato, México in 1984; M. Sc. in Electrical Engineeringfrom UNAM-México in 1987; Ph. D. in Electrical Engineering from UANL-México in 1992. He joined the department of Electrical Engineering of CINVESTAV in 1999, where he is currently a full time professor. His areas of interest are in operation and control of electrical power systems.

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