arm2103[1].docx

Development of microcontrller based infrared seeking target tracking system

AT

BHARAT DYNAMICS LIMITED

(MINISTRY OF DEFENCE)

HYDERABAD

BY

M. VAMSHIDHAR REDDY 09881A0454

D. BHARGAVA 09881A0406

K. TEJASWINI 09881A0453

C. PRAMOD KUMAR 09881A0428

Under the guidance of

Mr. M. CHANDRA SHEKAR

SENIOR MANAGER, D&E, BDL

Department of Electronics and Communications

VARDHAMAN COLLEGE OF ENGINEERING, SHAMSHABAD

ACKNOWLEDGEMENT

We take this unique opportunity to express our heartfelt gratitude to Chairman and Managing

Director, BDL and Executive Director, D&E for giving us opportunity to work in this esteemed

institution. We are indebted to them for assigning a project which involved a lot of practical work and

design.

We are grateful to Professor Y. Pandu Rangaiah, Head of the department of ECE, Vardhaman

College of Engineering, Shamshabad, for this opportunity where we got an exposure to working in an

Industrial organization.

We are thankful to Mr. R. Sudhakar Rao, Senior Manager(D&E) who has been a great source

of knowledge and practical experience. His enthusiasm and commitment made us work harder to

fulfill our objective.

We are very thankful to Mr. M. Chandrasekhar, Senior Manager (D&E), for his constant guidance and

inspiration throughout this project. Their encouragement, invaluable suggestion and assistance helped

us to complete this project within the stipulated time.

We would also thank all the members of simulators Lab (D&E) for their help and support in the

completion of the project.

ABSTRACT

Microcontrollers have found various applications in the present scenario and are used in most

of the electronics based equipments. They have become a user friendly component and their

programming part is being made easy through the wide spread knowledge about them. Our project

microcontroller based infrared seeking target tracking system is to identify the location of an IR

source. Whenever it gets hard to find the location of an object we are searching for, especially when

the object we are looking for is moving, we need to keep track of the object's movement to find it. Our

project gives an effective solution to this problem. In our project we continuously capture the images

of IR emission and according to the variations of the target movement; we program the

microcontroller in such a way that the receiver adjusts its position with corresponding variations of the

target.

The objective of the project is to construct a device that has the capability to track IR signals

emitted from a source and propel itself in the direction of that source. It was planned that the device

shall be 2-dimensional which is controlled by the direction from which the IR signals are received.

The brain of the entire assembly that shall control and coordinate the rotation of the device is a

microcontroller Chip named LP2103. The system under question shall be a fully automated

Microcontroller based embedded system. The navigation is based on the transmission of IR signals of

a specific frequency from a particular Direction so that the device moves towards that direction. The

primary challenge of the project is to convert the Infrared radiation to Analog voltage signal which in

turn will be fed to the microcontroller through an Analog to Digital Converter (ADC). The output from

the Microcontroller will finally drive the motors necessary for the locomotion of the device.

CONTENTS

CHAPTER 1

1.1 MISSILES

1.2 INFRARED SEEKER

1.3 INFRARED COUNTERMEASURES

CHAPTER 2

2.1 EMBEDDED SYSTEMS

2.2 REQUIREMENTS

CHAPTER 3

CKT

3.1 LPC2103

3.1.1 General description

3.1.2 Key features

3.1.3 Block diagram

3.1.4 Functional description

3.2 POWER SUPPLY3.3 MAX 2323.4 LDR3.5 LCD MODULE3.6 ULN20033.7 STEPPER MOTOR

CHAPTER 4

4.1 Software development

4.2 TOOLS USED

CHAPTER 5

RESULTS AND ANALYSIS

CHAPTER 6

CONCLUSION

REFERENCES

APPENDIX

CHAPTER 1

1.1 MISSILES

Etymology and usage:

A missile is a self-propelled guided weapon system. Missiles have four system components: targeting

and/or guidance, flight system, engine, and warhead. Missiles come in types adapted for different

purposes: surface-to-surface and air-to-surface missiles (ballistic, cruise, anti-ship, anti-tank), surface-

to-air missiles (anti-aircraft and anti-ballistic), air-to-air missiles, and anti-satellite missiles. The

word missile comes from the Latin verb mittere, meaning "to send".

In military usage, munitions projected towards a target are broadly categorized as follows:

A powered, guided munition that travels through the air or space is known as

a missile (or guided missile.)

A powered, unguided munition is known as a rocket.

Unpowered munitions not fired from a gun are called bombs whether guided or not;

unpowered, guided munitions are known as guided bombs or "smart bombs".

Munitions that are fired from a gun are known as projectiles whether guided or not. If

explosive they are known more specifically as shells or mortar bombs.

Powered munitions that travel through water are called torpedoes (an older usage includes

fixed torpedoes, which might today be called mines).

Hand grenades are not usually classed as missiles.

Early development

The first missiles to be used operationally were a series of missiles developed by Nazi

Germany in World War II. Most famous of these are the V-1 flying bomb and V-2, both of which used

a simple mechanical autopilot to keep the missile flying along a pre-chosen route. Less well known

were a series of anti-shipping and anti-aircraft missiles, typically based on a simple radio control

system directed by the operator.

Technology:Guided missiles have a number of different system components:

Targeting and/or guidance

Flight system

Engine

Warhead

Guidance systems

Missiles may be targeted in a number of ways. The most common method is to use some form

of radiation, such as infrared, lasers or radio waves, to guide the missile onto its target. This radiation

may emanate from the target (such as the heat of an engine or the radio waves from an enemy radar), it

may be provided by the missile itself (such as a radar) or it may be provided by a friendly third party

(such as the radar of the launch vehicle/platform, or a laser designator operated by friendly infantry).

The first two are often known as fire-and-forget as they need no further support or control from the

launch vehicle/platform in order to function. Another method is to use a TV camera—using

either visible light or infra-red—in order to see the target. The picture may be used either by a human

operator who steers the missile onto its target, or by a computer doing much the same job. One of the

more bizarre guidance methods instead used a pigeon to steer the missile to its target.

Many missiles use a combination of two or more of the above methods, to improve accuracy and the

chances of a successful engagement.

Targeting systems

Another method is to target the missile by knowing the location of the target, and using a

guidance system such as INS, TERCOM or GPS. This guidance system guides the missile by knowing

the missile's current position and the position of the target, and then calculating a course between

them. This job can also be performed somewhat crudely by a human operator who can see the target

and the missile, and guides it using either cable or radio based remote-control, or by an automatic

system that can simultaneously track the target and the missile.

Flight system

Whether a guided missile uses a targeting system, a guidance system or both, it needs a flight

system. The flight system uses the data from the targeting or guidance system to maneuver the missile

in flight, allowing it to counter inaccuracies in the missile or to follow a moving target. There are two

main systems: vectored thrust (for missiles that are powered throughout the guidance phase of their

flight) and aerodynamic maneuvering (wings, fins, canards, etc.).

Engine

Missiles are powered by an engine, generally either a type of rocket or jet engine. Rockets are

generally of the solid fuel type for ease of maintenance and fast deployment, although some larger

ballistic missiles use liquid fuel rockets. Jet engines are generally used in cruise missiles, most

commonly of the turbojet type, due to its relative simplicity and low frontal area. Turbofans and

ramjets are the only other common forms of jet engine propulsion, although any type of engine could

theoretically be used. Missiles often have multiple engine stages, particularly in those launched from

the surface. These stages may all be of similar types or may include a mix of engine types - for

example, surface-launched cruise missiles often have a rocket booster for launching and a jet engine

for sustained flight.

Some missiles may have additional propulsion from another source at launch; for example the V1 was

launched by a catapult and the MGM-51 was fired out of a tank gun (using a smaller charge than

would be used for a shell).

Warhead

Missiles generally have one or more explosive warheads, although other weapon types may

also be used. The warhead or warheads of a missile provides its primary destructive power (many

missiles have extensive secondary destructive power due to the high kinetic energy of the weapon and

unburnt fuel that may be on board). Warheads are most commonly of the explosive type, often

employing shaped charges to exploit the accuracy of a guided weapon to destroy hardened targets.

Other warhead types include sub munitions, incendiaries, weapons,

chemical, biological or radiological weapons or kinetic energy penetrators. War headless missiles are

often used for testing and training purposes.

Basic roles

Missiles are generally categorized by their launch platform and intended target. In broadest

terms, these will either be surface (ground or water) or air, and then sub-categorized by range and the

exact target type (such as anti-tank or anti-ship). Many weapons are designed to be launched from both

surface and the air, and a few are designed to attack either surface or air targets (such as

the ADATS missile). Most weapons require some modification in order to be launched from the air or

surface, such as adding boosters to the surface-launched version.

Surface-to-Surface/Air-to-Surface

Ballistic

An R-36 ballistic missile launch at a Soviet silo

After the boost-stage, ballistic missiles follow a trajectory mainly determined by ballistics. The

guidance is for relatively small deviations from that.

Ballistic missiles are largely used for land attack missions. Although normally associated with

nuclear weapons, some conventionally armed ballistic missiles are in service, such as ATACMS. The

V2 had demonstrated that a ballistic missile could deliver a warhead to a target city with no possibility

of interception, and the introduction of nuclear weapons meant it could efficiently do damage when it

arrived. The accuracy of these systems was fairly poor, but post-war development by most military

forces improved the basic inertial platform concept to the point where it could be used as the guidance

system on ICBMs flying thousands of kilometers. Today the ballistic missile represents the

only strategic deterrent in most military forces, however some ballistic missiles are being adapted for

conventional roles, such as the Russian Iskander or the Chinese DF-21D anti-ship ballistic missile.

Ballistic missiles are primarily surface launched from mobile launchers, silos, ships or submarines,

with air launch being theoretically possible with a weapon such as the cancelled Skybolt missile.

The Russian Topol M (SS-27 Sickle B) is the fastest (7,320 m/sec) missile currently in service[2]

Cruise missile

United States Tomahawk cruise missile

The V1 had been successfully intercepted during World War II, but this did not make

the cruise missile concept entirely useless. After the war, the US deployed a small number of nuclear-

armed cruise missiles in Germany, but these were considered to be of limited usefulness. Continued

research into much longer ranged and faster versions led to the US's Navaho missile, and

its Soviet counterparts, the Burya and Buran cruise missile. However, these were rendered largely

obsolete by the ICBM, and none were used operationally. Shorter-range developments have become

widely used as highly accurate attack systems, such as the US Tomahawk missile, the Russian Kh-

55 the German Taurus missile and the Pakistani Babur cruise missile.The BrahMos cruise missile

which is a joint venture between India and Russia.

Cruise missiles are generally associated with land attack operations, but also have an important

role as anti-shipping weapons. They are primarily launched from air, sea or submarine platforms in

both roles, although land based launchers also exist.

Anti-ship

The French Exocet missile in flight

Another major German missile development project was the anti-shipping class (such as

the Fritz X and Henschel Hs 293), intended to stop any attempt at a cross-channel invasion. However

the British were able to render their systems useless by jamming their radios, and missiles with wire

guidance were not ready by D-Day. After the war the anti-shipping class slowly developed, and

became a major class in the 1960s with the introduction of the low-flying jet- or rocket-powered cruise

missiles known as "sea-skimmers". These became famous during the Falklands War when an

Argentine Exocet missile sank a Royal Navy destroyer.

A number of anti-submarine missiles also exist; these generally use the missile in order to

deliver another weapon system such as a torpedo or depth charge to the location of the submarine, at

which point the other weapon will conduct the underwater phase of the mission.

Anti-tank

U.S. Army soldiers firing an FGM-148 Javelin

By the end of WWII all forces had widely introduced unguided rockets using HEAT warheads

as their major anti-tank weapon (see Panzerfaust,Bazooka). However these had a limited useful range

of a 100 m or so, and the Germans were looking to extend this with the use of a missile using wire

guidance, the X-7. After the war this became a major design class in the later 1950s, and by the 1960s

had developed into practically the only non-tank anti-tank system in general use. During the

1973 Yom Kippur War between Israel and Egypt, the 9M14 Malyutka (aka "Sagger") man-portable

anti-tank missile proved potent against Israeli tanks. While other guidance systems have been tried, the

basic reliability of wire-guidance means this will remain the primary means of controlling anti-tank

missile in the near future. Anti tank missiles may be launched from aircraft, vehicles or by ground

troops in the case of smaller weapons.

Surface-to-air

Anti-aircraft

MIM-104 Patriot missile being launched

By 1944 US and British air forces were sending huge air fleets over occupied Europe,

increasing the pressure on the Luftwaffe day and night fighter forces. The Germans were keen to get

some sort of useful ground-based anti-aircraft system into operation. Several systems were under

development, but none had reached operational status before the war's end. The US Navy also started

missile research to deal with the Kamikaze threat. By 1950 systems based on this early research started

to reach operational service, including the US Army's Nike Ajax, the Navy's "3T's" (Talos, Terrier,

Tartar), and soon followed by the Soviet S-25 Berkut and S-75 Dvina and French and British systems.

Anti-aircraft weapons exist for virtually every possible launch platform, with surface-launched

systems ranging from huge, self-propelled or ship-mounted launchers to man portable systems.

Anti-ballistic

Arrow missile

Like most missiles, the Arrow missile, S-300, S-400, Advanced Air Defence and MIM-104

Patriot are for defense against short-range missiles and carry explosive warheads.

However, in the case of a large closing speed, a projectile without explosives is used, just

a collision is sufficient to destroy the target. See Missile Defense Agency for the following systems

being developed:

Kinetic Energy Interceptor (KEI)

Aegis Ballistic Missile Defense System (Aegis BMD) - a SM-3 missile

with Lightweight Exo-Atmospheric Projectile (LEAP) Kinetic

Warhead (KW)

Air-to-air

A F-22 Raptor fires an AIM-120 AMRAAM

Soviet RS-82 rockets were successfully tested in combat at the Battle of Khalkhin Gol in 1939.

German experience in World War II demonstrated that destroying a large aircraft was quite difficult,

and they had invested considerable effort into air-to-air missile systems to do this. Their Me-262's jets

often carried R4M rockets, and other types of "bomber destroyer" aircraft had unguided rockets as

well. In the post-war period the R4M served as the pattern for a number of similar systems, used by

almost all interceptor aircraft during the 1940s and '50s. Lacking guidance systems, such rockets had

to be carefully aimed at relatively close range to successfully hit the target. The US Navy and U.S. Air

Force began deploying guided missiles in the early 1950s, most famous being the US Navy's AIM-9

Sidewinder and USAF's AIM-4 Falcon. These systems have continued to advance, and modern air

warfare consists almost entirely of missile firing. In the Falklands War, less powerful

British Harriers were able to defeat faster Argentinian opponents using AIM-9G missiles provided by

the United States as the conflict began. The latest heat-seeking designs can lock onto a target from

various angles, not just from behind, where the heat signature from the engines is strongest. Other

types rely on radar guidance (either on-board or "painted" by the launching aircraft). Air to Air

missiles also have a wide range of sizes, ranging from helicopter launched self-defense weapons with a

range of a few kilometers, to long range weapons designed for interceptor aircraft such as

the Vympel R-37.

Anti-satellite

ASM-135 ASAT missile launch in 1985

In the 1950s and 1960s, Soviet designers started work on an anti-satellite weapon, called the

"Istrebitel Sputnik", which meant literally, interceptor of satellites, or destroyer of satellites. After a

lengthy development process of roughly 20 years, it was finally decided that testing of the Istrebitel

Sputnik be canceled. This was when the U.S. started testing their own systems. The Brilliant

Pebbles defense system proposed during the 1980s would have used kinetic energy collisions without

explosives. Anti satellite weapons may be launched either by an aircraft or a surface platform,

depending on the design. To date, only a few known tests have occurred

1.2 INFRARED SEEKER

An infrared seeker head for target tracking missiles has a main detector and an imaging optical

system generating an image of a field of view on the main detector. The field of view contains a target

such as an enemy aircraft. The missile is guided to the target in accordance with signals from the main

detector. The target, if attacked by the missile, emits high-intensity laser radiation towards the missile

as a counter-measure. This is to disturb the operation of the seeker head by dazzling or even destroying

the main detector. The seeker head contains a device for defending against such disturbances. Various

types of such defending devices are described. Incident light is deviated from the main detector. A

second-quadrant-detector of reduced sensitivity guides the missile along the disturbing laser beam.

Another embodiment uses attenuating optical elements in front of the main detector under the control

of one or more second detectors.

Infrared homing refers to a passive missile guidance system which uses the emission from a

target of electromagnetic radiation in theinfrared part of the spectrum to track and follow it. Missiles

which use infrared seeking are often referred to as "heat-seekers", since infrared (IR) is just below the

visible spectrum of light in frequency and is radiated strongly by hot bodies. Many objects such as

people, vehicle engines and aircraft generate and retain heat, and as such, are especially visible in the

infra-red wavelengths of light compared to objects in the background.

The infrared sensor package on the tip or head of a heat-seeking missile is known as the  seeker

head. The NATO brevity code for an air-to-air infrared-guided missile launch is "Fox Two".[1] 90% of

all United States air combat losses over the past 25 years have been due to infrared-homing missiles.

Seeker types

The three main materials used in the infrared sensor are lead(II) sulfide (PbS), indium

antimonide (InSb) and mercury cadmium telluride (HgCdTe). Older sensors tend to use PbS, newer

sensors tend to use InSb or HgCdTe. All perform better when cooled, as they are both more sensitive

and able to detect cooler objects.

Early infrared seekers were most effective in detecting infrared radiation with shorter

wavelengths, such as the 4.2 micrometer emissions of the carbon dioxide efflux of a jet engine. Such

seekers, which are most sensitive to the 3 to 5 micrometer range, are now called single-color seekers.

Modern infrared seekers also operate in the 8 to 13 micrometer wavelength range, which is absorbed

least by the atmosphere. Such seekers are called two-color systems. Two-color seekers are harder to

defeat with countermeasures such as flares.

Scanning patterns and modulation

A missile's resistance to decoys can also be determined by the method in which the space in

front of itself is scanned for targets. Early missiles used spin scanning while newer seekers

useconical scanning which gives them superior decoy discrimination as well as overall increased

sensitivity for longer range tracking. There have also been missiles built using so-called "rosette"

scanning methods. Very modern heat-seeking missiles utilize imaging infrared (IIR), where the IR/UV

sensor is a focal plane array which is able to "see" in infra-red, much like the CCD in a digital camera.

This requires much more signal processing but can be much more accurate and harder to fool with

decoys. In addition to being more flare-resistant, newer seekers are also less likely to be fooled into

locking onto the sun, another common trick for avoiding heat-seeking missiles.

Before imaging infrared sensors there was also the question of sensor modulation; earlier

seekers used amplitude modulation (AM) to determine how far off-center the target was and thus how

hard the missile had to turn to center it, but this led to increased error as the missile approached the

target and the target's image became relatively larger (creating an artificially stronger signal).

Switching to frequency modulation (FM) solved this problem, which is better able to discriminate the

distance without being further confused by the image size.

Cooling

All-aspect seekers also tend to require cooling to give them the high degree of sensitivity

required to lock onto the lower level signals coming from the front and sides of an aircraft.

Background heat from inside the sensor, or the aerodynamically heated sensor window, can overpower

the weak signal entering the sensor from the target. (CCDs in cameras have similar problems; they

have much more "noise" at higher temperatures.) Modern all-aspect missiles like the AIM-9M

Sidewinder and FIM-92 Stinger use compressed gas or Argon to cool their sensors in order to lock

onto the target at longer ranges and all aspects. (Some such as the AIM-9J and early-model R-60 used

a peltier thermoelectric cooler).

Tracking

Most infrared guided missiles have their seekers mounted on a gimbals. This allows the sensor

to be pointed at the target when the missile is not. This is important for two main reasons. One is that

before and during launch, the missile cannot always be pointed at the target. Rather, the pilot or

operator points the seeker at the target using radar, a helmet-mounted sight, an optical sight or possibly

by pointing the nose of the aircraft or missile launcher directly at the target. Once the seeker sees and

recognises the target, it indicates this to the operator who then typically "uncages" the seeker (which is

allowed to follow the target). After this point the seeker remains locked on the target, even if the

aircraft or launching platform moves. When the weapon is launched, it may not be able to control the

direction it points until the motor fires and it reaches a high enough speed for its fins to control its

direction of travel. Until then, the gimbaled seeker needs to be able to track the target independently.

Finally, even while it is under positive control and on its way to intercept the target, it probably

will not be pointing directly at it; unless the target is moving directly toward or away from the

launching platform, the shortest path to intercept the target will not be the path taken while pointing

straight at it, since it is moving laterally with respect to the missile's view. The original heat-seeking

missiles would simply point towards the target and chase it; this was inefficient. Newer missiles are

smarter and use the gimbaled seeker head combined with what is known asproportional guidance in

order to avoid oscillation and to fly an efficient intercept path.

1.3 INFRARED COUNTERMEASURES

An infrared countermeasure (IRCM) is a device designed to protect aircraft from infrared

homing ("heat seeking") missiles by confusing the missiles infrared guidance system so that they will

miss their target.

IRCM principles

A ALQ-144 modulated IRCM jammer.

Infrared seekers are designed to track a strong source of infrared radiation (usually a jet

engine in modern military aircraft). IRCM systems are based on modulated source of infrared radiation

with a higher intensity than the target. When this modulated radiation is seen by a missile seeker, it

overwhelms the modulated signal from the aircraft and provides incorrect steering cues to the missile.

The missile will begin to deviate (wobble) from the target, rapidly breaking lock. Once an infrared

seeker breaks lock (they typically have a field of view of 1 - 2 degrees), they rarely reacquire the

target. By using flares, the target can cause the confused seeker to lock onto a new infrared source that

is rapidly moving away from the true target.

The modulated radiation from the IRCM generates a false tracking command in the seeker

tracking logic. The effectiveness of the IRCM is determined by the ratio of jamming intensity to the

target (or signal) intensity. this ratio is usually called the J/S ratio. Another important factor is the

modulation frequencies which should be close to the actual missile frequencies. For spin scan missiles

the required J/S is quite low but for newer missiles the required J/S is quite high requiring a directional

source of radiation (DIRCM).[1]

Drawbacks of IRCM

One of the drawbacks of standard IRCM systems is that they broadcast a bright source of

infrared. If the modulation of the signal is not effective against a particular seeker system, the IRCM

will enhance the ability of the missile to track the aircraft. The aircrews typically brief about potential

threats and choose an IRCM modulation that will be effective against likely threats.[citation needed]

Directional IRCM

DIRCM, or Directional Infrared Countermeasures, avoid this potential drawback by mounting

the energy source on a movable turret (much like a FLIR turret). They only operate when cued by a

missile warning system of a missile launch, and use the missile plume to accurately aim at the missile

seeker. The modulated signal can then be directed at the seeker, and the modulation scheme can be

cycled to try to defeat a variety of seekers. Countermeasure success depend on threat's tracking

techniques and requires threats' analysis capabilities.[2] Defeating advanced tracking systems requires a

higher level of DIRCM power. Issues of Laser Safety are also taken into account.

Israel has announced a program to develop a system called Multi Spectral Infrared

Countermeasure (MUSIC) that will similarly use active lasers instead of flares to protect civilian

aircraft against MANPADs.[3] The US Army is deploying a similar system to protect its helicopters.[4]

Department of the Navy Large Aircraft Countermeasures (Don LAIRCM) by Northrop

Grumman provides infrared threat protection for U.S. Marine Corps CH-53E, CH-46E and CH-53D

platforms.

BAE Systems' AN/ALQ-212 advanced threat infrared countermeasures (ATIRCM) - part of a

direct able infrared countermeasures suite - is fielded on U.S. Army CH-47 Chinook helicopters. The

suite provides protection against an array of threats, including all infrared threat bands. The AN/ALQ-

212 incorporates one or more infrared jam heads to counter multiple missile attacks.

CIRCM (Common Infrared Countermeasures)

ITT's CIRCM Fitted to US Army UH-60During Test Exercises

CIRCM will be a laser based IR countermeasure against current and future IR threat systems

for the US Army rotorcraft and fixed wing platforms and US Navy and US Air Force rotorcraft

platforms. Currently, systems by BAE Systems, ITT Defense and Information Solutions, Grumman

and Raytheon are under consideration. [6]

Flares

Flares create infrared targets with a much stronger signature than the aircraft's engines. The

flares provide false targets that cause the missile to make incorrect steering decisions. The missile will

rapidly break off a target lock-on.

A (decoy) flare is an aerial infrared countermeasure to counter an infrared homing ("heat

seeking") surface-to-air missile or air-to-air missile. Flares are commonly composed of a pyrotechnic

composition based on magnesium or another hot-burning metal, with burning temperature equal to or

hotter than engine exhaust. The aim is to make the infrared-guided missile seek out the heat signature

from the flare rather than the aircraft's engines.

CHAPTER 2

2.1 EMBEDDED SYSTEMS

Embedded systems are designed to do some specific task, rather than be a general-purpose

computer for multiple tasks. Some also have real time performance constraints that must be met, for

reason such as safety and usability; others may have low or no performance requirements, allowing the

system hardware to be simplified to reduce costs.

An embedded system is not always a separate block - very often it is physically built-in to the

device it is controlling. The software written for embedded systems is often called firmware, and is

stored in read-only memory or flash convector chips rather than a disk drive. It often runs with limited

computer hardware resources: small or no keyboard, screen, and little memory.

Wireless communication has become an important feature for commercial products and a

popular research topic within the last ten years. Lately, one area of commercial interest has been low-

cost, low-power, and short-distance wireless communication used for \personal wireless networks."

Technology advancements are providing smaller and more cost effective devices for integrating

computational processing, wireless communication, and a host of other functionalities. These

embedded communications devices will be integrated into applications ranging from homeland

security to industry automation and monitoring. They will also enable custom tailored engineering

solutions, creating a revolutionary way of disseminating and processing information. Unfortunately,

there are few adorable environments available for development and classroom use, so students often

do not learn about these technologies during hands-on lab exercises. The communication mediums

were twisted pair, optical fiber, infrared, and generally wireless radio.

HARDWARE:

1. ARM CONTROLLER(LPC 2103)

2. POWER SUPPLY

3. LCD

4. LDRS

5. MAX232

6. STEPPERMOTOR

7. ULN 2003

SOFTWARE:

1. KEIL MICROVISION

2. EMBEDDED C

CHAPTER 3

DESCRIPTION OF HARDWARE COMPONENTS

3.1 LPC2103

3.1.1. General description

The LPC2101/2102/2103 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU

with real-time emulation that combines the microcontroller with 8 kB, 16 kB or 32 kB of embedded

high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture

enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service

routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical

code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with

minimal performance penalty.

Due to their tiny size and low power consumption, the LPC2101/2102/2103 are ideal for

applications where miniaturization is a key requirement. A blend of serial communications interfaces

ranging from multiple UARTs, SPI to SSP and two I2C-buses, combined with on-chip SRAM of 2

kB/4 kB/8 kB, make these devices very well suited for communication gateways and protocol

converters. The superior performance also makes these devices suitable for use as math coprocessors.

Various 32-bit and 16-bit timers, an improved 10-bit ADC, PWM features through output match on all

timers, and 32 fast GPIO lines with up to nine edge or level sensitive external interrupt pins make

these microcontrollers particularly suitable for industrial control and medical systems.

3.1.2 Key features

1. 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP48 package.

2. 2 kB/4 kB/8 kB of on-chip static RAM and 8 kB/16 kB/32 kB of on-chip flash program

memory. 128-bit wide interface/accelerator enables high-speed 70 MHz operation.

3. ISP/IAP via on-chip boot loader software. Single flash sector or full chip erase in 100 ms and

programming of 256 bytes in 1 ms.

4. Embedded ICE RT offers real-time debugging with the on-chip Real Monitor software.

5. The 10-bit A/D converter provides eight analog inputs, with conversion times as low as 2.44

s per channel and dedicated result registers to minimize interrupt overhead.

6. Two 32-bit timers/external event counters with combined seven capture and seven compare

channels.

7. Two 16-bit timers/external event counters with combined three capture and seven compare

channels.

8. Low power Real-Time Clock (RTC) with independent power and dedicated 32 kHz clock

input.

9. Multiple serial interfaces including two UARTs (16C550), two Fast I2C-buses (400 Kbit/s),

SPI and SSP with buffering and variable data length capabilities.

10. Vectored interrupt controller with configurable priorities and vector addresses.

11. Up to thirty-two 5 V tolerant fast general purpose I/O pins. And Up to 13 edges or level

sensitive external interrupt pins available.

12. 70 MHz maximum CPU clock available from programmable on-chip PLL with a possible input

frequency of 10 MHz to 25 MHz and a settling time of 100 s.

13. On-chip integrated oscillator operates with an external crystal in the range from 1 MHz to 25

MHz

14. Power saving modes includes idle mode, Power-down mode with RTC active and Power-down

mode.

15. Individual enable/disable of peripheral functions as well as peripheral clock scaling for

additional power optimization

16. . Processor wake-up from Power-down mode via external interrupt or RTC.

3.1.3 Block diagram

TMS TDIXTAL2 V

DD(3V3) V

DD(1V8)

VSSTRST TCK TDO XTAL1 RST

LPC2101/2102/2103

TEST/DEBUG

INTERFACE

P0[31:0]

HIGH SPEED

PLL

SYSTEM

GENERAL 8 kB

ARM7TDMI-S

FUNCTIONS

PURPOSE I/O BOOT ROM

system

AHB BRIDGE clock

VECTORED

ARM7 local bus

INTERRUPT

CONTROLLER

AMBA AHB

(Advanced High-performance Bus)

INTERNAL

MEMORY

SRAM

ACCELERATOR

CONTROLLER

2 kB/4 kB/ 8 kB/16 kB/ AHB TO APB8 kB SRAM 32 kB FLASH BRIDGE

APB (ARM

EINT2 toperipheral bus)

I2

C-BUS SERIALEXTERNAL

EINT0(1)

INTERRUPTS INTERFACES 0 AND 1

3 CAP0(1)

4 CAP1(1)

CAPTURE/COMPARE3 CAP2

(1)

EXTERNAL COUNTER SPI AND SSP3 MAT0(1)

TIMER 0/TIMER 1/4 MAT1(1)

SERIAL INTERFACESTIMER 2/TIMER 3

3 MAT2(1)

4 MAT3(1)

AD0[7:0] UART0/UART1ADC

SCL0, SCL1(1)

SDA0, SDA1(1)

SCK0, SCK1(1)

MOSI0, MOSI1(1)

MISO0, MISO1(1)

SSEL0, SSEL1(1)

TXD0, TXD1(1)

RXD0, RXD1(1)

DSR1, CTS1,

RTS1, DTR1

DCD1, RI1

3.1.4 Functional description

Architectural overview

The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high

performance and very low power consumption. The ARM architecture is based on Reduced

Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are

much simpler than those of micro programmed Complex Instruction Set Computers (CISC). This

simplicity results in a high instruction throughput and impressive real-time interrupt response from a

small and cost-effective processor core.

Pipeline techniques are employed so that all parts of the processing and memory systems can

operate continuously. Typically, while one instruction is being executed, its successor is being

decoded, and a third instruction is being fetched from memory.

The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb,

which makes it ideally suited to high-volume applications with memory restrictions, or applications

where code density is an issue.

The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the

ARM7TDMI-S processor has two instruction sets:

The standard 32-bit ARM set.

A 16-bit Thumb set.

The Thumb setÕs 16-bit instruction length allows it to approach twice the density of standard

ARM code while retaining most of the ARMÕs performance advantage over a traditional 16-bit

processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit

register set as ARM code.

Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the

performance of an equivalent ARM processor connected to a 16-bit memory system.

The particular flash implementation in the LPC2101/2102/2103 allows for full speed execution

also in ARM mode. It is recommended to program performance critical and short code sections in

ARM mode. The impact on the overall code size will be minimal but the speed can be increased by 30

% over Thumb mode.

On-chip flash program memory

The LPC2101/2102/2103 incorporates a 8 kB, 16 kB or 32 kB flash memory system

respectively. This memory may be used for both code and data storage. Programming of the flash

memory may be accomplished in several ways. It may be programmed In System via the serial port.

The application program may also erase and/or program the flash while the application is running,

allowing a great degree of flexibility for data storage held firmware upgrades, etc. The entire flash

memory is available for user code as the boot loader.

On-chip static RAM

On-chip static RAM may be used for code and/or data storage. The SRAM may be accessed

as 8-bits, 16-bits, and 32-bits. The LPC2101/2102/2103 provides 2 kB, 4 kB or 8 kB of static RAM.

Memory map

The LPC2101/2102/2103 memory map incorporates several distinct regions.

In addition, the CPU interrupt vectors may be re-mapped to allow them to reside in either flash

memory (the default) or on-chip static RAM.

4.0 GB

AHB PERIPHERALS3.75 GB

APB PERIPHERALS3.5 GB

3.0 GB

RESERVED ADDRESS SPACE

2.0 GBBOOT BLOCK

RESERVED ADDRESS SPACE

8 kB ON-CHIP STATIC RAM (LPC2103)

4 kB ON-CHIP STATIC RAM (LPC2102)

2 kB ON-CHIP STATIC RAM (LPC2101)1.0 GB

RESERVED ADDRESS SPACE

32 kB ON-CHIP NON-VOLATILE MEMORY (LPC2103)

16 kB ON-CHIP NON-VOLATILE MEMORY (LPC2102)

8 kB ON-CHIP NON-VOLATILE MEMORY(LPC2101)

0.0 GB

0xFFFF FFFF

0xF000 0000

0xE000 0000

0xC000 0000

0x8000 0000 0x7FFF FFFF

0x7FFF E000 0x7FFF DFFF

0x4000 20000x4000 1FFF

0x4000 10000x4000 0FFF

0x4000 08000x4000 07FF

0x4000 0000

0x0000 80000x0000 7FFF

0x0000 40000x0000 3FFF

0x0000 20000x0000 1FFF

0x0000 0000

002aab822

LPC2101/2102/2103 memory map

Interrupt controller

The VIC accepts all of the interrupt request inputs and categorizes them as FIQ, vectored IRQ,

and non-vectored IRQ as defined by programmable settings. The programmable assignment scheme

means that priorities of interrupts from the various peripherals can be dynamically assigned and

adjusted.

FIQ has the highest priority. If more than one request is assigned to FIQ, the VIC combines

the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is

achieved when only one request is classified as FIQ, because then the FIQ service routine does not

need to branch into the interrupt service routine but can run from the interrupt vector location. If more

than one request is assigned to the FIQ class, the FIQ service routine will read a word from the VIC

that identifies which FIQ source(s) is (are) requesting an interrupt.

Vectored IRQs have the middle priority. Sixteen of the interrupt requests can be assigned to

this category. Any of the interrupt requests can be assigned to any of the 16 vectored IRQ slots,

among which slot 0 has the highest priority and slot 15 has the lowest.

Non-vectored IRQs have the lowest priority.

The VIC combines the requests from all the vectored and non-vectored IRQs to produce the

IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the

VIC and jumping there. If any of the vectored IRQs are pending, the VIC provides the address of the

highest-priority requesting IRQs service routine, otherwise it provides the address of a default routine

that is shared by all the non-vectored IRQs. The default routine can read another VIC register to see

what IRQs are active.

Interrupt sources

Each peripheral device has one interrupt line connected to the Vectored Interrupt Controller,

but may have several internal interrupt flags. Individual interrupt flags may also represent more than

one interrupt source.

Pin connect block

The pin connect block allows selected pins of the microcontroller to have more than one

function. Configuration registers control the multiplexers to allow connection between the pin and the

on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated,

and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is

not mapped to a related pin should be considered undefined.

The Pin Control Module with its pin select registers defines the functionality of the

microcontroller in a given hardware environment.

After reset all pins of Port 0 are configured as input with the following exceptions: If debug is

enabled, the JTAG pins will assume their JTAG functionality. The pins associated with the I2C0

interface are open-drain.

Fast general purpose parallel I/O

Device pins that are not connected to a specific peripheral function are controlled by the GPIO

registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or

clearing any number of outputs simultaneously. The value of the output register may be read back, as

well as the current state of the port pins.

LPC2101/2102/2103 introduce accelerated GPIO functions over prior LPC2000

devices:

GPIO registers are relocated to the ARM local bus for the fastest possible I/O timing.

Mask registers allow treating sets of port bits as a group, leaving other bits

unchanged.

All GPIO registers are byte addressable.

Entire port value can be written in one instruction.

Features

Bit-level set and clear registers allow a single instruction set or clear of any number

of bits in one port.

Direction control of individual bits.

Separate control of output set and clear.

All I/O default to inputs after reset.

10-bit A/D converter

The LPC2101/2102/2103 contains one analog to digital converter. It is a single 10-bit

successive approximation analog to digital converter with eight channels.

Features

Measurement range of 0 V to 3.3 V.

Each converter capable of performing more than 400,000 10-bit samples per second.

Burst conversion mode for single or multiple inputs.

Optional conversion on transition on input pin or Timer Match signal.

Every analog input has a dedicated result register to reduce interrupt overhead.

UARTs

The LPC2101/2102/2103 each contains two UARTs. In addition to standard transmit and

receive data lines, UART1 also provide a full modem control handshake interface.

Compared to previous LPC2000 microcontrollers, UARTs in LPC2101/2102/2103 include a

fractional baud rate generator for both UARTs. Standard baud rates such as 115200 can be achieved

with any crystal frequency above 2 MHz

Built-in fractional baud rate generator covering wide range of baud rates without a need for

external crystals of particular values.

Transmission FIFO control enables implementation of software (XON/XOFF) ßow control on

both UARTs.

UART1 is equipped with standard modem interface signals. This module also provides

full support for hardware ßow control (auto-CTS/RTS).

I2C-bus serial I/O controllers

The LPC2101/2102/2103 each contains two I2C-bus controllers.

The I2C-bus is bidirectional, for inter-IC control using only two wires: a Serial Clock Line

(SCL), and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate

as either a receiver-only device (e.g., LCD driver) or a transmitter with the capability to both receive

and send information such as serial memory. Transmitters and/or receivers can operate in either

master or slave mode, depending on whether the chip has to initiate a data transfer or is only

addressed. The I2C-bus is a multi-master bus, it can be controlled by more than one bus master

connected to it.

The I2C-bus implemented in LPC2101/2102/2103 supports bit rates up to 400 kbit/s (Fast I2C).

Features

o Compliant with standard I2C-bus interface.

o Easy to conÞgure as Master, Slave, or Master/Slave.

o Programmable clocks allow versatile rate control.

o Bidirectional data transfer between masters and slaves.

o Multi-master bus (no central master).

o Arbitration between simultaneously transmitting masters without corruption of serial data

on the bus.

o Serial clock synchronization allows devices with different bit rates to communicate via one

serial bus.

o Serial clock synchronization can be used as a handshake mechanism to suspend and resume

serial transfer.

o The I2C-bus can also be used for test and diagnostic purposes.

SPI serial I/O controller

The LPC2101/2102/2103 each contains one SPI controller. The SPI is a full duplex serial

interface, designed to handle multiple masters and slaves connected to a given bus. Only a single

master and a single slave can communicate on the interface during a given data transfer. During a data

transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits

to 16 bits of data to the master.

SSP serial I/O controller

The LPC2101/2102/2103 each contains one SSP. The SSP controller is capable of operation

on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus.

However, only a single master and a single slave can communicate on the bus during a given data

transfer. The SSP supports full duplex transfers, with data frames of 4 bits to 16 bits ßowing from the

master to the slave and from the slave to the master. Often only one of these data streams carries

meaningful data.

Features

o Compatible with Motorola SPI, 4-wire TIÕs SSI and National SemiconductorÕs

Microwire buses.

o Synchronous Serial Communication.

o Master or slave operation.

o 8-frame FIFOs for both transmit and receive.

o Four bits to 16 bits per frame.

General purpose 32-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally

supplied clock and optionally generate interrupts or perform other actions at specified timer values,

based on four match registers. It also includes four capture inputs to trap the timer value when an

input signals transitions, optionally generating an interrupt. Multiple pins can be selected to perform a

single capture or match function, providing an application with ÔorÕ and ÔandÕ, as well as

ÔbroadcastÕ functions among them.

The LPC2101/2102/2103 can count external events on one of the capture inputs if the

minimum external pulse is equal or longer than a period of the PCLK. In this configuration, unused

capture lines can be selected as regular timer capture inputs or used as external interrupts.

Features

o A 32-bit timer/counter with a programmable 32-bit prescaler.

o External event counter or timer operation.

o Four 32-bit capture channels per timer/counter that can take a snapshot of the timer value

when an input signals transitions. A capture event may also optionally generate an interrupt.

o Four 32-bit match registers that allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

Reset timer on match with optional interrupt generation.

Set LOW on match.

General purpose 16-bit timers/external event counters

The Timer/Counter is designed to count cycles of the peripheral clock (PCLK) or an externally

supplied clock and optionally generate interrupts or perform other actions at speciÞed timer values,

based on four match registers. It also includes three capture inputs to trap the timer value when an

input signal transitions, optionally generating an interrupt. Multiple pins can be selected to perform a

single capture or match function, providing an application with ÔorÕ and ÔandÕ, as well as

ÔbroadcastÕ functions among them.

The LPC2101/2102/2103 can count external events on one of the capture inputs if the minimum

external pulse is equal or longer than a period of the PCLK. In this conÞguration, unused capture lines

can be selected as regular timer capture inputs or used as external interrupts.

Features

o Two 16-bit timer/counters with a programmable 16-bit prescaler.

o External event counter or timer operation.

o Three 16-bit capture channels that can take a snapshot of the timer value when an input

signal transitions. A capture event may also optionally generate an interrupt.

o Four 16-bit match registers that allow:

Continuous operation with optional interrupt generation on match.

Stop timer on match with optional interrupt generation.

Reset timer on match with optional interrupt generation.

o Four external outputs per timer/counter corresponding to match registers, with the

following capabilities:

Set LOW on match.

Set HIGH on match.

Toggle on match.

Do nothing on match.

Watchdog timer

The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time

if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user

program fails to ÔfeedÕ (or reload) the watchdog within a predetermined amount of time.

Real-time clock

The Real-Time Clock (RTC) is designed to provide a set of counters to measure time when

normal or idle operating mode is selected. The RTC has been designed to use little power, making it

suitable for battery powered systems where the CPU is not running continuously (Idle mode).

Features

o Measures the passage of time to maintain a calendar and clock.

o Ultra-low power design to support battery powered systems.

o Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of

Year.

o Can use either the RTC dedicated 32 kHz oscillator input or clock derived from the

external crystal/oscillator input at XTAL1. Programmable Reference Clock Divider allows

Þne adjustment of the RTC.

o Dedicated power supply pin can be connected to a battery or the main 3.3 V.

Crystal oscillator

On-chip integrated oscillator operates with external crystal in range of 1 MHz to 25 MHz. The

oscillator output frequency is called fosc and the ARM processor clock frequency is referred to as

CCLK for purposes of rate equations, etc. fosc and CCLK are the same value unless the PLL is running

and connected.

PLL

The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input

frequency is multiplied up into the range of 10 MHz to 70 MHz with a Current Controlled Oscillator

(CCO). The multiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be

higher than 6 on this family of microcontrollers due to the upper frequency limit of the CPU). The

CCO operates in the range of 156 MHz to 320 MHz, so there is an additional divider in the loop to

keep the CCO within its frequency range while the PLL is providing the desired output frequency.

The output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. Since the

minimum output divider value is 2, it is insured that the PLL output has a 50 % duty cycle. The PLL is

turned off and bypassed following a chip reset and may be enabled by software. The program must

configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source.

The PLL settling time is 100 s.

Reset and wake-up timer

Reset has two sources on the LPC2101/2102/2103: the RESET pin and watchdog reset. The

RESET pin is a Schmitt trigger input pin with an additional glitch Þlter. Assertion of chip reset by any

source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset

to remain asserted until the external reset is de-asserted, the oscillator is running, a fixed number of

clocks have passed, and the on-chip flash controller has completed its initialization.

When the internal reset is removed, the processor begins executing at address 0, which is the

reset vector. At that point, all of the processor and peripheral registers have been initialized to

predetermined reset values.

The wake-up timer ensures that the oscillator and other analog functions required for chip

operation are fully functional before the processor is allowed to execute instructions. This is important

at power on, all types of reset, and whenever any of the aforementioned functions are turned off for

any reason. Since the oscillator and other functions are turned off during Power-down mode, any

wake-up of the processor from Power-down mode makes use of the wake-up timer.

The wake-up timer monitors the crystal oscillator as the means of checking whether it is safe

to begin code execution. When power is applied to the chip, or some event caused the chip to exit

Power-down mode, some time is required for the oscillator to produce a signal of sufficient

amplitude to drive the clock logic. The amount of time depends on many factors, including the rate

of VDD ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz

crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the

oscillator itself under the existing ambient conditions.

Code security

This feature of the LPC2103 allows an application to control whether it can be debugged or

protected from observation.

If after reset on-chip boot loader detects a valid checksum in flash and reads 0x8765 4321

from address 0x1FC in flash, debugging will be disabled and thus the code in flash will be protected

from observation. Once debugging is disabled, it can only be enabled by performing a full chip erase

using the ISP.

External interrupt inputs

The LPC2101/2102/2103 include up to three edge or level sensitive External Interrupt Inputs

as selectable pin functions. When the pins are combined, external events can be processed as three

independent interrupt signals. The External Interrupt Inputs can optionally be used to wake-up the

processor from Power-down mode.

Additionally all 10 capture input pins can also be used as external interrupts without the

option to wake the device up from Power-down mode.

Memory mapping control

The Memory Mapping Control alters the mapping of the interrupt vectors that appear

beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the on-chip flash

memory, or to the on-chip static RAM. This allows code running in different memory spaces to have

control of the interrupts.

Power control

The LPC2101/2102/2103 supports two reduced power modes: Idle mode and

Power-down mode.

In Idle mode, execution of instructions is suspended until either a reset or interrupt occurs.

Peripheral functions continue operation during Idle mode and may generate interrupts to cause the

processor to resume execution. Idle mode eliminates power used by the processor itself, memory

systems and related controllers, and internal buses.

In Power-down mode, the oscillator is shut down and the chip receives no internal clocks. The

processor state and registers, peripheral registers, and internal SRAM values are preserved throughout

Power-down mode and the logic levels of chip output pins remain static. The Power-down mode can

be terminated and normal operation resumed by either a reset or certain specific interrupts that are

able to function without clocks. Since all dynamic operation of the chip is suspended, Power-down

mode reduces chip power consumption to nearly zero.

Selecting an external 32 kHz clock instead of the PCLK as a clock-source for the on-chip RTC

will enable the microcontroller to have the RTC active during Power-down mode. Power-down

current is increased with RTC active. However, it is significantly lower than in Idle mode.

A Power Control for Peripherals feature allows individual peripherals to be turned off if they

are not needed in the application, resulting in additional power savings during active and idle mode.

APB bus

The APB divider determines the relationship between the processor clock (CCLK) and the

clock used by peripheral devices (PCLK). The APB divider serves two purposes. The first is to

provide peripherals with the desired PCLK via APB bus so that they can operate at the speed chosen

for the ARM processor. In order to achieve this, the APB bus may be slowed down to 12 to 14 of the

processor clock rate. Because the APB bus must work properly at power-up (and its timing cannot be

altered if it does not work since the APB divider control registers reside on the APB bus), the default

condition at reset is for the APB bus to run at 14 of the processor clock rate. The second purpose of

the APB divider is to allow power savings when an application does not require any peripherals to run

at the full processor rate. Because the APB divider is connected to the PLL output, the PLL remains

active (if it was running) during Idle mode.

Emulation and debugging

The LPC2101/2102/2103 support emulation and debugging via a JTAG serial port.

Embedded ICE

Standard ARM Embedded ICE logic provides on-chip debug support. The debugging of the

target system requires a host computer running the debugger software and an Embedded ICE protocol

convertor. Embedded ICE protocol convertor converts the Remote Debug Protocol commands to the

JTAG data needed to access the ARM core.

3.2 POWER SUPPLY

All digital circuits require regulated power supply. In this article we are going to learn how to

get a regulated positive supply from the mains supply.

Circuit diagram:

Fig 2.3. Circuit Diagram of power supply

3.3 MAX 232

RS-232 WAVEFORM

TTL/CMOS Serial Logic Waveform

The diagram above shows the expected waveform from the UART when using the

common 8N1 format. 8N1 signifies 8 Data bits, No Parity and 1 Stop Bit. The RS-232 line, when idle

is in the Mark State (Logic 1). A transmission starts with a start bit which is (Logic 0). Then each bit is

sent down the line, one at a time. The LSB (Least Significant Bit) is sent first. A Stop Bit (Logic 1) is

then appended to the signal to make up the transmission.

The data sent using this method, is said to be framed. That is the data is framed between

a Start and Stop Bit.

 RS-232 Voltage levels

+3 to +25 volts to signify a "Space" (Logic 0)                                              

-3 to -25 volts for a "Mark" (logic 1).

Any voltage in between these regions (i.e. between +3 and -3 Volts) is undefined.

The data byte is always transmitted least-significant-bit first.

The bits are transmitted at specific time intervals determined by the baud rate of the serial

signal.  This is the signal present on the RS-232 Port of your computer, shown below.

RS-232 Logic Waveform

2.3.2 RS-232 LEVEL CONVERTER

Standard serial interfacing of microcontroller (TTL) with PC or any RS232C Standard

device requires TTL to RS232 Level converter. A MAX232 is used for this purpose. It provides 2-

channel RS232C port and requires external 10uF capacitors.

The driver requires a single supply of +5V.

 MAX-232 includes a Charge Pump, which generates +10V and -10V from a single 5v supply.

 Serial communication:

When a processor communicates with the outside world, it provides data in byte sized

chunks. Computers transfer data in two ways: parallel and serial. In parallel data transfers, often more

lines are used to transfer data to a device and 8 bit data path is expensive. The serial communication

transfer uses only a single data line instead of the 8 bit data line of parallel communication which

makes the data transfer not only cheaper but also makes it possible for two computers located in two

different cities to communicate over telephone.

Serial data communication uses two methods, asynchronous and synchronous. The

synchronous method transfers data at a time while the asynchronous transfers a single byte at a time.

There are some special IC chips made by many manufacturers for data communications. These chips

are commonly referred to as UART (universal asynchronous receiver-transmitter) and USART

(universal synchronous asynchronous receiver transmitter). The AT89C51 chip has a built in UART.

In asynchronous method, each character is placed between start and stop bits. This is

called framing. In data framing of asynchronous communications, the data, such as ASCII characters,

are packed in between a start and stop bit. We have a total of 10 bits for a character: 8 bits for the

ASCII code and 1 bit each for the start and stop bits. The rate of serial data transfer communication is

stated in bps or it can be called as baud rate.

To allow the compatibility among data communication equipment made by various

manufacturers, and interfacing standard called RS232 was set by the Electronics industries Association

in 1960. Today RS232 is the most widely used I/O interfacing standard. This standard is used in PCs

and numerous types of equipment. However, since the standard was set long before the advent of the

TTL logic family, its input and output voltage levels are not TTL compatible. In RS232, a 1 bit is

represented by -3 to -25V, while a 0 bit is represented +3 to +25 V, making -3 to +3 undefined. For

this reason, to connect any RS232 to a microcontroller system we must use voltage converters such as

MAX232 to connect the TTL logic levels to RS232 voltage levels and vice versa. MAX232 ICs are

commonly referred to as line drivers.

The RS232 cables are generally referred to as DB-9 connector. In labeling, DB-9P refers

to the plug connector (male) and DB-9S is for the socket connector (female). The simplest connection

between a PC and microcontroller requires a minimum of three pin, TXD, RXD, and ground. Many of

the pins of the RS232 connector are used for handshaking signals. They are bypassed since they are

not supported by the UART chip.

IBM PC compatible computers based on x86(8086, 80286, 386, 486 and Pentium)

microprocessors normally have two COM ports. Both COM ports have RS232 type connectors. Many

PCs use one each of the DB-25 and DB-9 RS232 connectors. The COM ports are designated as COM1

and COM2. We can connect the serial port to the COM 2 port of a PC for serial communication

experiments. We use a DB9 connector in our arrangement.

3.4 LDR

Working

A photo resistor or Light Dependent Resistor or CdS Cell is a resistor whose resistance

decreases with increasing incident light intensity. It can also be referred to as a photoconductor.

A photo resistor is made of a high resistance semiconductor. If light falling on the device is of

high enough frequency, photons absorbed by the semiconductor give bound electrons enough

energy to jump into the conduction band. The resulting free electron (and its whole partner)

conducts electricity, thereby lowering resistance.

A photoelectric device can be either intrinsic or extrinsic. An intrinsic semiconductor has

its own charge carriers and is not an efficient semiconductor, e.g. silicon. In intrinsic devices the

only available electrons are in the valence band, and hence the photon must have enough energy

to excite the electron across the entire band gap. Extrinsic devices have impurities, also called

dopants, added whose ground state energy is closer to the conduction band; since the electrons

don't have as far to jump, lower energy photons (i.e., longer wavelengths and lower frequencies)

are sufficient to trigger the device. If a sample of silicon has some of its atoms replaced by

phosphorus atoms (impurities), there will be extra electrons available for conduction. This is an

example of an extrinsic semiconductor.

A Light Dependent Resistor (LDR, photoconductor, or photocell) is a device which has a

resistance which varies according to the amount of light falling on its surface. They will be having a

resistance of 1 Mohm in total darkness, and a resistance of a 1 to 10 of kohm in bright light. A

photoelectric device can be either intrinsic or extrinsic.

Applications:

An LDR can even be used in a simple remote control circuit using the backlight of a mobile

phone to turn on a device - call the mobile from anywhere in the world, it lights up the LDR, and lighting

can be turned on remotely!

There are two basic circuits using light dependent resistors - the first is activated by darkness, the

second is activated by light.

In the circuit diagram on the left, the led lights up whenever the LDR is in darkness. The 10K

variable resistor is used to fine-tune the level of darkness required before the LED lights up. The 10K

standard resistor can be changed as required to achieve the desired effect, although any replacement must

be at least 1K to protect the transistor from being damaged by excessive current.

By swapping the LDR over with the 10K and 10K variable resistors , the circuit will be activated

instead by light. Whenever sufficient light falls on the LDR (manually fine-tuned using the 10K variable

resistor), the LED will light up.

The circuits shown above are not practically useful. In a real world circuit, the LED (and

resistor) between the positive voltage input (Vin) and the collector (C) of the transistor would be

replaced with the device to be powered.

Typically a relay is used - particularly when the low voltage light detecting circuit is used

to switch on (or off) a 240V mains powered device. A diagram of that part of the circuit is shown

above. When darkness falls (if the LDR circuit is configured that way around), the relay is

triggered and the 240V device (for example a security light) - switches on.

Measure Light Intensity using Light Dependent Resistor (LDR):

The relationship between the resistance RL and light intensity Lux for a typical LDR is

RL = 500 / Lux Kohm

With the LDR connected to 5V through a 3.3K resistor, the output voltage of the LDR is

VO = 5*RL / (RL+3.3)

Reworking the equation, we obtain the light intensity

Lux = (2500/Vo - 500)/3

3.5 LCD MODULE

To display interactive messages we are using LCD Module. We examine an intelligent

LCD display of two lines,16 characters per line that is interfaced to the controllers. The protocol

(handshaking) for the display is as shown. Whereas D0 to D7th bit is the Data lines, RS, RW and

EN pins are the control pins and remaining pins are +5V, -5V and GND to provide supply.

Where RS is the Register Select, RW is the Read Write and EN is the Enable pin.

The display contains two internal byte-wide registers, one for commands (RS=0) and the

second for characters to be displayed (RS=1). It also contains a user-programmed RAM area (the

character RAM) that can be programmed to generate any desired character that can be formed

using a dot matrix. To distinguish between these two data areas, the hex command byte 80 will

be used to signify that the display RAM address 00h will be chosen.Port1 is used to furnish the

command or data type, and ports 3.2 to3.4 furnish register select and read/write levels.

The display takes varying amounts of time to accomplish the functions as listed. LCD bit

7 is monitored for logic high (busy) to ensure the display is overwritten.

Liquid Crystal Display also called as LCD is very helpful in providing user interface as

well as for debugging purpose. The most common type of LCD controller is HITACHI 44780

which provides a simple interface between the controller & an LCD. These LCD's are very

simple to interface with the controller as well as are cost effective.

2x16 Line Alphanumeric LCD Display

The most commonly used ALPHANUMERIC displays are 1x16 (Single Line & 16

characters), 2x16 (Double Line & 16 character per line) & 4x20 (four lines & Twenty characters

per line). 

The LCD requires 3 control lines (RS, R/W & EN) & 8 (or 4) data lines. The number on

data lines depends on the mode of operation. If operated in 8-bit mode then 8 data lines + 3

control lines i.e. total 11 lines are required. And if operated in 4-bit mode then 4 data lines + 3

control lines i.e. 7 lines are required. How do we decide which mode to use? It’s simple if you

have sufficient data lines you can go for 8 bit mode & if there is a time constrain i.e. display

should be faster then we have to use 8-bit mode because basically 4-bit mode takes twice as

more time as compared to 8-bit mode.

 Pin  Symbol Function

 1  Vss  Ground

 2  Vdd  Supply Voltage

 3  Vo  Contrast Setting

 4  RS  Register Select

 5  R/W  Read/Write Select

 6  En  Chip Enable Signal

 7-14  DB0-DB7  Data Lines

 15  A/Vee  Gnd for the backlight

 16  K  Vcc for backlight

When RS is low (0), the data is to be treated as a command. When RS is high (1), the data

being sent is considered as text data which should be displayed on the screen.

When R/W is low (0), the information on the data bus is being written to the LCD. When

RW is high (1), the program is effectively reading from the LCD. Most of the times there is no

need to read from the LCD so this line can directly be connected to Gnd thus saving one

controller line.

The ENABLE pin is used to latch the data present on the data pins. A HIGH - LOW

signal is required to latch the data. The LCD interprets and executes our command at the instant

the EN line is brought low. If you never bring EN low, your instruction will never be executed.

COMMANDS USED IN LCD

3.6 ULN2003

ULN is mainly suited for interfacing between low-level circuits and multiple peripheral

power loads,. The series ULN20XX high voltage, high current Darlington arrays feature

continuous load current ratings. The driving circuitry in- turn decodes the coding and conveys

the necessary data to the stepper motor, this module aids in the movement of the arm through

steppers

The driver makes use of the ULN2003 driver IC, which contains an array of 7 power

Darlington arrays, each capable of driving 500mA of current. At an approximate duty cycle,

depending on ambient temperature and number of drivers turned on, simultaneously typical

power loads totaling over 230w can be controlled.

The device has base resistors, allowing direct connection to any common logic family. All

the emitters are tied together and brought out to a separate terminal. Output protection diodes are

included; hence the device can drive inductive loads with minimum extra components. Typical

loads include relays, solenoids, stepper motors, magnetic print hammers, multiplexed LED,

incandescent displays and heaters.

Darlington Pair

A Darlington pair is two transistors that act as a single transistor but with a much higher current

gain.

Current gain

Transistors have a characteristic called current gain. This is referred to as its hFE. The

amount of current that can pass through the load when connected to a transistor that is turned on

equals the input current x the gain of the transistor (hFE) The current gain varies for different

transistor and can be looked up in the data sheet for the device. Typically it may be 100. This

would mean that the current available to drive the load would be 100 times larger than the input

to the transistor.

USE OF A DARLINGTON PAIR

In some application the amount of input current available to switch on a transistor is very

low. This may mean that a single transistor may not be able to pass sufficient current required by

the load.

As stated earlier this equals the input current x the gain of the transistor (hFE). If it is not

be possible to increase the input current then we need to increase the gain of the transistor. This

can be achieved by using a Darlington Pair.

A Darlington Pair acts as one transistor but with a current gain that equals:

Total current gain (hFE total) = current gain of transistor 1 (hFE t1) x current gain of

transistor 2 (hFE t2) So for example if you had two transistors with a current gain (hFE) = 100:

(hFE total) = 100 x 100

(hFE total) = 10,000

You can see that this gives a vastly increased current gain when compared to a single

transistor. Therefore this will allow a very low input current to switch a much bigger load

current.

Base Activation Voltage

Normally to turn on a transistor the base input voltage of the transistor will need to be

greater that 0.7V. As two transistors are used in a Darlington Pair this value is doubled.

Therefore the base voltage will need to be greater than 0.7V x 2 = 1.4V.

It is also worth noting that the voltage drop across collector and emitter pins of the

Darlington Pair when the turn on will be around 0.9V Therefore if the supply voltage is 5V (as

above) the voltage across the load will be will be around 4.1V (5V – 0.9V)

3.7 STEPPER MOTOR

A stepper motor is an electromechanical device which converts electrical pulses into

discrete mechanical movements. The shaft or spindle of a stepper motor rotates in discrete step

increments when electrical command pulses are applied to it in the proper sequence. The motors

rotation has several direct relationships to these applied input pulses. The sequence of the applied

pulses is directly related to the direction of motor shafts rotation. The speed of the motor shafts

rotation is directly related to the frequency of the input pulses and the length of rotation is

directly related to the number of input pulses applied.

Fundamentals of operation

Stepper motors operate differently from DC brush motors, which rotate when voltage is

applied to their terminals. Stepper motors, on the other hand, effectively have multiple "toothed"

electromagnets arranged around a central gear-shaped piece of iron. The electromagnets are

energized by an external control circuit, such as a microcontroller. To make the motor shaft turn,

first one electromagnet is given power, which makes the gear's teeth magnetically attracted to the

electromagnet's teeth. When the gear's teeth are thus aligned to the first electromagnet, they are

slightly offset from the next electromagnet. When the next electromagnet is turned on and the

first is turned off, the gear rotates slightly to align with the next one, and from there the process

is repeated. Each of those slight rotations is called a "step", with an integer number of steps

making a full rotation. In that way, the motor can be turned by a precise angle.

Stepper motor characteristics

1. Stepper motors are constant power devices.

2. As motor speed increases, torque decreases. (Most motors exhibit maximum torque when

stationary, however the torque of a motor when stationary 'holding torque' defines the

ability of the motor to maintain a desired position while under external load).

3. The torque curve may be extended by using current limiting drivers and increasing the

driving voltage (sometimes referred to as a 'chopper' circuit, there are several off the shelf

driver chips capable of doing this in a simple manner).

4. Steppers exhibit more vibration than other motor types, as the discrete step tends to snap

the rotor from one position to another (called a detent). The vibration makes stepper

motors noisier than DC motors.

5. This vibration can become very bad at some speeds and can cause the motor to lose

torque or lose direction. This is because the rotor is being held in a magnetic field which

behaves like a spring. On each step the rotor overshoots and bounces back and forth,

"ringing" at its resonant frequency. If the stepping frequency matches the resonant

frequency then the ringing increases and the motor comes out of synchronism, resulting

in positional error or a change in direction. At worst there is a total loss of control and

holding torque so the motor is easily overcome by the load and spins almost freely.

6. The effect can be mitigated by accelerating quickly through the problem speeds range,

physically damping (frictional damping) the system, or using a micro-stepping driver.

7. Motors with a greater number of phases also exhibit smoother operation than those with

fewer phases (this can also be achieved through the use of a micro stepping drive)

Stepper Motor Advantages and Disadvantages

Advantages:

1. The rotation angle of the motor is proportional to the input pulse.

2. The motor has full torque at standstill (if the windings are energized)

3. Precise positioning and repeatability of movement since good stepper motors have an accuracy

of 3 – 5% of a step and this error is non cumulative from one step to the next.

4. Excellent response to starting/ stopping/reversing.

5. Very reliable since there are no contact brushes in the motor. Therefore the life of the motor

Simply depends on the life of the bearing.

6. The motors response to digital input pulses provides open-loop control, making the motor

simpler and less costly to control.

7. It is possible to achieve very low speed synchronous rotation with a load that is directly

coupled to the shaft.

8. A wide range of rotational speeds can be realized as the speed is proportional to the frequency

of the input pulses.

Disadvantages

1. Resonances can occur if not properly controlled.

2. Not easy to operate at extremely high speeds.

CHAPTER 4

SOFTWARE DEVELOPMENT

4.1 Introduction:

In this chapter the software used and the language in which the program code is defined

is mentioned and the program code dumping tools are explained. The chapter also documents the

development of the program for the application. This program has been termed as “Source code”.

Before we look at the source code we define the two header files that we have used in the code.

4.2 Tools Used:

Figure 4.1 Keil Software- internal stages

4.3 SOURCE CODE:

////////////////--------MAIN----------/////////////

#include<LPC2103.H>

#include<string.h>

#define GPIO_Port0s_IODIR IODIR

#define Set_Port0s IOSET

#define Clear_Port0s IOCLR

#define Port0_Set IOPIN

#define Logic_Low 0

#define Port0 0

#define Port1 1

#include "LCD.c"

#include "adc0.c"

#include "App.c"

int PinStatus_Port(unsigned char ,unsigned int);

void Multichannel_Data_Display(void);

void LCD_Lable_display(void);

unsigned char x;

main()

{

GPIO_Port0s_IODIR = (LCD_Data|RS|EN|stepper_motor); //output=1 //

input=0

Clear_Port0s=stepper_motor;

Lcd_Init();

LCD_Lable_display();

Delay(150);

ADC0_Init();

Lcd_Data_Str(2,1,"Seeker System");

Delay(500);

LCD_Lable_display();

while(1)

{

Multichannel_Data_Display();

}

}

void Multichannel_Data_Display(void)

{

ADC0_Channel_3();

Delay(25);

ADC0_Channel_2();

Delay(25);

if(lux1>lux2)

{

Stepper_Motor_clk();

}

if(lux2>lux1)

{

Stepper_Motor_aclk();

}}

PinStatus_Port(unsigned char port,unsigned int pin)

{

if(port==0)

{

x=(Port0_Set& (1<<pin))?1:0;

}

return x;

}

/////////ADC.c///////////:

unsigned int Divisor;

unsigned char v1,v2,v3,k,t1,t2,t3,h1,h2,h3,l1,l2,l3,l4;\

unsigned char samples;

unsigned int RH,lux1,lux2;

unsigned int r;

float ADC_VALUE;

void ADC0_Init(void);

//void ADC0_Channel_1(void);

void ADC0_Channel_2(void);

void ADC0_Channel_3(void);

void ADC0_Channel_4(void);

void ADC0_Channel_5(void);

void ADC0_Init(void)

{

PCONP|=(1<<12);

PINSEL0|=0X03F30005;

PINSEL1|=0X00030000;

ADCR &=0X00000000;

ADCR |=0X00000600;

ADCR |=0X00010000;

ADCR &=0XFFF1FFFF;

ADCR |=0X00200000;

ADCR |=(1<<24);

}

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

void ADC0_Channel_2(void) //light //P0.28

{

unsigned int a1,b1,c1,p;

ADCR &=0xFFFFFFF0;

ADCR |=0X00000004;

ADC_VALUE=0X00000000;

Delay(10);

while((ADDR2&0X80000000)==0);

ADC_VALUE=0.003222*((ADDR2&0X0000FFC0)>>6);

Delay(10);

a1=2500/ADC_VALUE;

b1=a1-500;

c1=b1/2.2;

lux1= c1-115; //((2500/r1)-500)/2.2;

l1=lux1/1000;

k=lux1%1000;

l2=k/100;

p=k%100;

l3=p/10;

l4=p%10;

Delay(10);

Lcd_Data_Chr(1,1,11,l1+48);

Lcd_Data_Chr(1,1,12,l2+48);

Lcd_Data_Chr(1,1,13,l3+48);

Lcd_Data_Chr(1,1,14,l4+48);

//Lcd_Data_Chr(1,1,1,'L');

}

//////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

/////////////////////////////////////////////////////////////////////////////////////////////////////////////////////

void ADC0_Channel_3(void) //temp P0.10

{

unsigned int a1,b1,c1,p;

ADCR &=0xFFFFFFF0;

ADCR |=0X00000008;

ADC_VALUE=0X00000000;

Delay (10);

while ((ADDR3&0X80000000)==0);

ADC_VALUE=0.003222*((ADDR3&0X0000FFC0)>>6);

Delay (10);

Delay (10);

a1=2500/ADC_VALUE;

b1=a1-500;

c1=b1/2.2;

lux2= c1-115; //((2500/r1)-500)/2.2;

l1=lux2/1000;

k=lux2%1000;

l2=k/100;

p=k%100;

l3=p/10;

l4=p%10;

Delay(10);

Lcd_Data_Chr(1,2,11,l1+48);

Lcd_Data_Chr(1,2,12,l2+48);

Lcd_Data_Chr(1,2,13,l3+48);

Lcd_Data_Chr(1,2,14,l4+48);

//Lcd_Data_Chr(1,2,16,'L');

}

/*

void ADC0_Channel_6(void)

{

AD0CR &=0xFFFFFF0F;

AD0CR |=0X00000040;

ADC_VALUE=0X00000000;

Delay(10);

while((AD0DR6&0X80000000)==0);

ADC_VALUE=0.003222*((AD0DR6&0X0000FFC0)>>6);

Delay(10);

r=ADC_VALUE*100;

k=r/10;

v1=k/10;

v2=k%10;

v3=r%10;

UART0_TX_Chr (v1+48);

UART0_TX_Str (".");

UART0_TX_Chr (v2+48);

UART0_TX_Chr (v3+48);

Delay(25);

}

void ADC0_Channel_7(void)

{

AD0CR &=0xFFFFFF0F;

AD0CR |=0X00000080;

ADC_VALUE=0X00000000;

Delay(10);

while((AD0DR7&0X80000000)==0);

ADC_VALUE=0.003222*((AD0DR7&0X0000FFC0)>>6);

Delay(10);

r=ADC_VALUE*100;

k=r/10;

v1=k/10;

v2=k%10;

v3=r%10;

UART0_TX_Chr (v1+48);

UART0_TX_Str (".");

UART0_TX_Chr (v2+48);

UART0_TX_Chr (v3+48);

Delay(25);

}

*/

////////Application.c///////////:

#define step1 (1<<4)

#define step2 (1<<5)

#define step3 (1<<6)

#define step4 (1<<7)

#define stepper_motor (step1|step2|step3|step4)

unsigned char LCD_CLEAR=0x01;

void LCD_Lable_display(void)

{

Lcd_Data_Chr(0,0,0,LCD_CLEAR);

Lcd_Data_Str(1,8,"L1:");

Delay(10);

Lcd_Data_Str(2,8,"L2:");

Delay(10);

}

void Stepper_Motor_clk(void)

{

Set_Port0s=step1,Clear_Port0s=step2,Clear_Port0s=step3,Clear_Port0s=step4;

Delay(15);

Clear_Port0s=step1,Set_Port0s=step2,Clear_Port0s=step3,Clear_Port0s=step4;

Delay(15);

Clear_Port0s=step1,Clear_Port0s=step2,Set_Port0s=step3,Clear_Port0s=step4;

Delay(15);

Clear_Port0s=step1,Clear_Port0s=step2,Clear_Port0s=step3,Set_Port0s=step4;

Delay(15);

Clear_Port0s=step1,Clear_Port0s=step2,Clear_Port0s=step3,Clear_Port0s=step4;

Clear_Port0s=stepper_motor;

}

void Stepper_Motor_aclk(void)

{

Clear_Port0s=step1,Clear_Port0s=step2,Clear_Port0s=step3,Set_Port0s=step4;

Delay(15);

Clear_Port0s=step1,Clear_Port0s=step2,Set_Port0s=step3,Clear_Port0s=step4;

Delay(15);

Clear_Port0s=step1,Set_Port0s=step2,Clear_Port0s=step3,Clear_Port0s=step4;

Delay(15);

Set_Port0s=step1,Clear_Port0s=step2,Clear_Port0s=step3,Clear_Port0s=step4;

Delay(15);

Clear_Port0s=step1,Clear_Port0s=step2,Clear_Port0s=step3,Clear_Port0s=step4;

Clear_Port0s=stepper_motor;

}

///////////LCD.c/////////////:

#define LCD_Data (0xFF)<<16

#define RS (0xFFFFFFFF)<<31

#define EN (1<<30)

unsigned char LCD_C=0,LCD_D=1,Wr_Data=1;

void Delay(unsigned int );

void Lcd_Init(void);

int Lcd_Data_Chr(unsigned char ,unsigned char ,unsigned char ,unsigned char);

int Lcd_Data_Str(unsigned char ,unsigned char ,unsigned char temp[]);

int Lcd_Wr(unsigned char );

/****************************************************************************/

Lcd_Data_(0-cmd:1-data,line no,position,char to disp on LCD);

*****************************************************************************/

void Lcd_Init(void)

{

unsigned char LCD_2_LINE=0x38;

unsigned char LCD_CLEAR=0X01;

unsigned char DISPLAY_ON=0X0E;

unsigned char LCD_CURSOR_OFF=0x0C;

Lcd_Data_Chr(0,0,0,LCD_2_LINE);

Lcd_Data_Chr(0,0,0,DISPLAY_ON);

Lcd_Data_Chr(0,0,0,LCD_CURSOR_OFF);

Lcd_Data_Chr(0,0,0,LCD_CLEAR)

}

Lcd_Data_Chr(unsigned char RS1 ,unsigned char line,unsigned char position,unsigned char

temp1)

{

unsigned char x;

if(RS1==0)

{

Set_Port0s= (temp1<<16)&LCD_Data;

Lcd_Wr(LCD_C);

Clear_Port0s=LCD_Data;

}

if(RS1==1)

{

if(line==1)

{

x=0x7f+position;

Set_Port0s= (x<<16)&LCD_Data;

Lcd_Wr(LCD_C);

Clear_Port0s=LCD_Data;

}

if(line==2)

{

x=0xbf+position;

Set_Port0s= (x<<16)&LCD_Data;

Lcd_Wr(LCD_C);

Clear_Port0s=LCD_Data;

}

Set_Port0s= (temp1<<16)&LCD_Data;

Lcd_Wr(LCD_D);

Clear_Port0s=LCD_Data;

Delay(2);

}

}

Lcd_Data_Str(unsigned char line1,unsigned char position,unsigned char temp[])

{

unsigned int p;

unsigned char t;

if(line1==1)

{

p=0x7f+position;

Lcd_Data_Chr(0,0,0,(Set_Port0s=(p<<16)&LCD_Data));

}

if(line1==2)

{

p=0xbf+position;

Lcd_Data_Chr(0,0,0,(Set_Port0s=(p<<16)&LCD_Data));

}

while(temp[t]!='\0')

{

Set_Port0s= (temp[t]<<16)&LCD_Data;

Lcd_Wr(LCD_D);

t++;

Clear_Port0s=LCD_Data;

Delay(3);

}

}

Lcd_Wr(unsigned char r)

{

if(r==1)

{

Set_Port0s= RS;

Set_Port0s= EN;

Delay(1);

Clear_Port0s= EN;

}

if(r==0)

{

Clear_Port0s= RS;

Set_Port0s= EN;

Delay(1);

Clear_Port0s= EN;

}

}

void Delay(unsigned int time)

{

unsigned int i,j;

for(i=0;i<time;i++)

for(j=0;j<25000;j++);

}

CHAPTER 5

RESULTS AND ANALYSIS

Step1: open the NEW UVISION project which is in the project option in the tool bar.

Step2: save the project with the required name and click save button

Step:3 select the device from NXP options the window which comes after saving the

project.

Step 4: select the LPC 2148 from the NXP options

Step 5: click yes in the startup code of LPC 2148 window

Step 6: select the new file from the file options to write the C code

Step 7: a new text file will open which we have to write the following code

Step 8 : write the code require for ur applications

Step 9: save the text file as .C file

Step 10: Add the saved .C file p by right clicking the Source Group Option1 and u will get drop

down window in that select Add Files to Group

Step 11: select the saved .c file from the window which is showing to add the file by clicking the

add tab.

Step 12: thus .C file is added to the Source Group is clearly seen

Step 13: press the icon that shows Rebuilt Target which proceeds for the Linking if the .C file.

Step 14: Re-built All Target files for complete process of assembling->Compiling ->linking->

generating .hex file.

Step 15: press the start/stop debug icon for debugging of the code which written. Following are

debugging windows press F11 for step by step debug.

Window 1 :

Window 2:

CHAPTER 6

CONCLUSION

The project “MICROCONTROLLER BASED INFRARED SEEKING

TARGET TRACKING SYSTEM” has been successfully designed and tested.

Integrating features of all the hardware components used have developed it. Presence of

every module has been reasoned out and placed carefully thus contributing to the best

working of the unit. Secondly, using highly advanced IC’s and with the help of growing

technology the project has been successfully implemented.

BIBILOGRAPHY

1. WWW.MITEL.DATABOOK.COM

2. WWW.ATMEL.DATABOOK.COM

3. WWW.FRANKLIN.COM

4. WWW.KEIL.COM

en.wikipedia.org/wiki/ZigBee

WWW.ZIGBEE.ORG/

www.nxp.com/documents/user_manual/UM1 http://www.futurlec.com/GPS.shtml013

HTTP://EN.WIKIPEDIA.ORG/WIKI/GLOBAL_POSITIONING_SYSTEM9.PDF

http://electronics.howstuffworks.com/gadgets/travel/gps.htm

http://en.wikipedia.org/wiki/GSM

http://burnsidetelecom.com/whitepapers/gsm.pdf

http://www.itu.int/osg/spu/ni/3G/casestudies/GSM-FINAL.pdf

REFERENCES

1. ARM-systemonchip-architecture by Steve furber.

2. ARM-user manual UM10114.

3. ARM System Developers Guide by Andrew N.SLOSS

4. "Power Electronics” by M D Singh and K B Khanchandan

5. "Linear Integrated Circuits” by D Roy Choudary & Shail Jain

6. "Electrical Machines” by S K Bhattacharya

7. "Electrical Machines II” by B L Thereja

8. www.8051freeprojectsinfo.com