AndeShape TM OverviewOverview

1

AndeShapeTM OverviewAndeShapeAndeShapeTMTM OverviewOverview

2

2

Internal Bus StructureInternal Bus Structure

DVB

NCOREINCTRL

N1213

� AHB bus

� Masters

• N1213

• MAC

• LCD controller

• DMA controller

• APB Bridge

� Slaves

• All device on AHB are slave except N1213

� APB bus

� SRAM/SDRAM are sharing the IO pin on address and data

� Side Band

3

3

External interfaceExternal interface

� External AHB

� EBI for SRAM/SDRAM address and DATA

� SRAM, SDRAM control signals

� MII for Ethernet

� UTMI for USB

� LCD panel interface for STN, TFT

� CF, SD for memory cards

� I2C, SSPs/ AC97, UARTs

� GPIO

� AICE interface

4

4

PMUPMU

� Reset� Power on reset (everything)

� HW reset (everything except RTC)

� Watch dog reset (everything except RTC and/or PMU)� Sleep mode reset (everything except RTC and PMU)

� Clock control

� Normal mode� Frequency Scaling mode

� change CPU clock

� FCS mode � change PLL frequency

� Sleep mode � remove power from the core,

� PMU monitor the wake-up event

5

5

Boot sequence: power onBoot sequence: power on

� Jumper set PLL clock speed

� Jumper set boot device bus width setup

� Turn on power

� Push button on GPIO0

� Software read PMU status reg to check reset

type SMR, WDT, HWR

6

6

Boot sequence: HW reset Boot sequence: HW reset

� Push reset button

� the sequence is similar to POR

�No POR

�No power enable

�No power ok

7

7

Boot sequence: WDT resetBoot sequence: WDT reset

� WDT reset condition

�WDT is enable

�Without write magic key 0x5AB9 to WdRestart

reg for a period of time

� WDT reset will do:

�asserts to output pin X_reset_b, and X_hreset_b

�Reset everything except RTC and partial PMU

�Reset partial PMU depend on WDTCLR

8

8

Sleep modeSleep mode

� Sleep mode is triggered by software, or external signals (X_powerlow_b, GPIO) trigger interrupt to do sleep mode program

� Sleep mode will do

� SDRAMC let memory @ self-refresh mode

� Reset everything except PMU and RTC

� Assert X_reset_b, and X_hreset_b

� De-assert X_poweren

� Wake-up

� Wake-up on pre-program event

� Assert X_poweren

� After clocks stable, de-assert X_reset_b and X_hreset_b

9

9

Address MapAddress Map

AHB_SLAVE#AHB_SLAVE#AHB_SLAVE#AHB_SLAVE# prefixprefixprefixprefix start addressstart addressstart addressstart address end addressend addressend addressend address slave applicationslave applicationslave applicationslave application sizesizesizesize unitunitunitunit

* AHB_SLV4_BASE 16'h0000 32'h0000_0000 32'h0FFF_FFFF Static memory base 256 MB

* AHB_SLV6_BASE 16'h1000 32'h1000_0000 32'h8FFF_FFFF SDRAMC base 2048 MB

NULL space 16'h9000 32'h9000_0000 32'h900F_FFFF 1 MB

* AHB_SLV0_BASE 16'h9010 32'h9010_0000 32'h901F_FFFF AHB Controller(Arbiter/Decoder) 1 MB

* AHB_SLV3_BASE 16'h9020 32'h9020_0000 32'h902F_FFFF Static memory registers 1 MB

* AHB_SLV5_BASE 16'h9030 32'h9030_0000 32'h903F_FFFF SDRAMC registers 1 MB

* AHB_SLV7_BASE 16'h9040 32'h9040_0000 32'h904F_FFFF DMAC registers 1 MB

* AHB_SLV1_BASE 16'h9050 32'h9050_0000 32'h905F_FFFF AHB-to-APB Bridge Register. 1 MB

* AHB_SLV9_BASE 16'h9060 32'h9060_0000 32'h906F_FFFF LCDC 1 MB

* AHB_SLV10_BASE 16'h9070 32'h9070_0000 32'h907F_FFFF DSP 1 MB

* AHB_SLV11_BASE 16'h9080 32'h9080_0000 32'h908F_FFFF Bluetooth 1 MB

* AHB_SLV12_BASE 16'h9090 32'h9090_0000 32'h909F_FFFF MAC 1 MB

* AHB_SLV13_BASE 16'h90A0 32'h90A0_0000 32'h90AF_FFFF USB Host 1 MB

* AHB_SLV14_BASE 16'h90B0 32'h90B0_0000 32'h90BF_FFFF USB Client 1 MB

* AHB_SLV15_BASE 16'h90C0 32'h90C0_0000 32'h90CF_FFFF AHB-to-PCI Bridge Register 1 MB

* AHB_SLV16_BASE 16'h90D0 32'h90D0_0000 32'h90DF_FFFF AHB-to-AHB Register 1 MB

* AHB_SLV17_BASE 16'h90E0 32'h90E0_0000 32'h90EF_FFFF Ext AHB-to-APB Register 1 MB

* AHB_SLV18_BASE 16'h90F0 32'h90F0_0000 32'h90FF_FFFF Ext AHB slave1(LCD) 1 MB

* AHB_SLV8_BASE 16'h9100 32'h9100_0000 32'h917F_FFFF DMAC perpherials 8 MB

NULL space 32'h9180_0000 32'h91FF_FFFF 8 MB

* AHB_SLV19_BASE 16'h9200 32'h9200_0000 32'h920F_FFFF Ext AHB slave2 1 MB

NULL space 32'h9210_0000 32'h97FF_FFFF 95 MB

* AHB_SLV2_BASE 16'h9800 32'h9800_0000 32'h9FFF_FFFF APB device 128 MB

* AHB_SLV21_BASE 16'hA000 32'hA000_0000 32'hAFFF_FFFF Ext PCI Devices 256 MB

* AHB_SLV22_BASE 16'hB000 32'hB000_0000 32'hB7FF_FFFF Ext APB Devices 128 MB

NULL space 32'hB8000_0000 32'hFFFF_FFFF 1152 MB

TOTALTOTALTOTALTOTAL 4096

USEDUSEDUSEDUSED 2836

AVAILABLEAVAILABLEAVAILABLEAVAILABLE 1260

10

10

APB device Address MapAPB device Address Map

APB_SLAVE#APB_SLAVE#APB_SLAVE#APB_SLAVE# prefixprefixprefixprefix start addressstart addressstart addressstart address end addressend addressend addressend address slave applicationslave applicationslave applicationslave application sizesizesizesize unitunitunitunit

APB_SLAVE_0 14'h1800 32'h9800_0000 32'h980F_FFFF reserved 1 MB

APB_SLAVE_16 14'h1810 32'h9810_0000 32'h981F_FFFF PMU 1 MB

APB_SLAVE_3 14'h1820 32'h9820_0000 32'h982F_FFFF UART1 1 MB


APB_SLAVE_17 14'h1840 32'h9840_0000 32'h984F_FFFF TIMER 1 MB

APB_SLAVE_18 14'h1850 32'h9850_0000 32'h985F_FFFF WDT 1 MB

APB_SLAVE_19 14'h1860 32'h9860_0000 32'h986F_FFFF RTC 1 MB

APB_SLAVE_20 14'h1870 32'h9870_0000 32'h987F_FFFF GPIO 1 MB

APB_SLAVE_21 14'h1880 32'h9880_0000 32'h988F_FFFF INTC 1 MB


APB_SLAVE_22 14'h18A0 32'h98A0_0000 32'h98AF_FFFF I2C 1 MB

APB_SLAVE_2 14'h18B0 32'h98B0_0000 32'h98BF_FFFF SSP1 1 MB

APB_SLAVE_10 14'h18C0 32'h98C0_0000 32'h98CF_FFFF USB Client 1 MB

APB_SLAVE_1 14'h18D0 32'h98D0_0000 32'h98DF_FFFF CFC 1 MB

APB_SLAVE_5 14'h18E0 32'h98E0_0000 32'h98EF_FFFF SD 1 MB

APB_SLAVE_12 14'h18F0 32'h98F0_0000 32'h98FF_FFFF SMMC 1 MB

APB_SLAVE_9 14'h1900 32'h9900_0000 32'h990F_FFFF MS 1 MB

APB_SLAVE_23 14'h1910 32'h9910_0000 32'h991F_FFFF PWM 1 MB

APB_SLAVE_24 14'h1920 32'h9920_0000 32'h992F_FFFF 1 MB

APB_SLAVE_25 14'h1930 32'h9930_0000 32'h993F_FFFF KBC 1 MB

APB_SLAVE_6 14'h1940 32'h9940_0000 32'h994F_FFFF SSP2 1 MB

APB_SLAVE_7 14'h1950 32'h9950_0000 32'h995F_FFFF SSP3 1 MB


APB_SLAVE_26 14'h1970 32'h9970_0000 32'h997F_FFFF MOUSE 1 MB

APB_SLAVE_13

APB_SLAVE_14

APB_SLAVE_15

APB_SLAVE_27

APB_SLAVE_28

11

11

Device OverviewDevice Overview

� N1213

� PMU

� AHB controller

� APB bridge

� SRAM/SDRAM

� LCD

� MAC

� USB

� UART

� SD

� CF

� SSP/AC97

� I2C

� RTC/Timer/Watch Dog

� PWM

12

12

AHB controllerAHB controller

� Up to 15 AHB masters

� Up to 31 AHB slaves

� 2 level round robin arbitration

� Decode space 1M, 2M, 4M, 8M, ….1G, and 2G

13

13

APB bridgeAPB bridge

� Up to 32 APB slaves

� 4 DMA channels

� 16 sets of DMA handshake signals

� Decode space 1M, 2M, 4M,.., 256M

14

14

LCDLCD

� Panel I/F� 24bit bus TFT panel interface

� Max 1024x768 75MHz

� Swap function for red and blue channel� Input mode

� RGB 16(5:6:5)/24(8:8:8)

� Color palette 8/4/2/1 per pixel� YCbCr422(16 bits per pixel)

� YCbCr420

� OSD� 12x16 font size

� Font variety up to 256� 512 fonts/window

� Data format: Little/big endian, windows CE

15

15

SRAMC/SDRAMCSRAMC/SDRAMC

� SRAM/SDRAM share address and data pins� SRAM

� 8, 16, and 32 bit

� ROM, flash, burst-ROM, async/sync SRAM� Up to 256MB, 4 banks� Little/big endian� Shadow 1st and with the other banks

� SDRAM� Max bank size 512MB, 4 banks� Support 16~512 Mb devices � 3 AHB channels, up to 8 AHB channels� Little/big endian

16

16

MACMAC

� 10/100 Mb/sec MII Ethernet PHY

� Half/Full duplex

� DMA engines for TX/RX

� Programmable AHB burst size

� Wake up on Link status change, Magic packet,

Wake up frame

� Little endian

17

17

USB deviceUSB device

� USB 2.0

� 16 bit UTMI

� Automatic CRC5 CRC16 gen/chk

� Support suspend mode, host resume and device

remote wake-up

� Easy endpoint configuration

18

18

UARTUART

� NS 16C550A compatible

� Up to 11520 Kbps

� 5,6,7, and 8 bit data

� 1, 1.5, 2 stop bit

� Even, odd and not parity check

� Support handshake mode DMA

19

19

SDSD

� SD

�SD v1.0

�SD/MMC bus protocol

�Handshake DMA mode for large data transfer

�Built-in 7/16-bit CRC generation and checker

�Variable clock rate: 0~25 MHz

�Hot insertion/removal

�Write protect for SD card

20

20

CFCF

� Common, attribute memory, and IO access

� DMA and PIO mode

� Programmable 8/16 –bit mode

� Support power and reset control function

21

21

SSP/AC97SSP/AC97

� SSP, SPI, microwire, IIS, and AC-link protocol

� 4-32 bit serial data

� Internal or external serial bit clock

� Programmable LSB/MSB first

� Handshake DMA

22

22

I2CI2C

� Support standard and fast mode

� Glitch suppression

� 7-bit, 10-bit and general call address modes

� Programmable slave address

� Support master-tx, master-rx, salve-tx, slave-rx

� Support multi-master mode

23

23

RTC/Timer/Watch DogRTC/Timer/Watch Dog

� Clock source could be PCLK or 32.768 Osc.

� RTC: per-sec, per-minute, per-hour, and per-day

int

� Timer: 3 independent 32-bit counter, each timer

has 2 match registers

� WD 32-bit down counter

24

24

PWMPWM

� 2 pulse width modulation channels

� 6-bit clock divider

� 10-bit period control

� 10-bit duty cycle register

25

ADP_XC5 GuidelinesADP_XC5 GuidelinesADP_XC5 Guidelines

26

26

ADP-XC5FF676 Main Board OverviewADP-XC5FF676 Main Board Overview

RJ45

VIRTEX

LED

GPIO Push Buttons

UARTs

Audio Phone Jack

DC-IN Jack

SDRAM

Reset Button

Flash

Oscillator

SD/MMC

Nor Flash

Power Switch

AHB Connector

MII Connector

LCM

ConnectorEBI/X-BUS

A-ICE Connector

Power On Button

27

27

ADP-XC5 System Block DiagramADP-XC5 System Block Diagram

28

28

On Board DeviceOn Board Device

� Xilinx XC5VLX110-1FF676 FPGA

� 144-pin SO-DIMM for SDRAM

� 32MB on-board NOR flash

� 10/100 Ethernet PHY

� 2 DB9 UART ports

� X-Bus expansion

� AHB bus connector

� SD card slot

� IDE connector

� LCD I/F

� AC97 Audio Codec

29

29

ADP-XC5FF676 DevicesADP-XC5FF676 Devices

� Devices on AHB� SDRAM controller

(128MB)� LCD controller

� DMA controller� MAC controller� USB 2.0 device

controller

� SRAM controller(512KB)

� Flash controller (32MB)� AHB Bus controller

� Devices on APB� AHB-APB bridge� PMU

� I2C� GPIO� Interrupt controller

� Watch dog timer� Timer� RTC� UART

� SSP� I2S/AC97� SD/MMC

30

30

Platform IP Ready in ADP-XC5Platform IP Ready in ADP-XC5

N903N903Bus Controller

Bus Controller MAC

10/100

MAC

10/100 USB2.0USB2.0

LCD

Controller

LCD

ControllerSDRAM

Controller

SDRAM

ControllerDMA

Controller

DMA Controller

SRAM

Controller

SRAM

Controller

AHB to APBBridge

AHB to APBBridge

PWMPWM I2CI2C GPIOGPIO INTCINTC WDTWDT TimerTimer RTCRTC

IrDAIrDA ST

UART

ST

UARTBT

UART

BTUART

FFUART

FFUART SSPSSP CFCF I2SI2S SD/

MMC

SD/MMC

PowerManager

Power

Manager

AHB Bus

APB Bus

31

31

ADP-XC5FF676 ProfileADP-XC5FF676 Profile

� CPU frequency is 80 MHz : N1213; 40MHz : N903

� AHB Clock is 40 MHz

� XILINX Virtex5 LX110

� 64MB SDRAM SO-DIMM

� 32MB NOR Flash

� X-Bus for AIT Chip

� 10/100 Ethernet

� SD card slot

� 2-Digit debug port

� AndesICE port

� 5 push bottons

� 2 UART ports

32

32

Software InstallationSoftware Installation

� Prolific USB-to-Serial Software (If you need)

�PL-2303 Driver� PL-2303.Driver.Installer.exe

� Terminal Software

�TeraTerm� teraterm_utf8_452.exe

� TFTP Server for Windows

�Tftp32� tftpd32.284

33

33

Software SettingSoftware Setting

� Prolific USB-to-Serial Setting

�控制台/系統/硬體/裝置管理員/連接埠 (COM 和 LPT)

� TeraTerm Setting

� Start ‘TeraTerm’ and select ‘Setup / Serial port…‘ from the menu

� Port: COM3

� Baud Rate: 38400

� Data: 8bit

� Parity: none

� Stop: 1 bit

� Flow control: none

34

34


� TeraTerm

35

35


� Hyper Terminal

36

36


� Tftp32

37

37

C P U an d D R A M

co n tro lle r in it ia l iz a t io n

G P IO b u tto n

p u sh e d ?

Y

N

S TA RT

C h eck b o o tin g

m o d e

B o o t c o d e

in i tia l iz a tio n

B u rn in o r

d em o

D efau lt m o d e?

E N D

N

Y

B o o t O S im ag e o r

d ia g n o s is/se tu p

D iag n o sis /se tu p ?

Y

N

AndeShape eBIOS bootingAndeShape eBIOS booting

38

38

Boot procedures Boot procedures

� Plug in DC power to main board

� Turn power switch to ‘ON’

� Press push-button “SW4”

39

39

Diagnostic Main MenuDiagnostic Main Menu

------------------------------------------------------------------------------

Andes Development Platform Diagnosis Menu, Built@Aug 25 2008 (release: 1.1)

CPU: N10 Platform: EVB-AG101 Cache: no cache CPU: 40MHz HCLK: 40MHz

------------------------------------------------------------------------------

( 1) SDRAM Test ( 2) Timer Test ( 3) DMA Test

( 5) UART Loopback Test ( 6) UART DMA Test ( 9) Watchdog Test

(10) Watchdog Reset Test(11) MAC Loopback Test (12) Flash Test

(13) SODIMM Sizing (14) SDRAM(bnk1,2) (17) AC97 Test

(18) AC97 DMA Test (21) LCD Test (23) Query RTC

(24) RTC Alarm Test (25) GPIO Test (55) CLICLICLICLI

(67) Set Console's UART (75) Burnin Test (93) Exec Img on LM(I/D)

(94) Dhrystone Test (95) Boot Selection (97) CopyImageFromCardCopyImageFromCardCopyImageFromCardCopyImageFromCard

(99) Setup

Command>>

40

HW Development

SolutionHW Development HW Development

SolutionSolution

41

41

AHB Extension Bus – Two Leopards SolutionAHB Extension Bus – Two Leopards Solution

SOC platformwith N903

ADP-XC5Development Board

ADP-XC5Development Board

User Define ModuleAHB Extension Bus

. SW development

. AICE debugDownload your

FPGA design

42

42

AHB Extension Bus – Quick SOC IntegrationAHB Extension Bus – Quick SOC Integration

UserDefineCircuit

AHBExtension

Header

N903

DRAM

DMA

LCD

MAC

Uart / SPI

AHB Bus

43

43

AHB Basic ProtocolAHB Basic Protocol

44

44

AHB Extension Bus HeaderAHB Extension Bus Header

45

45

Bidirectional Bus ControlBidirectional Bus Control

� Address Phase�Master issue command

� haddr

� hwrite

� htrans

� hsize

� hburst

� Data Phase�Master/Slave read and write data

� hdata

�Slave response

� Hready

� hresp

46

46

Reserved External DevicesReserved External Devices

�Ext. AHB Master�Master No. 5

�X_hm5_hbusreq

�X_hm5_hgrant

�Master No. 6 �X_hm6_hbusreq

�X_hm6_hgrant

47

47

Reserved External DeviceReserved External Device

�Ext. AHB Slave�Slave No. 13,15,17,18,19,21,22

�X_hs13_hsel, X_hs15_hsel, X_hs17_hsel,

X_hs18_hsel, X_hs19_hsel, X_hs21_hsel,

X_hs22_hsel

�Memory Size : 1MB, 1MB, 1MB,

1MB, 1MB, 256MB,

128MB,

�Address Map : 0x90A0_0000, 0x90C0_0000, 0x90E0_0000,

0x90F0_0000, 0x9200_0000, 0xA000_0000,

0xB000_0000

AndeShape TM OverviewOverview

Documents