Aec manual for III SEM ECE Students VTU

Different Resistor Types: Carbon film resistors:

The size of the resistor decides its power rating (i.e., the maximum power it can dissipate without burning). Power rating from the top of the graph: 1/8 W 1/4 W 1/2 W

Metal film resistors: Used when a higher tolerance (more accurate value) is needed.

Power rating from the top of the graph: 1/8 W (tolerance ±1%) 1/4 W (tolerance ±1%) 1 W (tolerance ±5%) 2 W (tolerance ±5%)

Reading resistor values from the colored bands:

Single-In-Line (SIL) Resistor network:

Variable Resistors:

Wirewound resistors:

Ceramic (or cement) resistor:

Thermistor (thermally sensitive resistor ):

SMD resistors (Surface-Mount Device):

Different Capacitor Types: Ceramic Capacitors: Limited to quite small values, but have high voltage ratings. They range from 1pF to 0.47µF and are not polarized.

Reading Ceramic Capacitor values:

For the

num ber:

Mult iply

by: LETTER

TOLERANCE

1 0 pF or LESS

TOLERANCE

OVER 1 0 pF

0 1 B + / - 0.1pF

1 10 C + / -0.25pF

2 100 D + / - 0.5pF

3 1000 F + / - 1.0pF + / - 1%

4 10,000 G + / - 2.0pF + / - 2%

5 100,000 H + / - 3%

J + / - 5%

8 0.01 K + / - 10%

9 0.1 M + / - 20%

Example: 102 means 10 (and two zeroes) 00 or 1,000 pF or .001uF. Electrolytic Capacitors (Electrochemical type capacitors): Used for all values above 0.1µF. Electrolytics have lower accuracy and temperature stability than most other types and are almost always polarised. It's usually best to only use an electrolytic when no other type can be used, or for all values over 100µF.

From the left to right: 1µF (50V) 47µF (16V) 100µF (25V) 220µF (25V) 1000µF (50V)

Tantalum Capacitors: Tantalum capacitors pack a large capacity into a relatively small and tough package compared to electrolytics, but have much smaller voltage ratings. They are often polarized and range from 0.1µF to 100µF.

From the left to right: 0.33 µF (35V) 0.47 µF (35V) 10 µF (35V)

Polyester Film Capacitors (Green Caps): Ranging from 0.01µF to 5µF. They are similar to ceramics with some larger values and a slightly larger construction. They are not polarized.

Metallized Polyester Film Capacitors:

SMD Capacitors:

Variable Capacitors:

Different Inductor Types: Inductors:

Reading Inductor values from color codes:

High Frequency Coils (ferrite core):

The Toroidal Coil:

Other interesting components:

Diodes:

LED (Light Emitting Diodes):

Transistors:

ICs (Integrated Circuits):

Pin Numbers:

Multimeters (Analog and Digital):

K. S School of Engineering and Management

Department of Electronics and Communication Engineering

A LAB MANUAL ON

ANALOG ELECTRONICS

Subject Code: 10ESL37

(As per VTU Syllabus)

PREPARED BY

Staff members :

Gopalakrishna Murthy C R

Sanjay Naik

Vinay R

AEC LAB MANUAL

Dept. of ECE, KSSEM Page 1

CONTENTS

EXPT.

NO. NAME OF THE EXPERIMENT

PAGE

NO.

01 Testing of Half wave, full wave and bridge rectifier circuits with and without Capacitor filter.

01

02 Testing of Clamping circuits for Positive and Negative clamping

10

03 Testing of Diode Clipping circuits (Single/Double ended)

for peak clipping, peak detection. 16

04 RC coupled amplifier using BJT and FET 23

05 Testing for the performance of BJT- Hartley oscillator /

Colpitt’s oscillator for RF range fo > 100KHz. 31

06 Testing for the performance of BJT-Crystal oscillator for fo > 100KHz.

38

07 Wiring and testing for the performance of BJT-RC phase shift oscillator for fo < 10Khz.

41

08 Wiring of two stage BJT Voltage series feedback amplifier

45

09 Verification of Thevenin’s theorem and maximum power transfer theorem for DC circuits.

51

10 Characteristics of Series and parallel resonance circuits. 55

11 Wiring of BJT Darlington emitter follower with and without

bootstrapping 59

12 Testing of a transformer less Class-B push pull power amplifier and determination of its conversion efficiency.

63

13 Bibliography 65

14 Vivo-voce questions 66

AEC LAB MANUAL


Ex.No:01 HALF WAVE, FULL WAVE AND BRIDGE RECTIFIER

a) HALF WAVE RECTIFIER

AIM:

To study Half Wave Rectifier and to calculate ripple factor, efficiency and

regulation with filter and without filter.

COMPONENTS REQUIRED:

Sl. No. Components Details Range/Specification Qty

1. Diodes BY127/IN4007 1 No.

2. Capacitor 0.1µf, 100µf Each 1 No.

3. Power Resistance Board (DRB) - 1 No.

4. Step down Transformer 12 -0-12 1 No.

5. CRO, Multimeter, milli ammeter, Connecting Board, wires and etc.

THEORY:

Rectifier circuits are used to convert AC in DC. Half wave rectifier circuit

diode (rectifying element) conducts only during positive half cycle of input ac

supply. The negative half cycles of ac supply are eliminated from the output. The dc

output waveform is expected to be a straight line but the half wave rectifier gives

output in the form of positive sinusoidal pulses. Thus the output is called pulsating

dc.

In Full wave rectifier both positive and negative half cycles of AC inputs are

converted in to pulsating DC output. Capacitor is used as a filtering element to

remove ac components from output and to convert pulsating DC in to Constant DC .

CIRCUIT DIAGRAM:

a) HALF WAVE RECTIFIER WITHOUT FILTER CAPACITOR

C2

0.1µF BY127

A K

RL

AC (230V/50HZ)

12V

12V

0

Step down Transformer

A

Ammeter(0-250mA)

+ -

VODC VOAC

AEC LAB MANUAL


Note: connect Voltmeter/Multimeter across load Resistor to measure VODC and CRO

terminals to observe the output wave forms.

b) HALF WAVE RECTIFIER WITH FILTER CAPACITOR

DESIGN:

VVrmsIN 12

VVV INrmsINpeak 97.162

V4.5/VV mDCO

Given V5V DCO

mA100I DCO

50I/VR DCODCOL

Ripple = r = Vo rms / VO DC = 1.21

Design for the filter capacitor

Ripple = 1/ (23 f C RL)

Given r = 0.25

C = 1/(23 f r RL)

RL = 50

f = 50Hz

=95.43F 100F

Efficiency = output Power (PDC) /Input Power (PAC)

(I2DC * RL) / [(Irms)2 * (RL + RF + Rs)]

≈ 2 (Vodc)2/(Vi rms)2 ≈ 40.6%

C2

0.1µF BY127

A K

RL

AC (230V/50HZ)

12V

12V

0


A

Ammeter(0-250mA)

+ -

100µF

+

-

C1

VODC VOAC

AEC LAB MANUAL


Where Irms = Im/2 & Im = Vm/( RL + RF + Rs)

Regulation % Regulation = 100FL

FLNL

V

VV

Where VNL = Vo(dc) & VFL = Vo(dc) - Idc (Rf + Rs) or VFL = Idc * RL

Rf = Diode forward Resistance & Rs = Transformer Secondary Resistance.

PROCEDURE:

1. Connections are made as shown in the circuit diagram

2. Set say 100Ω in DRB and Switch on the AC power supply 3. Observe the wave form on CRO across the load resistor

4. Note down RL, IDC, VODC, VINrms, and VOrms in the tabular column for different load resistances. Don’t set zero resistance in DRB at any time.

5. Calculate the ripple and efficiency and Regulation for each load resistance.

6. With C filter calculate regulation and Compare the ripple factor rtheoretical with rpractical for the design values of RL and Capacitor.

TABULAR COLUMN:

Sl.

No. RL IDC

VO

(DC)

VIN

(AC)

VO

(AC) Ripple Efficiency Regulation

Result:

(Without filter) Ripple = rtheoretical = 1.21 rpractical =___

(With Filter) rtheoretical = 1/ (23 f C RL) = 0.25 for C= 100F, r practical =___

Ripple factor = rpractical = Vorms/ Vodc

Efficiency = theoritical = 40.6% practical ≈ [2 (Vodc)2]/(Vi rms)2

Regulation = % Regulation = 100FL

FLNL

V

VV

Where VNL = no load voltage = voltage across output by removing load resistance.

VFL = Full load voltage = Voltage across output with load resistance.

AEC LAB MANUAL


WAVEFORMS:

20

0 t

- 20

Vo (Without Filter)

0 t

Vo (with filter)

0 t

FULL WAVE RECTIFIER

AIM:

To study the full wave rectifier and to calculate ripple factor and efficiency

and Regulation with filter and without filter.


Sl. No. Components Details Specification Qty

1. Diodes BY127/IN4007 2 Nos.


3. Power Resistance Board (DRB) 1 No.

4. Step down Transformer 12 V 1 No.

5. CRO, Multimeter, Milli ammeter, Connecting Board and etc.

THEORY:

The center tapped full wave rectifier circuit is similar to a half wave rectifier

circuit, using two diodes and a center tapped transformer. Both the input half cycles

are converted into unidirectional pulsating DC.

VC

VIN

VO

AEC LAB MANUAL


CIRCUIT DIAGRAM:

FULL WAVE RECTIFIER WITHOUT FILTER CAPACITOR

FULL WAVE RECTIFIER WITH FILTER CAPACITOR

DESIGN:

Vin rms = 12V


VO DC = 2Vm/ = 10.8V

Given VO DC = 10V

IO DC = 100mA

RL = VO DC / IO DC = 100



Ripple = 1/ (43 f C RL)

Given r =0 .06

C = 1/(43 f r RL)

Step down

C2

0.1UF BY127

A K

RL

AC (230V/50HZ)

12V

12V

0

Transformer

A

Ammeter (0-250mA)

+ -

VO(DC)

BY127

A K

VO (AC)

(230V/50HZ)

C2

0.1UF BY127

A K

RL

AC

12V

12V

0


A

Ammeter (0-250mA)

+ -

470UF

+

-

C1

VO(DC)

BY127

A K

VO(AC)

AEC LAB MANUAL


RL = 100

f = 50Hz

C = 470UF

Efficiency = PDC /PAC (I2DC * RL) / [(Irms)2 * (RL + RF +Rs)]

Where Irms = IM/√2 and IM = VM /(RL + RF +Rs)

Efficiency = ≈ (Vodc)2/(Vi rms)2


FLNL

V

VV

Note: repeat the same procedure of HWR for calculating Regulation .

PROCEDURE:


2. Switch on the AC power supply

3. Observe the wave form on CRO across the load resistor and measure the o/p amplitude and frequency.

4. Note down RL, IDC, VODC , Vinac, Voac in the tabular column for different load

resistances.

5. Calculate the ripple and efficiency and regulation for each load resistance.

6. Repeat the above procedure with filter capacitor.

TABULAR COLUMN:

Sl.

No. RL IDC VO (DC)

VIN

(AC) VO (AC) Ripple Efficiency Regulation

(Without filter) Ripple = rtheoretical = 0.48 rpractical =___

(With Filter) rtheoretical = 1/ (43 f C RL) = 0.06 for C= 470F, r practical =___

Ripple factor = rpractical = Vorms/ Vodc

Efficiency = theoritical = 81.2% practical ≈ (Vodc)2/(Vi rms)2

Regulation = % Regulation = 100FL

FLNL

V

VV

Where VNL = no load voltage = voltage across output by removing load resistance.

VFL = Full load voltage = Voltage across output with load resistance.

AEC LAB MANUAL


WAVEFORMS:

0 t

-

Vo (Without Filter)

0

t

Vo (with filter)

0 t

VC

VIN

VO

AEC LAB MANUAL


BRIDGE RECTIFIER

AIM:

To study the bridge rectifier and to calculate ripple factor and efficiency and

regulation with filter and without filter.


Sl. No. Components Details Specification Qty

1. Diodes BY127/IN4007 4 Nos.


3. Power Resistance Board (DRB) 1 No.

4. Step down Transformer 12 V 1 No.

5. CRO, Multimeter, Milliammeter, Connecting Board

THEORY:

The bridge rectifier circuit is essentially a full wave rectifier circuit, using four

diodes, forming the four arms of an electrical bridge. To one diagonal of the bridge,

the ac voltage is applied through a transformer and the rectified dc voltage is taken

from the other diagonal of the bridge. The main advantage of this circuit is that it

does not require a center tap on the secondary winding of the transformer; ac

voltage can be directly applied to the bridge.

The bridge rectifier circuit is mainly used as a power rectifier circuit for

converting ac power to dc power, and a rectifying system in rectifier type ac

meters, such as ac voltmeter in which the ac voltage under measurement is first

converted into dc and measured with conventional meter.

CIRCUIT DIAGRAM:

BRIDGE RECTIFIER WITHOUT FILTER CAPACITOR

RL

- +

BRIDGE

1

4

3

2

C2

0.1UF

AC (230V/50HZ)

12V

12V

0


Vo

A

Ammeter(0-250mA)

+ -

AEC LAB MANUAL


BRIDGE RECTIFIER WITH FILTER CAPACITOR

DESIGN:

Vin rms = 12V


VO DC = 2Vm/ = 10.8V

Given VO DC = 10V and IO DC = 100mA

RL = VO DC / IO DC = 100



Ripple = 1/(43 f C RL)

Given r = .06

C = 1/(43 f r RL)

RL = 100 and f = 50Hz

C = 470UF

Efficiency

= PDC /PAC

= (I2DC * RL) / [(Irms)2 * (RL + RF)] OR = 0.812/(1+2Rf/ RL)

Where Irms = Im/2, & Im = Vm/(2Rf+RL)


FLNL

V

VV

C1

470UF

RL

- +

BRIDGE

1

4

3

2

C2

0.1UF

AC(230V/50HZ)

12V

12V

0

Step downTransformer

Vo

A

Ammeter(0-250mA)

+ -

+ -

AEC LAB MANUAL


PROCEDURE:


2. Switch on the AC power supply

3. Observe the wave form on CRO across the load resistor and measure the o/p amplitude and frequency.

4. Note down RL, IDC, VODC , Vinac, Voac in the tabular column for different load

resistances.

5. Calculate the ripple factor, efficiency and regulation for each load resistance.

6. Repeat the above procedure with filter capacitor.

TABULAR COLUMN:

Sl.

No.

RL IDC VO (DC) VIN

(AC) VO (AC) Ripple Efficiency Regulation

Calculations are same as FWR

WAVEFORMS:

Vin

20

t

0

- 20

Vo

Vo (Without Filter)

0 t

Vo (with filter)

VC

t

Observation and Result:

AEC LAB MANUAL


DIODE CLAMPING CIRCUITS

AIM: Testing of clamping circuits: positive /negative clamping.


Sl.No Component Range Quantity

1 Resistor 100K 1

2 Diode 1N4001 2

3 Capacitor 1µF 1

4 DC variable Power supply (0-30) V 1

5 DSO - 1

6 Function Generator - 1

7 Connecting Wires - 1 set

Theory:

Clamper is a circuit that clamps a signal to a different DC level without changing the shape of

the applied signal. Clamping circuit introduces a DC level into an ac signal. The different types

of clampers are positive, negative and biased clampers. A clamping network must have a

capacitor, a diode and a load resistor. The magnitude R and C must be chosen such that time

constant RC is large enough to ensure that the voltage across the capacitor does not discharge

significantly during the interval when the diode is non conducting. By connecting suitable Dc

voltage in series with the diode, clamping level can be varied.

The clamper with a positive DC shift is called positive clamper (Negative peak clamper) and a

clamper with a negative DC shift is called negative clamper (Positive peak clamper).

Positive Peak Clamper: This pushes down the DC the positive peak of the input signal to level

above or below the reference level depending upon the DC offset voltage.

Negative Peak Clamper: This pushes down the DC the negative peak of the input signal to level

above or below the reference level depending upon the DC offset voltage.

Design:

Assume C, and for the clamping to occur select R such that RC T, where T is the period of the

input signal.

RC T ; Assume T = 2ms, let RC = 50T = 100ms

Let R= 100K C = 1µF

AEC LAB MANUAL


Positive peak clamper (Positive Reference)

Design:

Assume Vin = 10VP-P, Vref = 2V, VK = 0.6V

a. During the positive half of the input signal diode is forward biased D = ON

Applying KVL to the loop

Vin – VC – VK – VR = 0

VC = Vin– VK – VR

VC = 5V – 0.6V – 2V

VC = 2.4V

b. During the negative half of the input signal diode is reverse biased D = OFF


Vin – VC – VO = 0

VO = Vin – VC

When Vin = 0V VO = -2.4V

Vin = 5V VO = 2.4V

Vin = -5V VO = -7.6V

The output varies between +2.4V to -7.6V

-8-7-6-5-4-3-2-1012345678

0 90 180 270 360 450

vi

vo

AEC LAB MANUAL


Positive peak clamper (Negative Reference)

Design:


a. During the positive half of the input signal diode is forward biased D = ON


Vin – VC – VK – VR = 0

VC = Vin– VK + VR

VC = 5V – 0.6V + 2V

VC = 6.4V

b. During the negative half of the input signal diode is reverse biased D = OFF


Vin – VC – VO = 0

VO = Vin – VC

When Vin = 0V VO = -6.4V

Vin = 5V VO = -1.4V

Vin = -5V VO = -11.4V

The output varies between -1.4V to -11.4V

-12-11-10

-9-8-7-6-5-4-3-2-1012345678

0 90 180 270 360 450

vi

vo

AEC LAB MANUAL


Negative Peak Clamper (Negative Reference)

Design:


a. During the negative half of the input signal diode is forward biased D = ON


-Vin + VC + VK + VR = 0

VC = - (-Vin – VK – VR)

VC = - (-5V + 0.6V + 2V)

VC = 2.4V

b. During the positive half of the input signal diode is reverse biased D = OFF


Vin + VC – VO = 0

VO = Vin + VC

When Vin = 0V VO = 2.4V

Vin = 5V VO = 7.4V

Vin = -5V VO = -2.4V

The output varies between -2.4V to 7.6V

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

0 90 180 270 360 450

vi

vo

AEC LAB MANUAL


Negative Peak Clamper (Positive Reference)

Design:


a. During the negative half of the input signal diode is forward biased D = ON


-Vin + VC + VK – VR = 0

VC = - (Vin – VK – VR)

VC = - (-5V + 0.6V – 2V)

VC = 6.4V

b. During the positive half of the input signal diode is reverse biased D = OFF


Vin + VC – VO = 0

VO = Vin + VC

When Vin = 0V VO = 6.4V

Vin = 5V VO = 11.4V

Vin = -5V VO = 1.4V

The output varies between 1.4V to 11.4V

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

7

8

9

10

11

12

0 90 180 270 360 450

vi

vo

AEC LAB MANUAL


Procedure:

1. Connect the circuit as shown in the figure.

2. Switch on the variable DC power supply, keeping voltage knobs at minimum position

and current knobs at maximum position and set reference voltage value.

3. Apply square wave or sine wave as an input signal at frequency say 1KHz and voltage

10V (p-p)

4. Observe the input and output waveforms on the CRO/DSO.

5. Vary the voltage and observe the clamping level of the output signal and note down the

value of clamping level.

Result:

AEC LAB MANUAL

Dept. of ECE Page 18

DIODE CLIPPING CIRCUITS

AIM:

Testing Of diode clipping (Single and Double Ended) circuits for peak clipping.


Sl.No Component Range Quantity

1 Resistor 10K 1

2 Diode 1N4001 2


4 DSO - 1


6 Connecting Wires - 1 set

Clippers:

Clipping is defined as removing some part of the a.c signal without affecting the other parts of

the a.c signal. This kind of processing is useful in wave shaping, circuit protection and

communications. Clipper circuit are also called limiter circuit, are used to eliminate portions of

that are above or below a specified level. A simple application of a clipper is to limit the voltage

at the input to the electronic circuit so as to prevent the breakdown of the transistor in the circuit.

The circuit can be used to measure the frequency of the signal, so the amplitude is not an

important part of the signal.

Types of clipper circuits:

1. Series Clipper (Single ended and double ended)

2. Parallel Clipper (Single ended and double ended)

Design of R

The Value of R should be chosen as geometric mean of Rf and Rr of diode. Where Rf represents

dynamic forward resistance and Rr represents reverse resistance of the diode.

R = √ Say, Rf = 100Ω, Rr = 1MΩ, then R= 10KΩ.

AEC LAB MANUAL


PARALLEL CLIPPERS (SINGLE ENDED)

PARALEL POSITIVE CLIPPER

Assume

Vi = 10VP-P, R = 10K, Vref = 1.4, VK = 0.6V Calculate VO.

Case 1: Case 1:

When Vi ≥ Vref + VK D = ON When Vi ≥ 1.4V + 0.6V D = ON VO = Vref + VK VO = 1.4V + 0.6V VO = 2V

Case 2: Case 2:

When Vi < Vref + VK D = OFF When Vi < 1.4V + 0.6V D = OFF VO = Vi VO = Vi

TRANSFER CAHARACTERISTICS

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

0 90 180 270 360 450 540 630 720 810

vi

vo

-6

-5

-4

-3

-2

-1

0

1

2

3

-6 -4 -2 0 2 4 6

AEC LAB MANUAL


PARALLEL NEGATIVE CLIPPER

Assume

Vi = 10VP-P, R = 10K, Vref = 1.4, VK = 0.6V Calculate VO.

Case 1: Case 1:

When Vi - [Vref + VK] D = ON When Vi - [1.4V+ 0.6V] D = ON VO = - [Vref + VK] VO = - [1.4V+ 0.6V] VO = - 2V

Case 2: Case 2:

When Vi - [Vref + VK] D = OFF When Vi - [1.4V+ 0.6V] D = OFF VO = Vi VO = Vi

TRANSFER CHARACTERISTICS

-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

0 90 180 270 360 450 540 630 720 810

vi

vo

-3

-2

-1

0

1

2

3

4

5

6

-6 -4 -2 0 2 4 6

AEC LAB MANUAL


SERIES POSITIVE CLIPPERS

Assume

Vi = 10VP-P, R = 10K, Vref = 2V, VK = 0.6V Calculate VO.

Case 1: Case 1:

When Vi [VR - VK] D = ON When Vi [2V-0.6V] D = ON

VO = Vi + VK VO = - 4.3V

Case 2: Case 2:

When Vi > [VR - VK] D = OFF When Vi > [VR - VK] D = OFF VO = Vref VO = 2V


-6.00

-5.00

-4.00

-3.00

-2.00

-1.00

0.00

1.00

2.00

3.00

4.00

5.00

6.00

0 90 180 270 360 450 540 630 720 810

Vi

VO

-5.00

-4.00

-3.00

-2.00

-1.00

0.00

1.00

2.00

3.00

-6.00 -4.00 -2.00 0.00 2.00 4.00 6.00

AEC LAB MANUAL


SERIES NEGATIVE CLIPPER

Assume

Vi = 10VP-P, R = 10K, Vref = 2V, VK = 0.6V Calculate VO.

Case1:

When Vi -[ VR - VK] D = ON VO = Vi - VK

Case 2:

When Vi -[ VR - VK] D = ON VO = VR


-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

0 90 180 270 360 450 540 630 720 810

VI

VO

-3.00

-2.00

-1.00

0.00

1.00

2.00

3.00

4.00

5.00

6.00

-6.00 -4.00 -2.00 0.00 2.00 4.00 6.00

AEC LAB MANUAL


PARALLEL CLIPPING (DOUBLE ENDED)

Assume

Vi = 10VP-P, R = 10K, Vref1 = 1.4V, Vref2 = 1.4V, VK = 0.6V Calculate VO.

Case1: Case 1:

When Vi [VRef1 + VK] When Vi [1.4V + 0.6V]

VO = [VRef1 + VK] VO = 2V

Case 2: Case 2:

When Vi [VRef2 + VK] When Vi [1.4V + 0.6V]

VO = - [VRef2 + VK] VO = - 2V

Case 3: Case 3:

When - [VRef2 + VK] Vi < [Vref1 + VK] When - [1.4V + 0.6V] Vi < [1.4V + 0.6V]

VO = Vi VO = Vi


-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

0 90 180 270 360 450 540 630 720 810

vi

vo

-3

-2

-1

0

1

2

3

-6 -4 -2 0 2 4 6

AEC LAB MANUAL


SERIES CLIPPING (DOUBLE ENDED)

Assume

Vi = 10VP-P, R = 10K, Vref1 = 1.4V, Vref2 = 1.4V, VK = 0.6V Calculate VO.

Case 1: Case 1:

When Vi [VRef1 + VK] D = ON When Vi [2V + 0.6V] D = ON VO = Vi - VK - VR VO = 5V - 0.6V - 1.4V VO = 3V

Case 2: Case 2:

When Vi [VRef1 + VK] D = OFF When Vi [VRef1 + VK] D = OFF VO = Vi - VK - VR VO = -5V + 0.6V + 1.4V

VO = - 3V


-6

-5

-4

-3

-2

-1

0

1

2

3

4

5

6

0 90 180 270 360 450 540 630 720 810

vi

vo

-4

-3

-2

-1

0

1

2

3

4

-6 -4 -2 0 2 4 6

AEC LAB MANUAL


RC COUPLED BJT AMPLIFIER

AIM:

Wiring of RC coupled single stage BJT amplifier and determination of the gain frequency

response, input and output impedance.


Sl.No Components Range Quantity

1 Transistor SL-100 1

2 Resistors 22K,2.2K,4.7K,470Ω 1

3 Capacitors 0.47µF,47µF 0.47 µF =2

47 µF=1

4 Variable power supply (0-30)V 1

5 DSO - 1

6 Function Generaator - 1

7 Connecting wires - 1 set

THEORY:

A common emitter amplifier is defined as an electronic circuit with an ac input voltage applied

across the base and emitter pins of a bipolar junction transistor with the output voltage taken as

the voltage from the collector pin to ground. As the name suggests, the emitter is connected to a

reference ground. RC coupled amplifier is the one which amplifies the given small signal.

Basically it is the multi stage amplifier which usually has two or more stages.

In each stage, there will be there would be a CE amplifier present whose output is given as the

input to the next stage. The function of the input capacitor is to block the base from any DC shift

caused by the input signal. Allowing a DC shift to be felt at the base would continuously change

the Q point of the amplifier, resulting in erratic effects on the amplifier’s output voltage.

The input capacitor must allow all the ac signal components through. The function of the output

capacitor is to block the collector from DC shift that might be caused by the load. Failure to do

so would result in a Q-point shift. The bypass capacitor is used to short out the emitter resistor

during ac operation.

The two values of frequency for which the voltage gain of about 0.707 times the peak voltage

gain are called the low and high frequency roll-off. These correspond to the minimum and

maximum frequencies for the power carried by the signal is at most a factor of two smaller than

the maximum. Hence, the difference between the two frequencies is called the half power

bandwidth.

AEC LAB MANUAL


CIRCUIT DIAGRAM:

Amplifier Design:

Select transistor SL-100 having the following specifications IE = IC = 2mA, β = 100, VCE = 5V

Selection of RE

VCC = 10V; VE = ; VE =

= 1V

VE = IERE; RE = ; RE =

= 0.5K; Select RE = 470Ω;

Selection of RC:

VCE = ; VCE = = 5V

VCE = ICRC + VCE + VE

RC =

RC = 2KΩ; Select RC = 2.2K Ω;

AEC LAB MANUAL


Selection of R1 and R2:

VB = VBE + VE; VB = 1.7V;

VB =

1.7V =

10R2 = 1.7R1 + 1.7 R2; R1 = 4.8R2;

Choose R2 = 4.7KΩ; R1 = 4.8 4.7K;

R1 = 22.56KΩ

Choose R1 = 22KΩ

Selection of bypass capacitor CE:

Let XCE = ; At f = 100Hz, =

CE = 59 F; Choose CE = 47 F

Selection of Coupling Capacitors:

Select CC1 = CC2 = 0.47 F

Procedure:

1. Connections are made as shown in the circuit diagram.

2. The input voltage Vin is adjusted to a convenient value (10mV to 50mV) within the

distortion less limit and value must be kept constant throughout the experiment.

3. Frequency of the input signal is varied from 100Hz to 2MHz in steps and at each step,

corresponding output VO is noted down.

4. All readings are tabulated and graph of voltage gain in dB Vs frequency is drawn on a

Semi-log sheet.

5. 3dB bandwidth is determined from the frequency response curve.

AEC LAB MANUAL


TABULAR COLUMN:

Frequency in Hz VO in Volts Gain in dB= 20log10(VO/Vin)

100Hz

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2MHz

Input Impedance

Procedure:

1. A DRB is connected in series with the input as shown in the figure.

2. In the mid frequency region (with constant gain) with zero resistance (all the knobs of the

DRB in zero position) the output is measured.

3. Now the DRB resistance is increased till the output voltage falls to half of the initial

value.

4. The corresponding DRB value gives the input impedance of the circuit.

AEC LAB MANUAL


Output impedance

Procedure:

1. A DRB is connected in series with the input as shown in the figure.

2. In the mid frequency region (with constant gain) with maximum resistance (all the knobs

of the DRB in maximum position) the output is measured.

3. Now the DRB resistance is decreased till the output voltage falls to half of the initial

value.

4. The corresponding DRB value gives the output impedance of the circuit

RESULT:

Gain AV

Bandwidth

Input impedance Zi

Output impedance ZO

AEC LAB MANUAL


HARTLEY OSCILLATOR

AIM: Testing for the performance of BJT Hartley oscillator for fo =100KHz.




2 Resistors 22K,2.2K,4.7K,1K,470Ω, 1K POT 1


47 µF=1


5 DSO - 1



8 Decade Inductance box - 1

9 Decade Capacitane box - 1

THEORY:

When the collector supply voltage Vcc is switched on, collector current starts rising and charges

the capacitor C. When this capacitor is fully charged, it discharges through coils L1 and L2,

setting up damped harmonic oscillations in the tank circuit. The oscillatory current in the tank

circuit produces an a.c. voltage across L1 which is applied to the base emitter junction of the

transistor and appears in the amplified form in the collector circuit.

Feedback of energy from output (collector emitter circuit) to input (base-emitter circuit is)

accomplished through auto transformer action. The output of the amplifier is applied across the

inductor L1, and the voltage across L2 forms the feedback voltage. The coil L1, is inductively

coupled to coil L2, and the combination acts as an auto-transformer.

This energy supplied to the tank circuit overcomes the losses occurring in it. Consequently the

oscillations are sustained in the circuit. The energy supplied to the tank circuit is in phase with

the generated oscillations. The phase difference between the voltages across L1 and that across

L2 is always 180° because the centre of the two is grounded. A further phase of 180° is

introduced between the input and output voltages by the transistor itself. Thus the total phase

shift becomes 360O

(or zero), thereby making the feedback positive or regenerative which is

essential for oscillations.

AEC LAB MANUAL


CIRCUIT DIAGRAM:

Amplifier design:

VCE = 5V , IC = 2mA, VCC = 2VCE = 10V

VRE = ×VCC =

×10 = 1V

RE = =

= 500Ω. Choose 470 Ω.

RC = = 2K. Choose 2.2KΩ.

Assume hfe = 50

IB = = 0.04mA = 40µA

VR2 = VBE – VBE = 1V + 0.6V = 1.6V & VR1 = VCC - VR2 = 10 – 1.6V = 8.4V

AEC LAB MANUAL


R2 = =

= =

= 4.7KΩ.

R1 =

= =

= = 22KΩ.

Design of Tank Circuit:

Let fo = 100KHz

Choose L1 = 200 µH, L2 = 600 µH

Choose fo = √

Calculate C = ?

C = 330 µF

PROCEDURE:


2. Measure the DC conditions.

3. Vary the 1K potentiometer so as to get an undistorted sine wave at the output.

4. Note down the amplitude and frequency of the output wave and frequency haas to match

with the theoritical frequency.

RESULT:

Frequency = Hz.

Amplitude = V.

AEC LAB MANUAL


COLPITTS OSCILLATOR

AIM: Testing for the performance of BJT Colpitts oscillator for fo =100KHz.




2 Resistors 22K,2.2K,47K,1K, 470Ω,1K, POT 1


47 µF=1


5 DSO - 1



8 Decade Inductance box - 1

9 Decade Capacitance box - 1

THEORY:

The Colpitt’s oscillator is designed for generation of high frequency sinusoidal oscillations (radio

frequencies ranging from 10 KHz to 100MHz). They are widely used in commercial signal

generators up to 100MHz. Colpitt's oscillator is same as Hartley oscillator except for one

difference. Instead of using a tapped inductance, Colpitt's oscillator uses a tapped capacitance.

When the collector supply voltage Vcc is switched on, collector current starts rising and charges

the capacitors C1 and C2. When these capacitors are fully charged, they discharge through coil L

setting up damped harmonic oscillations in the tank circuit. The oscillatory current in the tank

circuit produces an a.c. voltage across C1, C2. The oscillation across C2 is applied to base-

emitter junction of the transistor and appears in the amplified form in the collector circuit and

overcomes the losses occurring in the tank circuit.

The feedback voltage (across the capacitor C2) is 180° out of phase with the output voltage

(across the capacitor C1), as the centre of the two capacitors is grounded. A phase shift of 180° is

produced by the feedback network and a further phase shift of 180° between the output and input

voltage is produced by the CE transistor. Hence, the total phase shift is 360° or 0°, which is

essential for sustained oscillations, as per, the Barkhausen criterion.

AEC LAB MANUAL


CIRCUIT DIAGRAM:

AMPLIFIER DESIGN:


VRE = ×VCC =

×10 = 1V

RE = =

= 500Ω. Choose 470 Ω.


Assume hfe = 50

IB = = 0.04mA = 40µA


AEC LAB MANUAL


R2 = =

= =

= 4.7KΩ.

R1 =

= =

= = 22KΩ.

DESIGN OF TANK CIRCUIT:

Let fo = 100KHz

Choose C1 = C2 = 1000pF

fo = √

Calculate L = ?

L= 5mH

PROCEDURE:






RESULT:

Frequency = Hz.

Amplitude = V.

AEC LAB MANUAL

Depat. Of ECE, KSSEM Page 36

BJT-CRYSTAL OSCILLATOR

AIM: Testing for the performance of the BJT- crystal oscillator for fo > 500KHz.




2 Crystal 2MHz 1

3 Resistors 22K, 2.7K, 47K, 470Ω, 1K POT 1

4 Capacitors 0.47µF, 47 µF 0.47 µF =2

47 µF=1



7 DSO - 1

8 Connecting wires - 1set

THEORY:

A crystal oscillator is basically a tuned oscillator using a pizeoelectric crystal asa resonant

circuit. The crystal has a greatest stability in holding consant charge at whatever frequency the

crystal is originally cut to operate. Crystal oscillators are used whenever great stability is

required, such as communication, transmitters and recievers.

Characteristics of a Quartz crystal

A quartz crystal exihibits the property that whenever mechanical stress is applied across one set

of its faces, a difference os potential develops acoss the opposite faces. This property of a crystal

is called pizeoelectric effect. Similarly, a voltage applied across one set of faces of the crystal

causes mechanical distortion in the cryatal shape. When alternating voltage is applied to a

crystal, mechanical vibrations are set up- these vibrations having a natural resonating frequency

dependent on the crystal.

The inductor L and the cappacitor C represents electrical equivalents of crystal mass and

compliance respectively, whereas resistance R is an electrical equivalent of the crystal structures

internal friction. The shunt capacitance CM represents the capacitance due to mechanical

mounting of the crystal. Because the crystal loses, represented by R, are small, the equivalent

cryatal Q factor is high typically 20,000. Values of Q up to almost 106 can be achieved by using

crystals. The crystal has two resonant frequencies. One resonant condition occurs when the

reactances of the series RLC leg are equal.

AEC LAB MANUAL


CIRCUIT DIAGRAM:

Amplifier design:


VRE = ×VCC =

×10 = 1V

RE = =

= 500Ω. Choose 470 Ω.


Assume hfe = 50

IB = = 0.04mA = 40µA


AEC LAB MANUAL


R2 = =

= =

= 4.7KΩ.

R1 =

= =

= = 22KΩ.

PROCEDURE:






RESULT:

Frequency = Hz.

Amplitude = V.

AEC LAB MANUAL


RC PHASE SHIFT OSCILLATOR

AIM: To generate the sinusoidal waveform of RF range using RC phase shift oscillator.




2 Resistors 22K,2.2K,47K,1K,1K and 10K POT 2.2K=4,

Others=1

3 Capacitors 0.47µF, 0.02µF 0.47 µF =2

47 µF=1


5 DSO - 1



.

THEORY:

The RC Oscillator which is also called a Phase Shift Oscillator produces a sine wave output

signal using regenerative feedback from the resistor-capacitor combination. This regenerative

feedback from the RC network is due to the ability of the capacitor to store an electric charge,

(similar to the LC tank circuit). This resistor-capacitor feedback network can be connected as

shown in the figure to produce a leading phase shift (phase advance network) or interchanged to

produce a lagging phase shift (phase retard network) the outcome is still the same as the sine

wave oscillations only occur at the frequency at which the overall phase-shift is 360o. By varying

one or more of the resistors or capacitors in the phase-shift network, the frequency can be varied

and generally this is done using a 3-ganged variable capacitor.

Since the resistor-capacitor combination in the RC Oscillator circuit also acts as an attenuator

producing an attenuation of -1/29th (Vo/Vi = β) per stage, the gain of the amplifier must be

sufficient to overcome the losses and in our three mesh network above the amplifier gain must be

greater than 29. The loading effect of the amplifier on the feedback network has an effect on the

frequency of oscillations and can cause the oscillator frequency to be up to 25% higher than

calculated. Then the feedback network should be driven from a high impedance output source

and fed into a low impedance load such as a common emitter transistor amplifier but better still

is to use an operational amplifier as it satisfies these conditions perfectly.

AEC LAB MANUAL


CIRCUIT DIAGRAM

AMPLIFIER DESIGN:


VRE = ×VCC =

×10 = 1V

RE = =

= 500Ω. Choose 470 Ω.


Assume hfe = 50

IB = = 0.04mA = 40µA

AEC LAB MANUAL



R2 = =

= =

= 4.7KΩ.

R1 =

= =

= = 22KΩ.

FEEDBACK CIRCUIT DESIGN:

If the frequency for the RC phase shift oscillator is say, 1 KHz, Then,

fo = √ = 1KHz

Where k , Choose k=1, so RC = R = 2.2KΩ. Substituting these values in the frequency

equation, we get C = 0.022µF.

The current gain of the transistor, β 4K + 23 +

PROCEDURE:



3. Observe the sinusoidal waveform output and calculate the frequency using CRO/DSO.

4. Measure the phase difference between the output and at points A,B,C.

5. To observe the phase difference between the signals connect the output of the amplifier to

channel1 of the CRO/DSO and connect A or B or C to channel2 of the CRO/DSO.

6. Go to X-Y mode to observe the Lissajous figure, and also to measure the phase difference

between the output and A or B or C.

RESULT:

AEC LAB MANUAL


VOLTAGE SERIES FEEDBACK AMPLIFIER

AIM:

To conduct an experiment on two-stage BJT small signal amplifier (with and without feedback).

COMPONENTS AND EQUIPMENTS REQUIRED:



2 Resistors 22K,10K,2.2K,4.7K,470Ω,390 Ω,100 Ω 2


47 µF=2


5 DSO - 1



THEORY:

Feedback plays an important role in electronic circuits and the basic parameters such as input

impedance, output impedance, voltage or current gain and band width, may be altered

considerably in a desired direction by the use of feedback for a given amplifier. In any of the

feedback amplifiers, a part of the output signal is taken from the output of the amplifier and is

combined with the normal input signal and thereby the feedback is achieved. If the signal

feedback is aid the input signal, then it is said to positive feedback and if it is opposing, it is said

to be the negative feedback. Positive feedback is used in oscillators and negative feedback is

used wherever the gain has to be stabilized, bandwidth is to be increased and distortion has to be

reduced. There are four types of negative feedback amplifiers depending the input signal and

output signal that is feedback.

1. Voltage- series feedback

2. Voltage-shunt feedback

3. Current-series feedback

4. Current-shunt feedback

Voltage-Series Feedback Amplifier: In

this case, the part of the output voltage for the amplifier is feedback, which is in series opposition

with input. This reduces the gain, but stabilizes it. Also the input impedance and bandwidth

increases and output impedance decreases.

AEC LAB MANUAL


CIRCUIT DIAGRAM

Fig: Voltage Series amplifier without feedback

Fig: Voltage Series amplifier with feedback

AEC LAB MANUAL


Amplifier design:

It remains same as given for RC-coupled amplifier.

Here β = =

= , called as feedback factor.

Select RE = 390Ω; RE11 = 100Ω; RF = 10KΩ

PROCUDURE:

1. Connect the circuit as shown in the figure. Set the signal generator amplitude to 10mV

peak to peak sine waveform and observe the input and output signals of the circuit

simultaneously on the CRO/DSO.

2. By varying the frequency of the input from 100Hz to 2MHz range correspondingly note

down the output voltage.

3. Plot the gain in dB against frequency in a semi log graph sheet.

4. From the graph determine the bandwidth.

5. Repeat the same procedure for with feedback case also.

6. Calculate the input and output impedance in both the cases.

TABULAR COLUMN

F in Hz VO(P-P) in V AV = Voltage gain in

dB = 10log10AV

AEC LAB MANUAL


RESULT:

Gain AV without Feedback

Gain AV with Feedback

Bandwidth without Feedback

Bandwidth with Feedback

Input impedance Zi without feedback

Input impedance Zi with feedback

Output impedance ZO without feedback

Output impedance ZO with feedback

AEC LAB MANUAL


THEVENIN’S AND MAXIMUM POWER TRANSFER THEOREM

AIM:

To verify Theveinin’s theorem.


Sl. No Components Range Quantity

1 Resistors 1K 4


3 Multimeter - 1

4 Connecting Wires - 1 Set

5 DRB - 1

THEVENIN’S THEOREM:

Statement: “Any linear, bilateral network containing energy sources and impedances can be

replaced with equivalent circuit consisting of a Voltage Source in series with Impedance”.

THEORY:

M Leon Thevenin a French engineer in 1863 developed the most important theorem of all

network theorems. Using Thevenin’s theorem any complex network can be replaced by a simple equivalent circuit. The new simple single loop equivalent circuit enables us to make rapid

calculations of the current, voltage and power delivered to the load by the original network. It

also helps us to find the best value of load resistance needed for a particular application.

CIRCUIT DIAGRAM:

Given complex circuit

Fig. (1)

Measure the voltage across Load Resistance RL, i.e. across A and B and call that voltage as V1.

V1 =V.

AEC LAB MANUAL


Step 1: Equivalent Circuit to find VTH by opening Load Resistance RL across A and B

Fig. (2)

Measure the voltage across A and B and call that voltage as VTH.

VTH =______V.

Step 2: Equivalent Circuit to find RTH by removing RL across A and B and shorting the

supply voltage.

Fig. (3)

Measure the Resistance across A and B and call that Resistance as RTH.

RTH =_____Ω.

Step3: Thevenin’s Equivalent circuit

Fig. (4)

AEC LAB MANUAL


Measure the voltage across A and B and call that voltage as V2.

V2 =_____V.

If the voltage,V1 = V2, then Thevinin’s theorem is verified.

THEORETICAL CALCULATION:

VTH=

RTH = +R2

PROCEDURE:

1. Connections are made as shown in fig. (1).

2. Keep the voltage knobs at minimum position and Current knobs at Maximum position

and then switch on the power supply and adjust the voltage to say 5 Volts.

3. Measure the voltage across RL and note down as V1 from fig. (1).

4. To measure VTH, Open circuits the load resistor RL as shown in fig. (2), measure the

voltage across terminal A and B, call that voltage as VTH.

5. To find the Thevinin’s impedance (RTH) measure the resistance between the terminals A

and B after shorting the supply voltage as shown in fig. (3).

6. Thevinin’s equivalent circuit connections are made by setting supply voltage to VTH and

decade resistance box to RTH and connect back the load resistor RL across A and B as

shown in Fig. (4).

7. Now measure the Voltage across load resistor RL with respect to Thevinin’s equivalent

circuit. i.e. V2

8. Verify the voltages V1 and V2.

RESULT:

Voltage across the load resistor RL with respect to complex circuit = V.

Voltage across the load resistor RL with respect to Thevinin’s equivalent circuit = V.

AEC LAB MANUAL


MAXIMUM POWER TRANSFER THEOREM

AIM: To verify maximum power transfer theorem.


Sl No Components Range Quantity

1 Resistors 1.5 K 1

2 DC variable Power

supply

(0-30) V 1

3 Multimeter - 1

4 Connecting Wires - 1 Set

5 DRB - 1

MAXIMUM POWER TRANSFER THEOREM:

Statement: Maximum power is delivered from a network to a load when the load resistance is

equal to the Thevenin’s resistance of the network.

THEORY:

In many practical applications a circuit is designed to supply power to the load. For example in

communication systems, antennas supply power to receivers, audio amplifiers supply power to

load speakers, transmitters supply power to loads. Maximum power transfer theorem plays an

important role in matching circuit’s loads.

CIRCUIT DIAGRAM:

Given complex circuit

Fig. (1): Complex Network

AEC LAB MANUAL


Thevinin’s Equivalent circuit

Fig. (2): Thevinin’s Network

THEORITICAL CALCULATION:

VTH = = 5V

RTH = = 500Ω

PROCEDURE:

1. The resistance value in DRB is varied and the Voltage is noted down.

2. Connections are made as shown in the figure.

3. The power P is calculated using P= V2/RL.

4. A graph of load resistance Vs Power is plotted.

5. The maximum power occurs when RL = RS.

POWER Vs LOAD RESISTANCE CURVE:

P

Fig (3): Graph of Power v/s RL

AEC LAB MANUAL


TABULAR COLUMN

RL in Ω VO in Volts P = V2/RL (mW)

100 Ω

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

1K Ω

RESULT:

AEC LAB MANUAL


CHARACTERISTICS OF RESONANT CIRCUITS

AIM: To obtain the frequency response of RLC series and parallel resonant circuits and hence to

determine bandwidth and Q-factor.



1 Resistors 1KΩ 1

2 DSO - 1

3 Decade Capacitance Box - 1

4 Decade Inductance Box - 1



.

THEORY:

In a circuit containing capacitive and inductive components, the impedance of the circuit varies

as the applied voltage’s frequency is varied. At one point of frequency, the impedance offered by the circuit will be purely resistive and so the current in the circuit and applied voltage will be in

phase. This phenomenon is called resonance and the frequency which causes resonance is called

resonant frequency.

SERIES RESONANCE CIRCUIT:

AEC LAB MANUAL


DESIGN:

fo = √

Let fo = 800Hz

Assume R = 1KΩ

C = 0.1µF

Calculate L value

L = 395.7mH

PROCEDURE:


2. AC supply is switched on. Input voltage is adjusted to 10VP-P.

3. The frequency is gradually varied from 100Hz to 2KHz. Different values of ‘f’ using

DSO and voltage is noted down. The results are tabulated in the tabular column.

4. Frequency response i.e a graph of frequency Vs current is drawn.

5. From the graph, resonant frequency fO is noted down at which current is maximum.

6. Lower half frequency and upper half frequency are noted down corresponding to a

current of IO/√ . Bandwidth = f2 – f1 = Hz.

7. Q-factor = f2/(f2-f1).

TABULAR COLUMN

Frequency in

Hz

Output Voltage VO

(V)

AEC LAB MANUAL


FREQUENCY RESPONSE CURVE

VO (V)

F (Hz)

Fig: Graph of Voltage Vs Frequency

RESULT:

Resonant Frequency =

Bandwidth =

Upper and lower half frequencies =

Q-factor =

AEC LAB MANUAL


PARALLEL RESONANCE CIRCUIT:

:

DESIGN:

fo = √

Let fo = 800Hz

Assume R = 1KΩ

C = 0.1µF

Calculate L value

L = 395.7mH

PROCEDURE:


2. AC supply is switched on. Input voltage is adjusted to 10VP-P.

3. The frequency is gradually varied from 100Hz to 2KHz. Different values of ‘f’ using DSO and voltage is noted down. The results are tabulated in the tabular column.

4. Frequency response i.e a graph of frequency Vs current is drawn.

5. From the graph, resonant frequency fO is noted down at which current is maximum.

6. Lower half frequency and upper half frequency are noted down corresponding to a

current of IO/√ . Bandwidth = f2 – f1 = Hz.

7. Q-factor = f2/(f2-f1).

AEC LAB MANUAL


TABULAR COLUMN

Frequency in

Hz

Output Voltage VO

(V)

FREQUENCY RESPONSE CURVE:

VO(V)

F(Hz)

Fig: Graph of Voltage Vs Frequency

AEC LAB MANUAL


RESULT:

Resonant Frequency =

Bandwidth =

Upper and lower half frequencies =

Q-factor =

AEC LAB MANUAL


BJT DARLINGTON EMITTER FOLLOWER

AIM:

Wiring of BJT Darlington emitter follower with and without Bootstrapping and determination of

the gain, input impedance and output impedance.



1 Resistors 1K, 220K, 330K, 4.7K 1

2 Capacitors 0.47µF 2


4 D.C Variable Power supply (0-30)V 1

5 Multimeter - 1

6 Connecting Wires - 1set

7 Decade Resistance box - 1

THEORY:

In emitter follower, an input signal is applied to the base and the output is taken across the

emitter. The emitter follower has reasonably high input impedance and may be used whenever

impedance up to about 500K is needed. For higher input impedance, we may use two transistors

to form Darlington pair. The output voltage is always less than the input voltage due to drop

between the base and emitter. However, the voltage gain is approximately unity. In addition the

output voltage is in phase with the input voltage. Hence it is said to follow the input voltage with

an in phase relationship. This accounts for the terminology ’Emitter Follower’. The collector is at ac ground; therefore the circuit is actually common collector amplifier. This circuit presents high

input impedance at the input and low output impedance at the output. It is therefore frequently

used for impedance matching purposes, where load impedance is matched to source impedance

for maximum signal transfer.

The Darlington connection shown is a connection of two transistors which results in a current

gain that is the product of the current gains of the individual transistors. Hence the Darlington

pair operates as one ‘Super Beta Transistor’ offering a very high current gain. The Darlington

Emitter follower is a CC configuration but has the following characteristics.

Voltage Gain = Almost Unity

Current Gain = Very High, a few thousands

Input Impedance = High, hundreds of KΩ

Output Impedance = Low, tens of Ohms

AEC LAB MANUAL


Bootstrapped Emitter Follower: To overcome the decrease in the input impedance due to the

biasing resistors, the input circuit of fig.1 is modified by the addition of the resistor R3 and

capacitor in between R1 and R2 as shown in fig.2. The capacitance is chosen large enough to act

as a short circuit at the lowest frequency of operation. Hence the bottom of R3 is effectively

connected to output and the top of R3 is at the input. Using the concept of Miller’s theorem, the biasing arrangement R1, R2, R3 represents the input impedance of R3/(1-AV), which is very very

high as AV is almost equal to 1. The term bootstrapping arises from the fact that, if one end of the

resistor of R3 changes in voltage, the other end of R3 moves through the same potential

difference, it is as if R3 is pulling itself by its bootstraps. The output impedance in this case will

be almost equal to that of Darlington circuit

DESIGN:

Let Q-point = (VCE2, IC2) = (5V, 5mA)

Let VCC = 2 VCE2 = 10V

RE = =

= =

RE = 1KΩ.

Consider β1 = β2 = β = 50.

IB2 = IE1 = = 0.1mA

Therefore, IB1 = =

= = 0.002mA.

Applying KVL to B-E loop

V2 = 0.6V + 0.6V + 5V = 6.2V

R2 = =

= 344KΩ. Select 330KΩ

R1 = =

= 190KΩ. Select 220KΩ

AEC LAB MANUAL


CIRCUIT DIAGRAM:

Fig: Darlington Emitter follower without bootstrap

Fig: Darlington Emitter follower with bootstrap

AEC LAB MANUAL


PROCEDURE:

1. Place the components on the bread/spring board as shown in the figure.

2. Connect the signal generator and apply a sine wave of peak-to-peak amplitude 1V, 1KHz.

Connect the input and output of the circuit to the two channels of the CRO and observe

the waveforms.

3. Gradually increase the input signal until the signal gets distorted. When this happens

slightly reduce the input signal amplitude such that output is maximum undistorted

signal. Then measure the amplitude of the input and output waveform. Calculate the

voltage gain.

4. Connect input and output of the circuit to the two channels of the CRO/DSO and observe

the waveforms. Note down the corresponding waveform on the graph.

5. Find the input and output impedance per given procedure.

6. Connect the bootstrap circuit and make the necessary changes as per figure.

7. Find the input and output impedance with this circuit.

Input Impedance Zi

1. Adjust the input signal peak-peak in such that the output sine wave is not clipped.

2. Note down this value of the input Vin.(Let the frequency of the input signal be around

2KHz)

3. Note down the peak-peak amplitude of the corresponding output VO.

4. Connect a DRB (with zero resistance) in series with the function generator.

5. Increase the resistance in DRB and observe the magnitude of the output VO

simultaneously on the CRO/DSO.

6. When the magnitude of the output VO is reduced to half of its original value, stop varying

the potentiometer further and remove the DRB from the circuit.

7. Measure the value of resistance in DRB and this is measured value will be the input

impedance of the circuit.

AEC LAB MANUAL


Output Impedance ZO

1. Adjust the input signal peak-peak in such that the output sine wave is not clipped.

2. Note down this value of the input Vin.

3. Note down the peak-peak amplitude of the corresponding output VO.

4. Connect a DRB (with maximum resistance) in parallel with the load.

5. When the magnitude of the output VO is reduced to half of its original value, stop varying

the potentiometer further and remove the DRB from the circuit.

6. Measure the value of resistance in DRB and this is measured value will be the output

impedance of the circuit.

RESULT:

Parameters AV = (VO/Vi) Zi ZO

Without Bootstrap

With Bootstrap

AEC LAB MANUAL


TRANSFORMER-LESS CLASS B PUSH-PULL POWER AMPLIFIER

AIM:

Testing of a transformer less class-B push pull power amplifier and determination of its

conversion efficiency.



1 Transistors SL-100, SK-100 1

2 Resistors 270Ω 2



5 DSO - 1

6 Decade Resistance box - 1

7 Connecting Wires - 1set

THEORY:

Push-pull amplifier is basically a class B amplifier, in which a transistor conducts for a half

cycle. For complete conduction, such an amplifier uses two transistors. The arrangement of

transistors is called complementary circuit. During the positive half of the input signal, the NPN

transistor conducts and during negative half of the input signal PNP transistor conducts. The

transistor conducts only if the input voltage across the threshold voltage of 0.7V. This is because

input itself biases the transistors. During this interval, no transistors conducts or output is zero.

This causes a distortion called crossover distortion. If the peak load-voltage equals the supply

voltage, maximum efficiency occurs and the value is 78.5%. The main disadvantage is it uses

two power supply and distortion itself.

AEC LAB MANUAL


CIRCUIT DIAGRAM:

Fig. (1)

PROCEDURE:

1. Place the components on the spring board and connect them as shown in the fig.(1).

2. Connect one channel of the CRO to input signal and connect second channel to the

output.

3. Keep frequency of the function generator around 1KHz and increase the amplitude

around 10V and observe the input and output waveforms. Observe the crossover

distortion.

4. Gradually increase the input signal until the output signal gets distorted. When this

happens slightly reduce the input signal amplitude such that output is maximum

undistorted signal. Note down the Peak value of the output waveform and VCC.

5. Calculate the efficiency using the equation % efficiency = .

AEC LAB MANUAL


TABULAR COLUMN:

RL in KΩ %Efficiency

1KΩ

.

.

.

.

.

.

.

.

.

.

10KΩ

RESULT:

The efficiency of the class B power amplifier for different load resistance is verified.

AEC LAB MANUAL


BIBLIOGRAPHY

1. “Electronic devices and circuit theory”, Robert L.Boylestad and

Louis Nashelsky.

2. “Integrated electronics”, Jacob Millman and Christos C Halkias.

3. “Electronic devices and circuits”, David A. Bell.

4. “Electronic devices and circuits”, G.K.Mittal.

AEC LAB MANUAL


VIVA-VOCE QUESTIONS

1. What are conductors, insulators, and semi-conductors? Give egs.

2. Name different types of semiconductors.

3. What are intrinsic semiconductors and extrinsic semiconductors?

4. How do you get P-wpe and N-type semiconductors?

5. What is doping? Name different levels of doping.

6. Name different types of Dopants. .

7. What do you understand by Donor and acceptor atoms?

8. What is the other name for p-type and N-type semiconductors?

9. What are majority carriers and minority carriers?

10. What is the effect of temperature on semiconductors?

11. What is drift current? .

12. What is depletion region or space charge region?

13. What is junction potential or potential barrier in PN junctioI).?

14. What is a diode? Name different types of diodes and name its applications

15. What is biasing? Name different types w.r.t. Diode biasing

16. How does a diode behave in its forward and reverse biased conditions?

17. What is static and dyriantic resistance of diode?

18. Why the current in the fo~ard biased diode takes exponential path?

19. What do you understand 1?y AvaJanche breakdown and zener breakdown?

20. Why diode is called unidirectional device.

21. What is PIV of a diode

22. What is knee voltage or cut-in voltage?

23. What do you mean by transition capacitance or space charge capacitor?

24. What do you mean by diffusion capacitance or storage capacitance?

25. What is a transistor? Why is it called so? .

26. Name different types, of transistors?

27. Name different configurations in which the transistor is operated

28. Mention the applications of transistor. Explain how transistor is used as switch

29. What is transistor biasing? Why is it necessary?

30. What are the three different regions in which the transistor works?

31. Why trmisistor is called current controlled device?

32. What is FET? Why it is called so?

33. What are the parameters ofFET?

34. What are the characteristics of FET?

35. Why FET is known as voltage controlled device?

36. What are the differences between BJT and FET?

37. Mention applications ofFET. What is pinch offvQltage, VGS(ofJ) and lDss

38. What is an amplifier? What is the need for an amplifier circuit?

39. How do you classify amplifiers? ,

40. What is faithful amplification? How do you achieve this?

41. What is coupling? Name different type.s of coupling

42. What is operating point or quiescent point?

43. What do you mean by frequency response of an amplifier?

44. What are gain, Bandwidth, lower cutoff frequency and upper cutoff frequency?

45. What is the figure of merit of an amplifier circuit?

AEC LAB MANUAL


46. What are the advantages of RC coupled amplifier?

47. Why a 3db point is taken to calculate Bandwidth?

48. What is semi-log graph sheet? Why it is used to plot frequency response?

49. How do you test a diode, transistor, FET?

50. How do you identify the tenninals of Diode, Transistor& FET? Mention the type

number of the devices used in your lab.

51. Describe the operation ofNPN transistor. Define reverse saturation current.

52. Explain Doping w.r.t. Three regions of transistor

53. Explain the terms hie/hib, hoelhob, hre/hrb, hre/hfb.

54. Explain thermal run-.taway. How it can'be prevented.

55. Define FET parameters and write the relation between them.

56. What are Drain Characteristics and transfer characteristics?

57. Explain the construction and working of FET

58. What is feedback? Name different types.

59. What is the effect of negative feedback on the characteristics of an amplifier?

60. Why common collector amplifier is known as emitter follower circuit?

61. What is the application of emitter follower ckt?

62. What is cascading and cascoding? Why do you cascade the amplifier ckts.?

63. How do you determine the value of capacitor?

64. Write down the diode current equation.

65. Write symbols of various passive and active components

66. How do you determine th~value of resistor by colour code method?

67. What is tolerance and power rating of resistor?

68. Name different types of resistors.

69. How do you c1assify resistors?

70. Name different types of capacitors..

71. What are clipping circuits? Classify them.

72. Mention the application of clipping circuits.

73. What are clamping circuits? Classify them

74. What is the other name of clamping circuits?

75. Mention the applications of clamping circuits.

76. 'What is Darlington emitter follower circuit?

77. Can we increase the number of transistors in Darlington emitter follower circuit?

Justify your answer.

78. What is the different between Darlington emitter follower circuit & Voltage follower

circuit using Op-Amp. Which is better.

79. Name different types of Emitter follower circuits.

80. What is an Oscillator? Classify them.

81. What ar~ The Blocks, which fonns an Oscillator circuits?

82. What are damped & Un-damped Oscillations?

83. What are Barkhausen's criteria?

84. What type of oscillator has got frequency stability?

85. What is the disadvantage of Hartley & Colpiit's Oscillator?

86. Why RC tank Circuit Oscillator is used for AF range?

87. Why LC tank Circuit Oscillator is used for RF range?

88. What type of feedback is used in Oscillator circuit?

89. In a Transistor type No. SL 100 and in Diode BY 127, what does SL and BY stands

AEC LAB MANUAL


for

90. Classify Amplifiers based on: operating point selection.

91. What is the efficiency of Class B push pull amplifier?

92. What is the drawback of Class B Push pull Amplifier? How it is eliminated.

93. What is the advantage of having complimentary symmetry push pull amplifier?

94. What is Bootstrapping? What is the advantage of bootstrapping?

95. State Thevenin's Theorem and Max.power transfer theorem.

96. What is the figure of merit of resonance circuit?

97. What is the application of resonant circuit?

98. What is a rectifier? Classify.

99. What is the efficiency of half wave and full wave rectifier?

100. What is the advantage of Bridge rectifier of Centre tapped type FWR

101. What is the disadvantage of Bridge rectifier?

102. What is a filter?

103. Name different types of filter ckts.

104. Which type of filter is used in day to day application and why?

105. What is ripple and ripple factor? .

106. What is the theoretical value of ripple for Half Wave and .Full wave rectifier?

107. What is need for rectifier ckts.

108. Why a step down transformer is used at the input of Rectifier ckt.

109. What is TUF? .

110. What is regulation w.r.t rectifier? And how it is calculated?

111. What is figure of merit of Rectifier ckt.

AEC LAB MANUAL


QUESTION BANK

ANALOG ELECTRONIC CIRCUITS LAB (10ESL37)

1. A) Design a positive clamping circuit for a given reference voltage of Vref=+2v. B) Design a negative clamping circuit for a given reference voltage ofVref= -2v.

2. Conduct a suitable experiment to shift the given reference voltage waveform by 4v a) Above the reference waveform b) Below the reference waveform

3. Design and rig up suitable circuits to shift the given reference sinusoidal input voltage waveform as shown in the fig.

Vo V0

0 t

-1.5

-6.5 2.5

-11.5 0 t

-2.5

4. Design and rig up suitable circuits for the following transfer function as shown in the fig. For a sinusoidal/triangular input.(any two to be specified)

AEC LAB MANUAL


5. Design a suitable circuit to clip the reference voltage waveform at two different levels. Also obtain its transfer characteristics.

6. Rig up a suitable circuit for A) Diode positive peak clipping. B) Diode negative peak clipping.

7. Conduct an experiment to determine the gain v/s frequency response, input and output

impedances for a RC coupled single stage BJT amplifier.

8. Conduct an experiment to determine gain, input and output impedances for a Darlington

emitter follower circuit with and without bootstrap.

9. Conduct an experiment to obtain a relationship between the bandwidths for a voltage

series feedback circuit with and without feedback.

10. Design the LC oscillator circuits to generate frequency of oscillations at f=100 khz

Using BJT.

AEC LAB MANUAL


11. Design and rig up Hartley and colpitts oscillator circuits for a given frequency using BJT.

12. Conduct an experiment to generate the given frequency of an oscillation. (type of the

oscillator to be specified).

13. Conduct a suitable experiment to introduce a phase shift of 1800 at an audio frequency

Range.

14. Conduct a suitable experiment to produce sinusoidal oscillations using RC phase shift network.

15. Conduct a suitable experiment to determine the frequency of oscillations of a given crystal.

16. Determine ripple factor, regulation and efficiency of Half wave Rectifier Circuit with and Without Capacitor filter.

17. Determine ripple factor, regulation and efficiency of center tapped Full wave Rectifier Circuit with

and Without Capacitor filter.

AEC LAB MANUAL


18. Determine ripple factor, regulation and efficiency of Bridge Rectifier Circuit with and

Without Capacitor filter.

19. Conduct an experiment to verify Thevenin’s Theorem and Maximum Power Transfer theorem. 20. Rig up suitable circuit to determine the Characteristics of Series and Parallel resonant circuits

21. Rig up suitable circuit to determine the Characteristics of RLC circuits.

1N

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© 2007 Fairchild Semiconductor Corporation www.fairchildsemi.com

1N5221B - 1N5263B Rev. 1.2.0 1

July 2013

1N5221B - 1N5263BZener Diodes

Absolute Maximum RatingsStresses exceeding the absolute maximum ratings may damage the device. The device may not function or be opera-ble above the recommended operating conditions and stressing the parts to these levels is not recommended. In addi-tion, extended exposure to stresses above the recommended operating conditions may affect device reliability. Theabsolute maximum ratings are stress ratings only. Values are at TA = 25°C unless otherwise noted.

Note:

1. These ratings are limiting values above which the serviceability of any semiconductor device may be impaired.

Non-recurrent square wave Pulse Width = 8.3 ms, TA = 50°C

Symbol Parameter Value Units

PD

Power Dissipation 500 mW

Derate above 50°C 4.0 mW°C

TSTG Storage Temperature Range -65 to +200 °C

TJ

Operating Junction Temperature Range -65 to +200 °C

Lead Temperature (1/16 inch from case for 10 s) +230 °C

DO-35 Glass caseCOLOR BAND DENOTES CATHODE

Tolerance = 5%

1N

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1N5221B - 1N5263B Rev. 1.2.0 2

Electrical Characteristics

Values are at TA = 25°C unless otherwise noted .

Note:

2. Zener Voltage (VZ) The zener voltage is measured with the device junction in the thermal equilibrium at the lead temperature (TL) at 30°C ± 1°C and 3/8” lead length.

DeviceVZ (V) @ IZ (2)

ZZ (Ω) @ IZ (mA) ZZK (Ω) @ IZK(mA) IR (µA) @ VR (V)TC

(%/°C)Min. Typ. Max.

1N5221B

1N5222B

1N5223B

1N5224B

1N5225B

2.28

2.375

2.565

2.66

2.85

2.4

2.5

2.7

2.8

3

2.52

2.625

2.835

2.94

3.15

30

30

30

30

29

20

20

20

20

20

1,200

1,250

1,300

1,400

1,600

0.25

0.25

0.25

0.25

0.25

100

100

75

75

50

1.0

1.0

1.0

1.0

1.0

-0.085

-0.085

-0.080

-0.080

-0.075

1N5226B

1N5227B

1N5228B

1N5229B

1N5230B

3.135

3.42

3.705

4.085

4.465

3.3

3.6

3.9

4.3

4.7

3.465

3.78

4.095

4.515

4.935

28

24

23

22

19

20

20

20

20

20

1,600

1,700

1,900

2,000

1,900

0.25

0.25

0.25

0.25

0.25

25

15

10

5.0

2.0

1.0

1.0

1.0

1.0

1.0

-0.07

-0.065

-0.06

+/-0.055

+/-0.03

1N5231B

1N5232B

1N5233B

1N5234B

1N5235B

4.845

5.32

5.7

5.89

6.46

5.1

5.6

6

6.2

6.8

5.355

5.88

6.3

6.51

7.14

17

11

7.0

7.0

5.0

20

20

20

20

20

1,600

1,600

1,600

1,000

750

0.25

0.25

0.25

0.25

0.25

5.0

5.0

5.0

5.0

3.0

2.0

3.0

3.5

4.0

5.0

+/-0.03

0.038

0.038

0.045

0.05

1N5236B

1N5237B

1N5238B

1N5239B

1N5240B

7.125

7.79

8.265

8.645

9.5

7.5

8.2

8.7

9.1

10

7.875

8.61

9.135

9.555

10.5

6.0

8.0

8.0

10

17

20

20

20

20

20

500

500

600

600

600

0.25

0.25

0.25

0.25

0.25

3.0

3.0

3.0

3.0

3.0

6.0

6.5

6.5

7.0

8.0

0.058

0.062

0.065

0.068

0.075

1N5241B

1N5242B

1N5243B

1N5244B

1N5245B

10.45

11.4

12.35

13.3

14.25

11

12

13

14

15

11.55

12.6

13.65

14.7

15.75

22

30

13

15

16

20

20

9.5

9.0

8.5

600

600

600

600

600

0.25

0.25

0.25

0.25

0.25

2.0

1.0

0.5

0.1

0.1

8.4

9.1

9.9

10

11

0.076

0.077

0.079

0.080

0.082

1N5246B

1N5247B

1N5248B

1N5249B

1N5250B

15.2

16.15

17.1

18.05

19

16

17

18

19

20

16.8

17.85

18.9

19.95

21

17

19

21

23

25

7.8

7.4

7.0

6.6

6.2

600

600

600

600

600

0.25

0.25

0.25

0.25

0.25

0.1

0.1

0.1

0.1

0.1

12

13

14

14

15

0.083

0.084

0.085

0.085

0.086

1N5251B

1N5252B

1N5253B

1N5254B

1N5255B

20.9

22.8

23.75

25.65

26.6

22

24

25

27

28

23.1

25.2

26.25

28.35

29.4

29

33

35

41

44

5.6

5.2

5.0

4.6

4.5

600

600

600

600

600

0.25

0.25

0.25

0.25

0.25

0.1

0.1

0.1

0.1

0.1

17

18

19

21

21

0.087

0.088

0.088

0.089

0.090

1N5256B

1N5257B

1N5258B

1N5259B

1N5260B

28.5

31.35

34.2

37.05

40.85

30

33

36

39

43

31.5

34.65

37.8

40.95

45.15

49

58

70

80

93

4.2

3.8

3.4

3.2

3.0

600

700

700

800

900

0.25

0.25

0.25

0.25

0.25

0.1

0.1

0.1

0.1

0.1

23

25

27

30

33

0.09

0.092

0.093

0.094

0.095

1N5261B

1N5262B

1N5263B

44.65

48.45

53.2

47

51

56

49.35

53.55

58.8

105

125

150

2.7

2.5

2.2

1000

1100

1300

0.25

0.25

0.25

0.1

0.1

0.1

36

39

43

0.095

0.096

0.096

VF Forward Voltage = 1.2V Max. @ IF = 200mA

1N

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1N5221B - 1N5263B Rev. 1.2.0 3

Top Mark Information

Device Line 1 Line 2 Line 3

1N5221B

1N5222B

1N5223B

1N5224B

1N5225B

LOGO

LOGO

LOGO

LOGO

LOGO

22

22

22

22

22

1B

2B

3B

4B

5B

1N5226B

1N5227B

1N5228B

1N5229B

1N5230B

LOGO

LOGO

LOGO

LOGO

LOGO

22

22

22

22

23

6B

7B

8B

9B

0B

1N5231B

1N5232B

1N5233B

1N5234B

1N5235B

LOGO

LOGO

LOGO

LOGO

LOGO

23

23

23

23

23

1B

2B

3B

4B

5B

1N5236B

1N5237B

1N5238B

1N5239B

1N5240B

LOGO

LOGO

LOGO

LOGO

LOGO

23

23

23

23

24

6B

7B

8B

9B

0B

1N5241B

1N5242B

1N5243B

1N5244B

1N5245B

LOGO

LOGO

LOGO

LOGO

LOGO

24

24

24

24

24

1B

2B

3B

4B

5B

1N5246B

1N5247B

1N5248B

1N5249B

1N5250B

LOGO

LOGO

LOGO

LOGO

LOGO

24

24

24

24

25

6B

7B

8B

9B

0B

1N5251B

1N5252B

1N5253B

1N5254B

1N5255B

LOGO

LOGO

LOGO

LOGO

LOGO

25

25

25

25

25

1B

2B

3B

4B

5B

1N5256B

1N5257B

1N5258B

1N5259B

1N5260B

LOGO

LOGO

LOGO

LOGO

LOGO

25

25

25

25

26

6B

7B

8B

9B

0B

1N5261B

1N5262B

1N5263B

LOGO

LOGO

LOGO

26

26

26

1B

2B

3B

1N

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1N5221B - 1N5263B Rev. 1.2.0 4

Top Mark Information (Continued)

General Requirements:

1.0 Cathode Band

2.0 First Line: F - Fairchild Logo

3.0 Second Line: Device name - For 1Nxx series: 4th to 5th characters of the device name.

For BZxx series: 5th to 6th characters of the device name.

4.0 Third Line: Device name - For 1Nxx series: 6th to 7th characters of the device name.

For BZXyy series: Voltage rating

5.0 Devices shall be marked as required in the device specification (PID or FSC Test Spec).

6.0 Maximum no. of marking lines: 3

7.0 Maximum no. of digits per line: 2

8.0 FSC logo must be 20 % taller than the alphanumeric marking and should occupy the 2 characters of the specified

line.

9.0 Marking Font: Arial (Except FSC Logo)

10.0 First character of each marking line must be aligned vertically.

11.0 All device markings must be based on Fairchild device specification.

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1N5221B - 1N5263B Rev. 1.2.0 5

Physical Dimensions

Figure 1. AXIAL LEADED; GLASS; JEDEC DO204; VARIATION AH (ACTIVE)

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the

warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/dwg/DO/DO35A.pdf.

For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area:

http://www.fairchildsemi.com/packing_dwg/PKG-DO35A_TC.pdf.

25.40 MIN

(2X)

0.533

0.460

4.56

3.05

1.91

1.53

NOTES: UNLESS OTHERWISE SPECIFIED

A) PACKAGE STANDARD REFERENCE: JEDEC DO-204, VARIATION AH.

B) HERMETICALLY SEALED GLASS PACKAGE. C) PACKAGE WEIGHT IS 0.137 GRAM. D) ALL DIMENSIONS ARE IN MILLIMETERS. E) DRAWING FILE NAME: DO35AREV02

DO-35

© Fairchild Semiconductor Corporation www.fairchildsemi.com

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PowerTrench®

PowerXS™

Programmable Active DroopQFET

®

QS

Quiet Series

RapidConfigure

Saving our world, 1mW/W/kW at a time™

SignalWise

SmartMax

SMART START

Solutions for Your SuccessSPM

®

STEALTHSuperFET

®

SuperSOT -3

SuperSOT -6

SuperSOT -8 SupreMOS

®

SyncFET

Sync-Lock™

®*

TinyBoost

TinyBuck

TinyCalcTinyLogic

®

TINYOPTO

TinyPower

TinyPWM

TinyWire

TranSiC

TriFault DetectTRUECURRENT

®*

SerDes

UHC®

Ultra FRFET

UniFET

VCX

VisualMax

VoltagePlusXS™

* Trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.

2. A critical component in any component of a life support, device, or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

ANTI-COUNTERFEITING POLICY

Fairchild Semiconductor Corporation's Anti-Counterfeiting Policy. Fairchild's Anti-Counterfeiting Policy is also stated on our external website, www.fairchildsemi.com, under Sales Support.

Counterfeiting of semiconductor parts is a growing problem in the industry. All manufacturers of semiconductor products are experiencing counterfeiting of their parts. Customers who inadvertently purchase counterfeit parts experience many problems such as loss of brand reputation, substandard performance, failed applications, and increased cost of production and manufacturing delays. Fairchild is taking strong measures to protect ourselves and our customers from the proliferation of counterfeit parts. Fairchild strongly encourages customers to purchase Fairchild parts either directly from Fairchild or from Authorized Fairchild Distributors who are listed by country on our web page cited above. Products customers buy either from Fairchild directly or from Authorized Fairchild Distributors are genuine parts, have full traceability, meet Fairchild's quality standards for handling and storage and provide access to Fairchild's full range of up-to-date technical and product information. Fairchild and our Authorized Distributors will stand behind all warranties and will appropriately address any warranty issues that may arise. Fairchild will not provide any warranty coverage or other assistance for parts bought from Unauthorized Sources. Fairchild is committed to combat this global problem and encourage our customers to do their part in stopping this practice by buying direct or from authorized distributors.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications may change in any manner without notice.

Preliminary First Production Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design.

No Identification Needed Full Production Datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve the design.

Obsolete Not In Production Datasheet contains specifications on a product that is discontinued by Fairchild Semiconductor. The datasheet is for reference information only.

Rev. I64

®

AEC LAB MANUAL


AEC LAB MANUAL


AEC LAB MANUAL


AEC LAB MANUAL


AEC LAB MANUAL


VALUE(pF) CODE VALUE(pF) VALUE(uF) CODE

1.5pF 1,000pF .001uF 102

3.3pF 1,500pF .0015uF 152

10pF 2,000pF .002uF 202

15pF 2,200pF .0022uF 222

20pF 4,700pF .0047uF 472

30pF 5,000pF .005uF 502

33pF 5,600pF .0056uF 562

47pF 6,800pF .0068uF 682

56pF .01uF 103

68pF .015

75pF .02 203

82pF .022 223

91pF .033 333

100pF 101 .047 473

120pF 121 .05 503

130pF 131 .056 563

150pF 151 .068 683

180pF 181 .1 104

220pF 221 .2 204

330pF 331 .22 224

470pF 471 .33 334

560pF 561 .47 474

680pF 681 .56 564

750pF 751 1 105

820pF 821 2 205

AEC LAB MANUAL


Capacitor Types and colors:

1pf - 1800pf Yellow Ceramic Disk or Blue or Yellow Monolithics

.001; .01; .022; .047; 0.1; 0.47; 1uF (C96 on

K2) Red Monolithics

Temperature stable caps are marked "NP0", "C0G" or have a black top.

Capacitor Marking Table (Ceramic and Monolithic Cap's)

IMPORTANT: Capacitors with values below 100 pf may be marked two ways: Either with just

two digits (22 pF = "22") or three digits (22 pF = "220",). In the latter case the third digit

signifies the number of zeros following the first two digits. "220" = 22 pF, "221" = 220

pF, "222" = 2200 pF.

VALUE MARKING VALUE MARKING VALUE MARKING

1pf; 3pf; 5pf

1; 3; 5

2.7, 3 or 3.3 pF can be interchanged with each other.

4.7 or 5 pF can be interchanged with each other.

10 pf 10 or 100 0.001 uF 102 0.10 uF 104

12 pf 12 or 120 0.0012uF (1200pf)

122 0.12 uF 124

15 pf 15 or 150 0.0015uF 152 0.15 uf 154

18 pf 18 or 180 0.0018 uF

(1800pf)

182 0.18 uF 184

22 pf 22 or 220 0.0022uF 222 0.22 uF 224

27 pf 27 or 270 0.0027uF 272 0.27 uF 274

33 pf 33 or 330 0.0033 uF

332 0.33 uF 334

39 pf 39 or 390 0.0039uF 392 0.39 uF 394

47 pf 47 or 470 0.0047uF 472 0.47 uF 474

58 pf 58 or 580 0.0056uF 562 0.56 uF 564

68 pf 68 or 680 0.0068uF 682 0.68 uF 684

82 pf 82 or 820 0.0082uF 822 0.82 uF 824

100 pf 101 0.01 uF 103 1uF 105 or 1uf

120 pf 121 0.012 uF 123

150 pf 151 0.015 uF 153

180 pf 181 0.018 uF 183

220 pf 221 0.022 uF 223

270 pf 271 0.027 uF 273

330 pf 331 0.033 uF 333

390 pf 391 0.039 uF 393

470 pf 471 0.047 uF 473

560 pf 561 0.056 uF 563

680 pf 681 0.068 uF 683

820 pf 821

0.082 uF 823

AEC LAB MANUAL
