ANALOG AND DIGITAL COMMUNICATION Laboratory Manual K. Michael Mahesh M.E, MISTE, AMIE, MIET, MIEEE Assistant Professor / ECE St. Joseph College of Eng., Chennai. Abstract Analog and Digital Communication Laboratory Manual for ECE Department 2013 Regulation
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ANALOG AND DIGITAL COMMUNICATION
Laboratory Manual
K. Michael Mahesh M.E, MISTE, AMIE, MIET, MIEEE Assistant Professor / ECE
St. Joseph College of Eng., Chennai.
Abstract Analog and Digital Communication Laboratory Manual for ECE Department 2013 Regulation
1
ST. JOSEPH COLLEGE OF ENGINEERING Chennai - 602117
NAME :
ROLL NO :
CLASS / SEM : II B.E -ECE / III SEM
SECTION :
SUBJECT CODE : EC6311
SUBJECT NAME : ANALOG AND DIGITAL CIRCUITS LABORATORY
Prepared by
Mr. K. Michael Mahesh.,
M.E, MISTE, AMIE, MIET, MIEEE
Assistant Professor / ECE
St. Joseph College of Eng., Chennai.
2
LABORATORY REGULATIONS AND SAFETY RULES
The following Regulations and Safety Rules must be observed in all concerned
laboratory location.
It is the duty of all concerned who use any electronics laboratory to take all
reasonable steps to safeguard the HEALTH and SAFETY of themselves and
all other users and visitors.
Be sure that all equipment is properly working before using them for
laboratory exercises. Any defective equipment must be reported immediately
to the Lab. Instructors or Lab. Technical Staff.
Students are allowed to use only the equipment provided in the experiment
manual.
Power supply terminals connected to any circuit are only energized with the
presence of the Instructor or Lab. Staff.
Avoid any part of your body to be connected to the energized circuit and
ground.
Switch off the equipment and disconnect the power supplies from the circuit
before leaving the laboratory.
Observe cleanliness and proper laboratory housekeeping of the equipment and
other related accessories.
Make sure that the last connection to be made in your circuit is the power
supply and first thing to be disconnected is also the power supply.
Equipment should not be removed, transferred to any location without
permission from the laboratory staff.
Students are not allowed to use any equipment without proper orientation and
actual hands on equipment operation.
3
EXTRACT OF ANNA UNIVERSITY SYLLABUS
ANALOG AND DIGITAL CIRCUITS LABORATORY
LIST OF EXPERIMENTS
LIST OF ANALOG EXPERIMENTS:
1. Frequency Response of CE / CB / CC amplifier
2. Frequency response of CS Amplifiers
3. Darlington Amplifier
4. Differential Amplifiers- Transfer characteristic.
5. CMRR Measurment
6. Cascode / Cascade amplifier
7. Determination of bandwidth of single stage and multistage amplifiers
8. Spice Simulation of Common Emitter and Common Source amplifiers
LIST OF DIGITAL EXPERIMENTS
9. Design and implementation of code converters using logic gates
(i) BCD to excess-3 code and vice versa
(ii) Binary to gray and vice-versa
10. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC
7483
11. Design and implementation of Multiplexer and De-multiplexer using logic gates
12. Design and implementation of encoder and decoder using logic gates
13. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple
counters
14. Design and implementation of 3-bit synchronous up/down counter
15. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- flops
4
INDEX
S.NO
DATE
EXPERIMENT NAME
MARKS
SIGN
I CYCLE EXPERIMENTS ( ANALOG EXPERIMENTS)
1 (a) COMMON EMITTER AMPLIFIER
(b) COMMON BASE AMPLIFIER
(c) COMMON COLLECTOR AMPLIFIER
2 COMMON SOURCE AMPLIFIER
3 DARLINGTON AMPLIFIER
4 DIFFERENTIALAMPLIFIER
5 CASCODE AMPLIFIER
6 CASCADED AMPLIFIER
SIMULATION EXPERIMENT
7 COMMON EMITTER AMPLIFIER
8 COMMON SOURCE AMPLIFIER
II CYCLE EXPERIMENTS ( DIGITAL EXPERIMENTS)
9(a) BCD TO EXCESS-3 CODE
(b) EXCESS-3 TO BCD
(c) BINARY TO GRAY CODE
(d) GRAY TO BINARY CODE
10(a) 4 BIT BINARY ADDER/ SUBTRACTOR
(b) BCD ADDER USING IC 7483
11(a) MULTIPLEXER USING LOGIC GATES
(b) DEMULTIPLEXER USING LOGIC GATES
12(a) ENCODER
(b) DECODER
13(a) 4 BIT RIPPLE COUNTER
(b) MOD-10 / MOD-12 RIPPLE COUNTERS
14 3-BIT SYNCHRONOUS UP
COUNTER/DOWN COUNTER
15 SHIFT REGISTERS USING FLIP- FLOPS
5
EXP. NO : 1 (a) DATE:
COMMON EMITTER AMPLIFIER
Aim : To construct a Common Emitter Amplifier circuit and to plot it’s frequency
response characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor BC547 1
2. Resistors 63KΩ,12KΩ,600Ω,2.5KΩ Each 1
3. Capacitors 0.78µF,0.63 µF,2.6 µF Each 1
4. DC power supply 12 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
This type of biasing is otherwise called Emitter Biasing. The necessary biasing is provided
using 3 resistors: R1, R2 and RE. The resistors R1 and R2 act as a potential divider and give a
fixed voltage to the base. If the collector current increases due to change in temperature or change
in β, the emitter current IE also increases and the voltage drop across RE increases, reducing the
voltage difference between the base and the emitter. Due to reduction in VBE, base current IB and
hence collector current IC also reduces. This reduction in VBE, base current IB and hence collector
current IC also reduces. This reduction in the collector current compensates for the original change
in IC.
The stability factor S= (1+β) * ((1/ (1+β)). To have better stability, we must keep RB/RE
as small as possible. Hence the value of R1 R2 must be small. If the ratio RB/RE is kept fixed, S
increases with β.
6
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
7
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-peak
and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression 20
log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Common Emitter Amplifier circuit is constructed and it’s frequency response is
plotted.
8
EXP. NO : 1 (b) DATE:
COMMON BASE AMPLIFIER
Aim : To construct a Common Base Amplifier circuit and to plot it’s frequency response
characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 1
2. Resistors 15KΩ,10KΩ,4.7KΩ,3.3KΩ,1
KΩ
Each 1
3. Capacitors 10µF,100 µF 2,1
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
Common-base transistor amplifiers are so-called because the input and output voltage points
share the base lead of the transistor in common with each other, not considering any power
supplies.
The current gain of a common-base amplifier is always less than 1. The voltage gain is a
function of input and output resistances, and also the internal resistance of the emitter-base
junction, which is subject to change with variations in DC bias voltage. Suffice to say that the
voltage gain of a common-base amplifier can be very high.
The ratio of a transistor's collector current to emitter current is called α. The α value for any
transistor is always less than unity, or in other words, less than 1. Some of it’s applications include
radio frequency amplifiers. The grounded base helps shield the input at the emitter from the
collector output, preventing instability in RF amplifiers. The common base configuration is usable
at higher frequencies than common emitter or common collector.
9
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0
0
0
0
R4
4.7k
R3
15k
R2
3.3k
R1
10k
Q1
Q2N2222
C3
10u
C2
100u
C1
10u
R5
1k
V1
V3
20V
10
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Common Base Amplifier circuit is constructed and it’s frequency response is
plotted.
.
11
EXP. NO : 1 (C) DATE:
COMMON COLLECTOR AMPLIFIER
Aim : To construct a Common Collector Amplifier circuit and to plot it’s frequency
response characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 1
2. Resistors 200KΩ,10KΩ,100KΩ 2,1,1
3. Capacitors 0.01µF 2
4. DC power supply 15 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
Common-collector transistor amplifiers are so-called because the input and output voltage
points share the collector lead of the transistor in common with each other, not considering any
power supplies.
The common-collector amplifier is also known as an emitter-follower. The output voltage
on a common-collector amplifier will be in phase with the input voltage, making the common-
collector a non-inverting amplifier circuit.
The current gain of a common-collector amplifier is equal to β plus 1. The voltage gain is
approximately equal to 1. A popular application of the common-collector amplifier is for
regulated DC power supplies, where an unregulated (varying) source of DC voltage is clipped
at a specified level to supply regulated (steady) voltage to a load.
12
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0
0
R2
10k
R3
200k
R4
200k
C1
0.01u
V1
V3
15V
Q1
Q2N2222
C2
0.01u
R6
1000k
13
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) and thus calculate the Io (p-p)= Vo (p-p) / Ro for
various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The current gain can be calculated by using the expression 20*log (I0/Ii) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and the current gain in dB is calculated by using the
expression 20 log10 (I0/Ii).
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Ii = _______ mA
S.No.
Input signal
frequency in (Hz)
Output Voltage
Vo
(volt)
Output Current
Io= Vo/ Ro
(mA)
Gain in db
=20 log (I0/Ii)
RESULT:
Thus the Common Collector Amplifier circuit is constructed and it’s frequency response
is plotted.
14
EXP. NO : 2 DATE:
COMMON SOURCE AMPLIFIER
Aim : To construct a Common Source Amplifier circuit and to plot it’s frequency
response characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor BFW10 1
2. Resistors 220KΩ,68KΩ,2.2KΩ,
3.9KΩ, 5.6KΩ,1.5k
1 each
3. Capacitors 1µF, 10µF,6.8µF 1 each
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
The common-source (CS) amplifier may be viewed as a transconductance amplifier or as
a voltage amplifier.As a transconductance amplifier, the input voltage is seen as modulating the
current going to the load. As a voltage amplifier, input voltage modulates the amount of current
flowing through the FET, changing the voltage across the output resistance according to Ohm's
law. However, the FET device's output resistance typically is not high enough for a reasonable
transconductance amplifier, nor low enough for a decent voltage amplifier.
15
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0
J1
J2N3819
R4
2.2k
R1
3.9k
R5
68kC1
10u
C3
1u
C2
6.8u
V1
20V
R6
5.6k
V2
R13
1.5k
R14
220k
16
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Common Source Amplifier circuit is constructed and it’s frequency response is
plotted.
17
EXP. NO : 3 DATE:
DARLINGTON AMPLIFIER
Aim : To construct a Darlington Amplifier circuit and to find it’s frequency response.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 15KΩ,4.7KΩ,2.2KΩ,1KΩ,
1000KΩ
Each one
3. Capacitors 10µF 2
4. Dual DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9 Connecting Wires - Few
OVERVIEW :
In Darlington connection of transistors, emitter of the first transistor is directly connected
to the base of the second transistor .Because of direct coupling dc output current of the first stage
is (1+hfe )Ib1.If Darlington connection for n transistor is considered, then due to direct coupling
the dc output current for the last stage is nx(1+hfe ) times Ib1 .Due to a very large amplification
factor even two stage Darlington connection has large output current.
In Darlington transistor connection, the leakage current of the first transistor is amplified
by the second transistor and overall leakage current may be high, which is not desired.
18
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH :
0
0R7
15kC4
10u
V3
20V
V4
R36
1k
Q28
Q2N2222Q29
Q2N2222R34
1000k
C20
10u
R37
4.7k
R38
2.2k
19
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Darlington Amplifier circuit is constructed and it’s frequency response is plotted.
20
EXP. NO : 4 DATE:
DIFFERENTIALAMPLIFIER
Aim : To construct a Differential Amplifier circuit and to find its transfer Characteristics
and measure it’s CMRR.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 2KΩ,1 KΩ 1,2
3. Dual DC power supply 5 V 1
4. Function Generator 0 – 10MHz 1
5. CRO Dual channel,30MHz 1
6. Probes - 2
7. Breadboard - 1
8. Connecting Wires - Few
OVERVIEW :
The differential amplifier can be implemented using BJTs and is a commonly used building block
in analog IC design. The BJT implementation of the differential pair as emitter-coupled, common-emitter
(or emitter-resist or) amplifiers.
The simplest form of the differential amplifier is formed using two matched transistors (Q1and
Q2), in the E configuration whose emitters have been tied together. The differential pair has two inputs
(v1and v2), and three possible outputs (vo1, vo2, and vout). It is necessary that RE have a large value to keep
the voltage drop across it nearly constant with reasonable changes n current. It is absolutely imperative
however, that whatever is in the collector circuit ensures that Q1and Q2 never enter saturation.
For the differential mode operation the input is taken from two different sources and for the
common mode operation the applied signals are taken from the same source
Common Mode Rejection Ratio (CMRR) is an important parameter of the differential amplifier.
CMRR is defined as the ratio of the differential mode gain Ad to the common mode gain, Ac.In ideal cases,
the value of CMRR is very high.
21
SCHEMATIC REPRESENTATION WITH VALUES
MODEL GRAPH : Voltage transfer characteristic
0
0
00
Q19
Q2N2222
Q17
Q2N2222
R30
1k
R29
1k
R31
2k
V18
5V
V17
5V
V19 V20
22
CALCULATION OF CMRR
COMMON MODE GAIN
AC=VOUT/[(V1+V2)/2]
DIFFERENTIAL MODE GAIN
AD=VOUT/(V1-V2)
CMRR = | AD/AC |
TABULAR COLUMN
VOLTAGE TRANSFER CHARACTERISTICS
V1 (V) V2 (V) VO1 (V)
VO2 (V)
VID=V1-V2(V) VOD= VO1- VO2(V)
23
CMRR CALCULATION
MODES V1 (V) V2 (V) VO (V)
COMMON MODE
DIFFERENTIAL
MODE
PROCEDURE
1. Connections are given as per the circuit diagram.
2. To determine the common mode gain, set the input signal same at both inputs and
determine Vo at the collector terminals. Calculate common mode gain, from
AC=VOUT/[(V1+V2)/2]
3. To determine the differential mode gain, set the input signals with voltages V1 and V2 at
the two inputs. Find Vo at the collector terminals. Calculate differential mode gain, from
AD=VOUT/(V1-V2)
4. Calculate CMRR=AD/Ac.
5. For different values of input and the corresponding outputs in differential mode, the
voltage transfer characteristic graph is drawn.
RESULT:
Thus the Differential Amplifier circuit is constructed and it’s transfer characteristics
and CMRR are measured.
24
EXP. NO : 5 DATE:
CASCODE AMPLIFIER
Aim : To construct a Cascode Amplifier circuit and to plot it’s frequency response
characteristics.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 6.8KΩ,5.6KΩ,4.7KΩ1.1KΩ,1.8KΩ,1KΩ Each 1
3. Capacitors 10µF,5µF,20µF 1,2,1
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
The cascode is a two-stage amplifier composed of a trans conductance amplifier followed by a
current buffer.
Compared to a single amplifier stage, this combination may have one or more of the following
characteristics: higher input-output isolation, higher input impedance, high output impedance, higher gain
or higher bandwidth.
The cascode amplifier is constructed from two BJTs, with one operating as a common emitter and
the other as a common base. The cascode improves input-output isolation (or reverse transmission) as there
is no direct coupling from the output to input. This eliminates the Miller effect and thus contributes to a
much higher bandwidth.
25
SCHEMATIC REPRESENTATION WITH VALUES
0
0
0 R4
5.6k
R3
4.7kR2
1.1k
C2
20u
C4
5u
V2
Q2
Q2N2222
V1
18V
R6
1k
C1
10u
C3
5uQ1
Q2N2222
R1
1.8k
R5
6.8k
26
MODEL GRAPH :
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
27
Tabular Column: Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the Cascode Amplifier circuit is constructed and it’s frequency response is plotted.
28
EXP. NO : 6 DATE:
CASCADED AMPLIFIER
Aim : To construct a single stage and two -stage amplifier circuit and determine it’s
bandwidth.
Components Required :
S.NO COMPONENTS/EQUIPMENTS SPECIFICATION QUANTITY
1. Transistor 2N2222 2
2. Resistors 15KΩ,2.2KΩ,4.7KΩ1KΩ,10 KΩ 2,2,2,2,1
3. Capacitors 10µF,20µF 3,2
4. DC power supply 20 V 1
5. Function Generator 0 – 10MHz 1
6. CRO Dual channel,30MHz 1
7. Probes - 2
8. Breadboard - 1
9. Connecting Wires - Few
OVERVIEW :
When we want to achieve higher amplification than a single stage amplifier can offer, it is
a common practice to cascade various stages of amplifiers, as it is shown in Fig.1.a. In such a
structure the input performance of the resulted multistage amplifier is the input performance of the
first amplifier while the output performance is that of the last amplifier. The total voltage gain of
cascade connection is the product of the individual stage i.e. Av=Av1*Av2.But the bandwidth is
decreased. Hence there is a trade-off between the gain and bandwidth of the amplifier as the
number of stages is increased.
29
SCHEMATIC REPRESENTATION WITH VALUES
SINGLE STAGE AMPLIFIER
0
0
R28
10k
R24
2.2k
R26
15k
R20
4.7k
R22
1kC17
20u
C18
10uQ14
Q2N2222
V15
20V
C16
10u
V16
30
TWO-STAGE AMPLIFIER
MODEL GRAPH :
0
0
R18
10k
R16
15k
R15
15k
R14
2.2k
R131k
R12
1kR11
4.7kR10
4.7k
Q5
Q2N2222
Q4
Q2N2222
R17
2.2k
C8
10u
C7
20u
C6
10u
C10
10u
C9
20u
V5
20V
V6
31
PROCEDURE
1. Connect the circuit as shown in the circuit diagram.
2. Apply an input of 50mV peak-to-peak and 10 Hz frequency using function generator
3. Measure the output voltage Vo (p-p) for various values of frequencies.
4. Tabulate the readings in the tabular column.
5. The voltage gain can be calculated by using the expression 20*log(V0/Vi) in dB.
6. For plotting the frequency response the input voltage is kept constant at 50mV peak-to-
peak and the frequency is varied from 10Hz to 2MHz using function generator
7. Note down the value of output voltage for each frequency.
8. All the readings are tabulated and voltage gain in dB is calculated by using the expression
20 log10 (V0/Vi)
9. A graph is drawn by taking frequency on x-axis and gain in dB on y-axis on a semi-log
graph.
10. The bandwidth is calculated from the frequency response graph as BW=f2-f1.
Tabular Column:
SINGLE STAGE AMPLIFIER
Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
32
TWO-STAGE AMPLIFIER
Vi = _______ V
S.No.
Input signal
frequency in (Hz)
Output Voltage Vo
(volt)
Gain in db
=(20 log (Vo/Vi))
RESULT:
Thus the single stage and two -stage amplifier circuit is constructed and it’s frequency it’s
bandwidth is measured.
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EXP. NO : 7 DATE:
SIMULATION EXPERIMENT
COMMON EMITTER AMPLIFIER
Aim : To simulate a Common Emitter Amplifier in ORCAD PSPICE and to obtain it’s
frequency response characteristics.
SOFTWARE REQUIRED:
ORCAD PSPICE
SCHEMATIC REPRESENTATION WITH VALUES
0
0
R1
2.2kR2
910k
R4
1.2k
R5
220kC1
20u
C2
10uC3
5u
V1
15V
R6
1k
V2
Q1
Q2N2222
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OVERVIEW :
This type of biasing is otherwise called Emitter Biasing. The necessary biasing is provided
using 3 resistors: R1, R2 and RE. The resistors R1 and R2 act as a potential divider and give a
fixed voltage to the base. If the collector current increases due to change in temperature or change
in β, the emitter current IE also increases and the voltage drop across RE increases, reducing the
voltage difference between the base and the emitter. Due to reduction in VBE, base current IB and
hence collector current IC also reduces. This reduction in VBE, base current IB and hence collector
current IC also reduces. This reduction in the collector current compensates for the original change
in IC.
The stability factor S= (1+β) * ((1/ (1+β)). To have better stability, we must keep RB/RE
as small as possible. Hence the value of R1 R2 must be small. If the ratio RB/RE is kept fixed, S
increases with β.
MODEL GRAPH :
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PROCEDURE:
1. Select File >> New >> Project. Name your project and select the directory as the
location field. Be sure that you selected “Analog or Mixed A/D”.
2. Now, select “Create a blank project” at the appeared diagram box below
3. An empty page in Schematic Editor will be opened. Now draw the given circuit in the
Schematic Editor. To work your circuit properly, don’t forget to add Ground to your
circuit. Set the parameters as shown in the circuit above.
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37
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4. After the construction of the circuit, create a new profile using Pspice >> New
Simulation Profile from toolbar. Write a name in the New Simulation Name.
5. After clicking on the Create button, the following dialog box will appear. For frequency
response characteristics specify the type of analysis as ‘AC Sweep /Noise’. Since the
input frequency is varied , enter the start frequency as 20Hz and end frequency as
20KHz. Enter the total number of points per decade in the Points/Decade box
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6. Run your program by using toolbar as Pspice >> Run.
7. Another window will be opened and the frequency response characteristics will be