L A T E X TikZposter AN EW T RANSVERSE AND L ONGITUDINAL B UNCH BY B UNCH F EEDBACK P ROCESSOR M.G. Abbott, G. Rehm, I.S. Uzun 1 Diamond Light Source, Oxfordshire, UK 1 STFC, UK AN EW T RANSVERSE AND L ONGITUDINAL B UNCH BY B UNCH F EEDBACK P ROCESSOR M.G. Abbott, G. Rehm, I.S. Uzun 1 Diamond Light Source, Oxfordshire, UK 1 STFC, UK Abstract and Context Abstract We describe the development of firmware to support Longitudinal Bunch by Bunch Feedback at Diamond Light source. As well as feedback, the system supports complex experiments and the capture of detailed electron beam diagnostics. In this paper we describe the firmware development and some details of the processing chain. We focus on some of the challenges of FPGA development from the perspective of a software engineer. We are transitioning from Libera Bunch-by-Bunch platform (based on 15 year old Virtex-II Pro FPGA) to MicroTCA, which provides access to more up to date hardware. New Hardware Platform Here we see the chosen hardware platform, with a 500 MSPS ADC/DAC FMC card at top right, and a Virtex-7 690 FPGA under the heatsink at bottom left. FMC-500M High Pin Count FMC providing dual channel 500 MS/s 14-bit ADC and dual channel 1230 MS/s 16-bit DAC. This will support bunch-by-bunch operation at our machine RF frequency of 500 MHz. AMC525 Double width AMC card with two HPC FMC slots, 2 GB of fast on board DRAM and 128 MB of slower DRAM connected to a Virtex-7 690 FPGA, supporting an 8 lane gen3 PCIe connection over the MicroTCA backplane. This is where all the FPGA firmware will run, and the fast backplane connection will allow us to do a lot of data processing in the associated CPU. Data Processing Paths through Bunch-by-Bunch Processor ADC Bunch FIR DAC ADC OVF FIR MMS MEM 0 ÷N BB FIR ×N MEM 0 G G G + × MMS MEM 0 FIR DLY DAC sequencer bunch select detector ∼ NCO 1 ∼ NCO 0 MEM 1 This figure shows the data processing for a single LMBF/TMBF channel: OVF ADC input overflow detection (programmable threshold) FIR I/O compensation filter (8 tap FIR) MMS bunch position and motion measurement, measures min/max/sum and sum of squares ÷N bunch by bunch decimation (average over programmable count) BB FIR bunch by bunch filter (8 tap FIR per bunch) ×N bunch by bunch interpolation G gain control (scale by power of 2) DLY output alignment delay ∼ controllable oscillator (NCO) Overflow detection and saturation is implemented at each point where overflow can occur. Overview of Implementation interconnect axi burst master axi lite slave axi lite master register top system registers clocking dsp main fmc500m PLL ADC DAC ADC in DAC out f RF f REV idelay 125 MHz TRG PM BLK SEQ 0 SEQ 1 fmc digital io REF CLK REG CLK DSP CLK ADC CLK PCIe DRAM0 2 GB DRAM1 128 MB DRAM1 128 MB 100 MHz fmc500m idelay interrupts ADC (×2) DAC (×2) TRG/PM/BLK SEQ 0/1 PCIe DSP int DMA DSP DRAM DRAM DMA PCIe MGT PCIe DSP DMA interrupt control DRAM DSP register interface adc sequencer ADC bunch fir FIR bunch select BNCH nco 0 NCO 0 nco 1 NCO 1 dac DAC detector ADC in DAC out adc event nco 1 gain nco 1 gain trigger blanking window window start/write start/write SEQ DRAM 1 turn clock T registers R R T R T R T R T R T R T R Overview of top level FPGA design. The “interconnect” at the top connects to all of the hardware resources provided by the AMC525 carrier card, including 8-lane PCIe and 2 GB of fast DRAM. The rest of the this figure shows connections to the FMC cards, clocking and control, and the data processing core “dsp main”. Overview of data processing implementation for a single channel. The symbol ADC represents points were data is interchanged with the other channel depending on whether TMBF or LMBF mode has been selected.