a Complete 12-Bit, 65 MSPS ADC Converter AD9226

REV. B

Information furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Devices.

a

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700 World Wide Web Site: http://www.analog.com

Fax: 781/326-8703 © Analog Devices, Inc., 2001

AD9226

Complete 12-Bit, 65 MSPSADC Converter

FUNCTIONAL BLOCK DIAGRAM

VINA

CAPT

CAPB

SENSE

OTRBIT 1(MSB)BIT 12(LSB)

VREF

DRVSSAVSS

AD9226

SHA

CORRECTION LOGIC

OUTPUT BUFFERS

VINB

1V

REFCOM

416 3

12

DRVDDAVDDCLK

MODESELECT

MDAC1 A/D

A/D

8-STAGE1-1/2-BIT PIPELINE

MODE

REFSELECT

CALIBRATIONROM

DUTY CYCLE STABILIZER

FEATURES

Signal-to-Noise Ratio: 69 dB @ fIN = 31 MHz

Spurious-Free Dynamic Range: 85 dB @ fIN = 31 MHz

Intermodulation Distortion of –75 dBFS @ fIN = 140 MHz

ENOB = 11.1 @ fIN = 10 MHz

Low-Power Dissipation: 475 mW

No Missing Codes Guaranteed

Differential Nonlinearity Error: 0.6 LSB

Integral Nonlinearity Error: 0.6 LSB

Clock Duty Cycle Stabilizer

Patented On-Chip Sample-and-Hold with

Full Power Bandwidth of 750 MHz

Straight Binary or Two’s Complement Output Data

28-Lead SSOP, 48-Lead LQFP

Single 5 V Analog Supply, 3 V/5 V Driver Supply

Pin-Compatible to AD9220, AD9221, AD9223,

AD9224, AD9225

PRODUCT DESCRIPTIONThe AD9226 is a monolithic, single-supply, 12-bit, 65 MSPSanalog-to-digital converter with an on-chip, high-performancesample-and-hold amplifier and voltage reference. The AD9226uses a multistage differential pipelined architecture with a pat-ented input stage and output error correction logic to provide12-bit accuracy at 65 MSPS data rates. There are no missingcodes over the full operating temperature range (guaranteed).

The input of the AD9226 allows for easy interfacing to bothimaging and communications systems. With a truly differentialinput structure, the user can select a variety of input ranges andoffsets including single-ended applications.

The sample-and-hold amplifier (SHA) is well suited for IFundersampling schemes such as in single-channel communi-cation applications with input frequencies up to and wellbeyond Nyquist frequencies.

The AD9226 has an on-board programmable reference. For sys-tem design flexibility, an external reference can also be chosen.

A single clock input is used to control all internal conversioncycles. An out-of-range signal indicates an overflow conditionthat can be used with the most significant bit to determine lowor high overflow.

The AD9226 has two important mode functions. One will setthe data format to binary or two’s complement. The second willmake the ADC immune to clock duty cycle variations.

PRODUCT HIGHLIGHTSIF Sampling—The patented SHA input can be configured foreither single-ended or differential inputs. It will maintain out-standing AC performance up to input frequencies of 300 MHz.

Low Power—The AD9226 at 475 mW consumes a fraction ofthe power presently available in existing, high-speed monolithicsolutions.

Out of Range (OTR)—The OTR output bit indicates whenthe input signal is beyond the AD9226’s input range.

Single Supply—The AD9226 uses a single 5 V power supplysimplifying system power supply design. It also features a sepa-rate digital output driver supply line to accommodate 3 V and5 V logic families.

Pin Compatibility—The AD9226 is similar to the AD9220,AD9221, AD9223, AD9224, and AD9225 ADCs.

Clock Duty Cycle Stabilizer—Makes conversion immune tovarying clock pulsewidths.

AD9226* PRODUCT PAGE QUICK LINKSLast Content Update: 02/23/2017

COMPARABLE PARTSView a parametric search of comparable parts.

DOCUMENTATIONApplication Notes

• AN-1142: Techniques for High Speed ADC PCB Layout

• AN-282: Fundamentals of Sampled Data Systems

• AN-302: Exploit Digital Advantages in an SSB Receiver

• AN-345: Grounding for Low-and-High-Frequency Circuits

• AN-348: Avoiding Passive-Component Pitfalls

• AN-501: Aperture Uncertainty and ADC System Performance

• AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated

• AN-737: How ADIsimADC Models an ADC

• AN-741: Little Known Characteristics of Phase Noise

• AN-742: Frequency Domain Response of Switched-Capacitor ADCs

• AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter

• AN-807: Multicarrier WCDMA Feasibility

• AN-808: Multicarrier CDMA2000 Feasibility

• AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs

• AN-835: Understanding High Speed ADC Testing and Evaluation

• AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual

• AN-935: Designing an ADC Transformer-Coupled Front End

Data Sheet

• AD9226: Complete 12-Bit, 65 MSPS ADC Converter Data Sheet

User Guides

• UG-173: High Speed ADC USB FIFO Evaluation Kit (HSC-ADC-EVALB-DCZ)

TOOLS AND SIMULATIONS• Visual Analog

REFERENCE MATERIALSTechnical Articles

• Correlating High-Speed ADC Performance to Multicarrier 3G Requirements

• DNL and Some of its Effects on Converter Performance

• MS-2210: Designing Power Supplies for High Speed ADC

DESIGN RESOURCES• AD9226 Material Declaration

• PCN-PDN Information

• Quality And Reliability

• Symbols and Footprints

DISCUSSIONSView all AD9226 EngineerZone Discussions.

SAMPLE AND BUYVisit the product page to see pricing options.

TECHNICAL SUPPORTSubmit a technical question or find your regional support number.

DOCUMENT FEEDBACKSubmit feedback for this data sheet.

This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.

REV. B–2–

AD9226–SPECIFICATIONS(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, Differential inputs, TMIN to TMAX unless otherwisenoted.)DC SPECIFICATIONS

Parameter Temp Test Level Min Typ Max Unit

RESOLUTION 12 Bits

ACCURACYIntegral Nonlinearity (INL) Full V ±0.6 LSB

25°C I ±1.6 LSBDifferential Nonlinearity (DNL) Full V ±0.6 LSB

25°C I ±1.0 LSBNo Missing Codes Guaranteed Full I 12 BitsZero Error Full V ±0.3 % FSR

25°C I ±1.4 % FSRGain Error 25°C I ±2.0 % FSR

Full V ±0.6 % FSR

TEMPERATURE DRIFTZero Error Full V ± 2 ppm/°CGain Error1 Full V ±26 ppm/°CGain Error2 Full V ±0.4 ppm/°C

POWER SUPPLY REJECTIONAVDD (5 V ± 0.25 V) Full V ±0.05 % FSR

25°C I ±0.4 % FSR

INPUT REFERRED NOISEVREF = 1.0 V Full V 0.5 LSB rmsVREF = 2.0 V Full V 0.25 LSB rms

ANALOG INPUTInput Span (VREF = 1 V) Full V 1 V p-p

(VREF = 2 V) Full V 2 V p-pInput (VINA or VINB) Range Full IV 0 AVDD VInput Capacitance Full V 7 pF

INTERNAL VOLTAGE REFERENCEOutput Voltage (1 V Mode) Full V 1.0 VOutput Voltage Tolerance (1 V Mode) 25°C I ±15 mVOutput Voltage (2.0 V Mode) Full V 2.0 VOutput Voltage Tolerance (2.0 V Mode) 25°C I ±29 mVOutput Current (Available for External Loads) Full V 1.0 mALoad Regulation3 Full V 0.7 mV

25°C I 1.5 mV

REFERENCE INPUT RESISTANCE Full V 5 kΩ

POWER SUPPLIESSupply Voltages

AVDD Full V 4.75 5 5.25 V (±5% AVDD Operating)DRVDD Full V 2.85 5.25 V (±5% DRVDD Operating)

Supply CurrentIAVDD4 Full V 86 mA (2 V External VREF)

25°C I 90.5 mA (2 V External VREF)IDRVDD5 Full V 14.6 mA (2 V External VREF)

25°C I 16.5 mA (2 V External VREF)

POWER CONSUMPTION4, 5 Full V 47525°C I 500 mW (2 V External VREF)

NOTES1Includes internal voltage reference error.2Excludes internal voltage reference error.3Load regulation with 1 mA load current (in addition to that required by the AD9226).4AVDD = 5 V5DRVDD = 3 V

Specifications subject to change without notice.

REV. B –3–

AD9226

DIGITAL SPECIFICATIONSParameters Temp Test Level Min Typ Max Unit

LOGIC INPUTS (Clock, DFS1, Duty Cycle1, andOutput Enable1)

High-Level Input Voltage Full IV 2.4 VLow-Level Input Voltage Full IV 0.8 VHigh-Level Input Current (VIN = AVDD) Full IV –10 +10 µALow-Level Input Current (VIN = 0 V) Full IV –10 +10 µAInput Capacitance Full V 5 pFOutput Enable1 Full IV V

LOGIC OUTPUTS (With DRVDD = 5 V)High-Level Output Voltage (IOH = 50 µA) Full IV 4.5 VHigh-Level Output Voltage (IOH = 0.5 mA) Full IV 2.4 VLow-Level Output Voltage (IOL = 1.6 mA) Full IV 0.4 VLow-Level Output Voltage (IOL = 50 µA) Full IV 0.1 VOutput Capacitance 5 pF

LOGIC OUTPUTS (With DRVDD = 3 V)High-Level Output Voltage (IOH = 50 µA) Full IV 2.95 VHigh-Level Output Voltage (IOH = 0.5 mA) Full IV 2.80 VLow-Level Output Voltage (IOL = 1.6 mA) Full IV 0.4 VLow-Level Output Voltage (IOL = 50 µA) Full IV 0.05 V

NOTES1LQFP package.

Specifications subject to change without notice.

SWITCHING SPECIFICATIONSParameters Temp Test Level Min Typ Max Unit

Max Conversion Rate Full VI 65 MHzClock Period1 Full V 15.38 nsCLOCK Pulsewidth High2 Full V 3 nsCLOCK Pulsewidth Low2 Full V 3 nsOutput Delay Full V 3.5 7 nsPipeline Delay (Latency) Full V 7 Clock CyclesOutput Enable Delay3 Full V 15 ns

NOTES1The clock period may be extended to 10 µs without degradation in specified performance @ 25°C.2When MODE pin is tied to AVDD or grounded, the AD9226 SSOP is not affected by clock duty cycle.3LQFP package.

Specifications subject to change without notice.

(AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, unless otherwise noted.)

(TMIN to TMAX with AVDD = 5 V, DRVDD = 3 V, CL = 20 pF)

n+1 n+2n+3

n+4

n+5n+6

n+7

n+8nANALOG

INPUT

CLOCK

DATAOUT

n–8 n–7 n–6 n–5 n–4 n–3 n–2 n+1nn–1

TOD = 7.0 MAX3.5 MIN

Figure 1. Timing Diagram

DRVDD2

0 5– .

DRVDD2

0 5+ .

REV. B–4–

AD9226–SPECIFICATIONSAC SPECIFICATIONS (AVDD = 5 V, DRVDD = 3 V, fSAMPLE = 65 MSPS, VREF = 2.0 V, TMIN to TMAX, Differential Input unless otherwise noted.)

Parameter Temp Test Level Min Typ Max Unit

SIGNAL-TO-NOISE RATIOfIN = 2.5 MHz Full V 68.9 dBc

25°C I 68 dBcfIN = 15 MHz Full V 68.4 dBc

25°C I 67.4 dBcfIN = 31 MHz Full V 68 dBcfIN = 60 MHz Full V 68 dBcfIN = 200 MHz1 Full V 65 dBc

SIGNAL-TO-NOISE RATIO AND DISTORTIONfIN = 2.5 MHz Full V 68.8 dBc

25°C I 67.9 dBcfIN = 15 MHz Full V 68.3 dBc

25°C I 67.3 dBcfIN = 31 MHz Full V 67 dBcfIN = 60 MHz Full V 67 dBcfIN = 200 MHz1 Full V 60 dBc

TOTAL HARMONIC DISTORTIONfIN = 2.5 MHz Full V –84 dBc

25°C I –77.0 dBcfIN = 15 MHz Full V –82.3 dBc

25°C I –76.0 dBcfIN = 31 MHz Full V –68 dBcfIN = 60 MHz Full V –68 dBcfIN = 200 MHz1 Full V –61 dBc

SECOND AND THIRD HARMONIC DISTORTIONfIN = 2.5 MHz Full V –86.5 dBc

25°C I –78 dBcfIN = 15 MHz Full V –86.7 dBc

25°C I –76 dBcfIN = 31 MHz Full V –83 dBcfIN = 60 MHz Full V –82 dBcfIN = 200 MHz1 Full V –75 dBc

SPURIOUS FREE DYNAMIC RANGEfIN = 2.5 MHz Full V 86.4 dBc

25°C I 78 dBcfIN = 15 MHz Full V 85.5 dBc

25°C I 76 dBcfIN = 31 MHz Full V 82 dBcfIN = 60 MHz Full V 81 dBcfIN = 200 MHz1 Full V 60 dBc

ANALOG INPUT BANDWIDTH 25°C V 750 MHz

NOTES11.0 V Reference and Input Span

Specifications subject to change without notice.

REV. B

AD9226

–5–

CAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without detection. Althoughthe AD9226 features proprietary ESD protection circuitry, permanent damage may occur ondevices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions arerecommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS1

WithPin Name Respect to Min Max Unit

AVDD AVSS –0.3 +6.5 VDRVDD DRVSS –0.3 +6.5 VAVSS DRVSS –0.3 +0.3 VAVDD DRVDD –6.5 +6.5 VREFCOM AVSS –0.3 +0.3 VCLK, MODE AVSS –0.3 AVDD + 0.3 VDigital Outputs DRVSS –0.3 DRVDD + 0.3 VVINA, VINB AVSS –0.3 AVDD + 0.3 VVREF AVSS –0.3 AVDD + 0.3 VSENSE AVSS –0.3 AVDD + 0.3 VCAPB, CAPT AVSS –0.3 AVDD + 0.3 VOEB2 DRVSS –0.3 DRVDD + 0.3 VCM LEVEL2 AVSS –0.3 AVDD + 0.3 VVR2 AVSS –0.3 AVDD + 0.3 VJunction Temperature 150 °CStorage Temperature –65 +150 °CLead Temperature (10 sec) 300 °CNOTES1Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingsfor extended periods may affect device reliability.

2LQFP package.

EXPLANATION OF TEST LEVELSTest LevelI. 100% production tested.

II. 100% production tested at 25°C and sample tested atspecified temperatures. AC testing done on sample basis.

III. Sample tested only.

IV. Parameter is guaranteed by design and characterizationtesting.

V. Parameter is a typical value only.

VI. All devices are 100% production tested at 25°C; sample testedat temperature extremes.

THERMAL RESISTANCEθJC SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23°C/WθJA SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63.3°C/WθJC LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17°C/WθJA LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76.2°C/W

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9226ARS –40°C to +85°C 28-Lead Shrink Small Outline (SSOP) RS-28AD9226AST –40°C to +85°C 48-Lead Thin Plastic Quad Flatpack (LQFP) ST-48AD9226-EB Evaluation Board (SSOP)AD9226-LQFP-EB Evaluation Board (LQFP)

REV. B

AD9226

–6–

48-PIN FUNCTION DESCRIPTIONS

PinNumber Name Description

1, 2, 32, 33 AVSS Analog Ground3, 4, 31, 34 AVDD 5 V Analog Supply5, 6, 8, 10, NC No Connect11, 447 CLK Clock Input Pin9 OEB Output Enable (Active Low)12 BIT 12 Least Significant Data Bit (LSB)13 BIT 11 Data Output Bit14, 22, 30 DRVSS Digital Output Driver Ground15, 23, 29 DRVDD 3 V to 5 V Digital Output

Driver Supply16–21, BITS 10–5, Data Output Bits24–26 BITS 4–227 BIT 1 Most Significant Data Bit (MSB)28 OTR Out of Range35 MODE2 Data Format Select36 SENSE Reference Select37 VREF Reference In/Out38 REFCOM Reference Common

(AVSS)39, 40 CAPB Noise Reduction Pin41, 42 CAPT Noise Reduction Pin43 MODE1 Clock Stabilizer45 CM LEVEL Midsupply Reference46 VINA Analog Input Pin (+)47 VINB Analog Input Pin (–)48 VR Noise Reduction Pin

PIN CONNECTION28-Lead SSOP

TOP VIEW(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD9226

OTR

(MSB) BIT 1

BIT 2

BIT 3

BIT 4

BIT 5

BIT 6

CLK

(LSB) BIT 12

BIT 11

BIT 10

BIT 7

BIT 8

BIT 9

AVDD

AVSS

SENSE

VREF

REFCOM (AVSS)

CAPB

CAPT

DRVDD

DRVSS

AVDD

AVSS

MODE

VINA

VINB

PIN CONNECTION48-Lead LQFP

36

35

34

33

32

31

30

29

28

27

26

25

13 14 15 16 17 18 19 20 21 22 23 24

1

2

3

4

5

6

7

8

9

10

11

12

48 47 46 45 44 39 38 3743 42 41 40

PIN 1IDENTIFIER

TOP VIEW(Not to Scale)

SENSE

MODE2AVDD

AVSS

AVSS

AVDD

DRVSS

AVSS

AVSSAVDD

AVDD

NC

NC

CLK

NC = NO CONNECT

NC

OEBNC

NC

DRVDD

OTRBIT 1 (MSB)

BIT 2

AD9226

(LSB) BIT 12 BIT 3

VR

VIN

B

VIN

A

CM

LE

VE

L

NC

MO

DE

1

CA

PT

CA

PT

CA

PB

CA

PB

RE

F C

OM

(A

VS

S)

VR

EF

BIT

11

DR

VS

S

DR

VD

DB

IT 1

0

BIT

9

BIT

8

BIT

7

BIT

6

BIT

5

DR

VS

S

DR

VD

DB

IT 4

28-PIN FUNCTION DESCRIPTIONS

PinNumber Name Description

1 CLK Clock Input Pin2 BIT 12 Least Significant Data Bit (LSB)3–12 BITS 11–2 Data Output Bits13 BIT 1 Most Significant Data Bit (MSB)14 OTR Out of Range15, 26 AVDD 5 V Analog Supply16, 25 AVSS Analog Ground17 SENSE Reference Select18 VREF Input Span Select (Reference I/O)19 REFCOM Reference Common

(AVSS)20 CAPB Noise Reduction Pin21 CAPT Noise Reduction Pin22 MODE Data Format Select /Clock Stabilizer23 VINA Analog Input Pin (+)24 VINB Analog Input Pin (–)27 DRVSS Digital Output Driver Ground28 DRVDD 3 V to 5 V Digital Output

Driver Supply

REV. B

AD9226

–7–

DEFINITIONS OF SPECIFICATIONSINTEGRAL NONLINEARITY (INL)INL refers to the deviation of each individual code from a linedrawn from “negative full scale” through “positive full scale.”The point used as “negative full scale” occurs 1/2 LSB beforethe first code transition. “Positive full scale” is defined as a level1 1/2 LSB beyond the last code transition. The deviation ismeasured from the middle of each particular code to the truestraight line.

DIFFERENTIAL NONLINEARITY (DNL, NO MISSINGCODES)An ideal ADC exhibits code transitions that are exactly 1 LSBapart. DNL is the deviation from this ideal value. Guaranteedno missing codes to 12-bit resolution indicates that all 4096codes, respectively, must be present over all operating ranges.

ZERO ERRORThe major carry transition should occur for an analog value1/2 LSB below VINA = VINB. Zero error is defined as thedeviation of the actual transition from that point.

GAIN ERRORThe first code transition should occur at an analog value1/2 LSB above negative full scale. The last transition shouldoccur at an analog value 1 1/2 LSB below the positive full scale.Gain error is the deviation of the actual difference between firstand last code transitions and the ideal difference between firstand last code transitions.

TEMPERATURE DRIFTThe temperature drift for zero error and gain error specifies themaximum change from the initial (25°C) value to the value atTMIN or TMAX.

POWER SUPPLY REJECTIONThe specification shows the maximum change in full scale fromthe value with the supply at the minimum limit to the value withthe supply at its maximum limit.

APERTURE JITTERAperture jitter is the variation in aperture delay for successivesamples and can be manifested as noise on the input to the ADC.

APERTURE DELAYAperture delay is a measure of the sample-and-hold amplifier(SHA) performance and is measured from the rising edge of theclock input to when the input signal is held for conversion.

SIGNAL-TO-NOISE AND DISTORTION (S/N+D, SINAD)RATIOS/N+D is the ratio of the rms value of the measured inputsignal to the rms sum of all other spectral components belowthe Nyquist frequency, including harmonics but excluding dc.The value for S/N+D is expressed in decibels.

EFFECTIVE NUMBER OF BITS (ENOB)For a sine wave, SINAD can be expressed in terms of the num-ber of bits. Using the following formula,

N = (SINAD – 1.76)/6.02

it is possible to obtain a measure of performance expressed asN, the effective number of bits.

Thus, effective number of bits for a device for sine wave inputsat a given input frequency can be calculated directly from itsmeasured SINAD.

TOTAL HARMONIC DISTORTION (THD)THD is the ratio of the rms sum of the first six harmonic com-ponents to the rms value of the measured input signal and isexpressed as a percentage or in decibels.

SIGNAL-TO-NOISE RATIO (SNR)SNR is the ratio of the rms value of the measured input signal tothe rms sum of all other spectral components below the Nyquistfrequency, excluding the first six harmonics and dc. The valuefor SNR is expressed in decibels.

SPURIOUS FREE DYNAMIC RANGE (SFDR)SFDR is the difference in dB between the rms amplitude of theinput signal and the peak spurious signal.

ENCODE PULSEWIDTH DUTY CYCLEPulsewidth high is the minimum amount of time that the clockpulse should be left in the logic “1” state to achieve rated per-formance; pulsewidth low is the minimum time the clock pulseshould be left in the low state. At a given clock rate, these specsdefine an acceptable clock duty cycle.

MINIMUM CONVERSION RATEThe clock rate at which the SNR of the lowest analog signalfrequency drops by no more than 3 dB below the guaranteed limit.

MAXIMUM CONVERSION RATEThe encode rate at which parametric testing is performed.

OUTPUT PROPAGATION DELAYThe delay between the clock logic threshold and the time whenall bits are within valid logic levels.

TWO TONE SFDRThe ratio of the rms value of either input tone to the rms valueof the peak spurious component. The peak spurious componentmay or may not be an IMD product. May be reported in dBc(i.e., degrades as signal levels are lowered) or in dBFS (alwaysrelated back to converter full scale).

REV. B

AD9226

–8–

DRVDD

DRVSS

DRVDD

DRVSS

DRVDD

AVSS

AVDD

AVSS

AVDD

AVDD

AVSS

Figure 2. Equivalent Circuits

a. D0–D11, OTR b. Three-State (OEB) c. CLK

d. AIN e. CAPT, CAPB, MODE, SENSE, VREF

REV. B

FREQUENCY – MHz

0

dB

FS

–120

–100

–80

–60

–40

–20

0 32.56.5 13 19.5 26

–110

–90

–70

–50

–30

–10 SNR = 69.9dBcSINAD = 69.8dBcENOB = 11.4BITSTHD = –86.4dBcSFDR = 88.7dBc

TPC 1. Single-Tone 8K FFT with fIN = 5 MHz

FREQUENCY – MHz

0

dB

FS

–120

–100

–80

–60

–40

–20

0 32.56.5 13 19.5 26

–110

–90

–70

–50

–30

–10 SNR = 70.4dBFSSFDR = 87.5dBFS

TPC 2. Dual-Tone 8K FFT with fIN–1 = 18 MHz andfIN–2 = 20 MHz (AIN–1 = AIN–2 = –6.5 dBFS)

FREQUENCY – MHz

0

dB

FS

–120

–100

–80

–60

–40

–20

0 32.56.5 13 19.5 26

–110

–90

–70

–50

–30

–10 SNR = 69.5dBcSINAD = 69.4dBcENOB = 11.3BITSTHD = –85dBcSFDR = 87.6dBc

TPC 3. Single-Tone 8K FFT with fIN = 31 MHz

(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25C, 2 V Differential Input Span, VCM = 2.5 V, AIN = –0.5 dBFS,VREF = 2.0 V, unless otherwise noted.)

Typical Performance Characteristics–AD9226

–9–

SNR – dBFSSFDR – dBc

SFDR – dBFS

SNR – dBc

100

80

60

40

AIN – dBFS

dB

FS

AN

D d

Bc

–30 –25 –20 –15 –10 0–5

50

70

90

TPC 4. Single-Tone SNR/SFDR vs. AIN with fIN = 5 MHz

SNR – dBFS

SFDR – dBc

SNR – dBc

100

80

60

40

dB

FS

AN

D d

Bc

50

70

90

AIN – dBFS

–30 –25 –20 –15 –10 0–5

SFDR – dBFS

TPC 5. Dual-Tone SNR/SFDR vs. AIN with fIN–1 = 18 MHzand fIN–2 = 20 MHz

100

80

60

40

AIN – dBFS

dB

FS

AN

D d

Bc

–30 –25 –20 –15 –10 0–5

50

70

90

SNR – dBFS

SFDR – dBc

SFDR – dBFS

SNR – dBc

TPC 6. Single-Tone SNR/SFDR vs. AIN with fIN = 31 MHz

REV. B

AD9226

–10–

FREQUENCY – MHz

451 1000

SIN

AD

– d

Bc

10010

50

55

60

65

75

70

7.3

8.1

8.9

9.8

10.6

11.4

12.2

EN

OB

– B

its

2V SPAN, DIFFERENTIAL

1V SPAN,DIFFERENTIAL

2V SPAN, SINGLE-ENDED

1V SPAN,SINGLE-ENDED

TPC 7. SINAD/ENOB vs. Frequency

FREQUENCY – MHz1 1000

TH

D –

dB

c

10010

–45

–50

–55

–60

–65

–70

–75

–80

–85

–90

2V SPAN,DIFFERENTIAL

1V SPAN,DIFFERENTIAL

1V SPAN,SINGLE-ENDED

2V SPAN, SINGLE-ENDED

TPC 8. THD vs. Frequency

FREQUENCY – MHz1 1000

SN

R –

dB

c

1001062

64

66

72

70

68+85C

+25C–40C

TPC 9. SNR vs. Temperature and Frequency

FREQUENCY – MHz

611 1000

SN

R –

dB

c

10010

62

64

66

68

71

70

69

67

65

63

2V SPAN, DIFFERENTIAL

1V SPAN,DIFFERENTIAL

1V SPAN,SINGLE-ENDED

2V SPAN, SINGLE-ENDED

TPC 10. SNR vs. Frequency

FREQUENCY – MHz

451 1000

SF

DR

– d

Bc

10010

50

60

70

80

95

90

85

75

65

55

2V SPAN,DIFFERENTIAL

1V SPAN,DIFFERENTIAL

1V SPAN,SINGLE-ENDED

2V SPAN, SINGLE-ENDED

TPC 11. SFDR vs. Frequency

TH

D –

dB

c

–72

–74

–76

–78

–80

–82

–84

–86

–88

–90

–70

FREQUENCY – MHz1 10010

+85C

+25C

–40C

TPC 12. THD vs. Temperature and Frequency

REV. B

AD9226

–11–

FREQUENCY – MHz1 1000

HA

RM

ON

ICS

– d

Bc

1001055

65

75

105

95

85

4th HARMONIC

3RD HARMONIC

2ND HARMONIC

TPC 13. Harmonics vs. Frequency

100

90

85

95

SAMPLE RATE – MSPS10 20 30 40 50 7060

SF

DR

– d

Bc

80

fIN = 2MHz

fIN = 12MHz

fIN = 20MHz

TPC 14. SFDR vs. Sample Rate

CODE4000

INL

– L

SB

1.0

0.8

0.6

0.4

0.2

0.0

–0.2

–0.4

–0.6

–0.8

–1.03500300025002000150010005000

TPC 15. Typical INL

70.5

70

69.5

69

69.25

69.75

70.25

SAMPLE RATE – MSPS10 20 30 40 50 7060

SIN

AD

– d

Bc

fIN = 2MHz

fIN = 12MHz

fIN = 20MHz

TPC 16. SINAD vs. Sample Rate

% POSITIVE DUTY CYCLE

30 45

SIN

AD

/SF

DR

– d

Bc

35 50 55 7045

50

55

60

65

70

75

80

85

90

40 60 65

SFDR – CLOCK STABILIZER ON

SINAD – CLOCK STABILIZER ON

SFDR – CLOCK STABILIZER OFF

SINAD – CLOCK STABILIZER OFF

TPC 17. SINAD/SFDR vs. Duty Cycle @ fIN = 20 MHz

CODE

1

0

–10

DN

L –

LS

B

500 1k 1500 2k 2500 3k 3500 4k

–0.8

–0.6

–0.4

–0.2

0.2

0.4

0.6

0.8

TPC 18. Typical DNL

REV. B

AD9226

–12– REV. B

FREQUENCY – MHz

0

dB

FS

–80

–60

–40

–20

0 244 12 16 20

–90

–70

–50

–30

–10

8 28 32–120

–100

–110

SNR = 70.2dBFSSFDR = 89dBFSNOISE FLOOR = 145.33dBFS/Hz

TPC 19. Dual-Tone 8K FFT with fIN–1 = 44.2 MHz andfIN–2 = 45.6 MHz

FREQUENCY – MHz

0

dB

FS

–80

–60

–40

–20

0 244 12 16 20

–90

–70

–50

–30

–10

8 28 32–120

–100

–110

SNR = 68.5dBFSSFDR = 75dBFSNOISE FLOOR = 143.6dBFS/Hz

TPC 20. Dual-Tone 8K FFT with fIN–1 = 69.2 MHz andfIN–2 = 70.6 MHz

FREQUENCY – MHz

0

dB

FS

–80

–60

–40

–20

0 244 12 16 20

–90

–70

–50

–30

–10

8 28 32–120

–100

–110

SNR = 67.5dBFSSFDR = 75dBFSNOISE FLOOR = 142.6dBFS/Hz

TPC 21. Dual-Tone 8K FFT with fIN–1 = 139.2 MHz andfIN–2 = 140.7 MHz

AD9226–Typical IF Sampling Performance Characteristics

–12–

(AVDD = 5.0 V, DRVDD = 3.0 V, fSAMPLE = 65 MSPS with CLK Stabilizer Enabled, TA = 25C, 2 V Differential Input Span, VCM = 2.5 V, AIN = –6.5 dBFS,VREF = 2.0 V, unless otherwise noted.)

AIN – dBFS

–24

SN

R/S

FD

R –

dB

FS

–2165

70

75

95

80

85

90

–18 –15 –12 –9 –6

SNR/NOISE FLOOR – 2V SPAN

SFDR – 2V SPAN

NO

ISE

FL

OO

R –

dB

FS

/Hz

140.1

145.1

150.1

170.1

155.1

160.1

165.1

TPC 22. Dual-Tone SNR and SFDR with fIN–1 = 44.2 MHzand fIN–2 = 45.6 MHz

AIN – dBFS

–24

SN

R/S

FD

R –

dB

FS

–2160

65

70

90

75

80

85

–18 –15 –12 –9 –6

NO

ISE

FL

OO

R –

dB

FS

/Hz

135.1

140.1

145.1

165.1

150.1

155.1

160.1

SNR/NOISE FLOOR – 1V SPAN

SFDR – 2V SPAN

SNR/NOISE FLOOR – 2V SPAN

SFDR – 1V SPAN

TPC 23. Dual-Tone SNR and SFDR with fIN–1 = 69.2 MHzand fIN–2 = 70.6 MHz

AIN – dBFS–24

SN

R/S

FD

R –

dB

FS

–2160

65

70

90

75

80

85

–18 –15 –12 –9 –6

NO

ISE

FL

OO

R –

dB

FS

/Hz

135.1

140.1

145.1

165.1

150.1

155.1

160.1

SNR/NOISE FLOOR – 1V SPAN

SFDR – 2V SPAN

SNR/NOISE FLOOR – 2V SPAN

SFDR – 1V SPAN

TPC 24. Dual-Tone SNR and SFDR with fIN–1 = 139.2 MHzand fIN–2 = 140.7 MHz

REV. B

AD9226

–13–

FREQUENCY – MHz

0d

BF

S

–80

–60

–40

–20

0 255 15 20

–90

–70

–50

–30

–10

10 30–120

–100

–110

fIN = 190.82MHzfSAMPLE = 61.44MSPS

TPC 25. Single-Tone 8K FFT at IF = 190 MHz–WCDMA(fIN = 190.82 MHz, fSAMPLE = 61.44 MSPS)

FREQUENCY – MHz

0

dB

FS

–80

–60

–40

–20

0 244 12 16 20

–90

–70

–50

–30

–10

8 28 32–120

–100

–110

SNR = 65.1dBFSSFDR = 59dBFSNOISE FLOOR = 140.2dBFS/Hz

TPC 26. Dual-Tone 8K FFT with fIN–1 = 239.1 MHz andfIN–2 = 240.7 MHz

FREQUENCY – MHz1 1000

CM

RR

– d

Bc

10010–95

–85

–75

–65

–55

–45

–35

INPUT SPAN = 2V p–p

INPUT SPAN = 1V p–p

TPC 27. CMRR vs. Frequency (AIN = –0 dBFS andCML = 2.5 V)

AIN – dBFS

–24

SN

R/S

FD

R –

dB

FS

–2160

65

70

90

75

80

85

–18 –15 –12 –9 –6

NO

ISE

FL

OO

R –

dB

FS

/Hz

135.1

140.1

145.1

165.1

150.1

155.1

160.1

SNR/NOISE FLOOR – 1V SPAN

SFDR – 2V SPAN

SNR/NOISE FLOOR – 2V SPAN

SFDR – 1V SPAN

TPC 28. Single-Tone SNR and SFDR vs. AIN at IF = 190 MHz–WCDMA (fIN–1 = 190.8 MHz, fSAMPLE = 61.44 MSPS)

AIN – dBFS–24

SN

R/S

FD

R –

dB

FS

–2155

60

65

85

70

75

80

–18 –15 –12 –9 –6

NO

ISE

FL

OO

R –

dB

FS

/Hz

130.1

135.1

140.1

160.1

145.1

150.1

155.1

SNR/NOISE FLOOR – 1V SPAN

SFDR – 2V SPAN

SNR/NOISE FLOOR – 2V SPAN

SFDR – 1V SPAN

TPC 29. Dual-Tone SNR and SFDR with fIN–1 = 239.1 MHzand fIN–2 = 240.7 MHz

REV. B

AD9226

–14–

THEORY OF OPERATIONThe AD9226 is a high-performance, single-supply 12-bit ADC.The analog input of the AD9226 is very flexible allowing for bothsingle-ended or differential inputs of varying amplitudes that canbe ac- or dc-coupled.

It utilizes a nine-stage pipeline architecture with a wideband,sample-and-hold amplifier (SHA) implemented on a cost-effective CMOS process. A patented structure is used in theSHA to greatly improve high frequency SFDR/distortion. Thisalso improves performance in IF undersampling applications.Each stage of the pipeline, excluding the last stage, consists of alow resolution flash ADC connected to a switched capacitorDAC and interstage residue amplifier (MDAC). The residueamplifier amplifies the difference between the reconstructed DACoutput and the flash input for the next stage in the pipeline. Onebit of redundancy is used in each of the stages to facilitate digitalcorrection of flash errors. The last stage simply consists of aflash ADC.

Factory calibration ensures high linearity and low distortion.

ANALOG INPUT OPERATIONFigure 3 shows the equivalent analog input of the AD9226 whichconsists of a 750 MHz differential SHA. The differential inputstructure of the SHA is highly flexible, allowing the device to beeasily configured for either a differential or single-ended input.The analog inputs, VINA and VINB, are interchangeable withthe exception that reversing the inputs to the VINA and VINBpins results in a data inversion (complementing the output word).

The optimum noise and dc linearity performance for eitherdifferential or single-ended inputs is achieved with the largest inputsignal voltage span (i.e., 2 V input span) and matched inputimpedance for VINA and VINB. Only a slight degradation indc linearity performance exists between the 2 V and 1 V inputspans.

High frequency inputs may find the 1 V span better suited toachieve superior SFDR performance. (See Typical Perfor-mance Characteristics.)

The ADC samples the analog input on the rising edge of the clockinput. During the clock low time (between the falling edge andrising edge of the clock), the input SHA is in the sample mode;during the clock high time it is in hold. System disturbances justprior to the rising edge of the clock and/or excessive clock jitteron the rising edge may cause the input SHA to acquire the wrongvalue and should be minimized.

When the ADC is driven by an op amp and a capacitive load isswitched onto the output of the op amp, the output will momen-tarily drop due to its effective output impedance. As the outputrecovers, ringing may occur. To remedy the situation, a seriesresistor can be inserted between the op amp and the SHAinput as shown in Figure 4. A shunt capacitance also acts likea charge reservoir, sinking or sourcing the additional chargerequired by the hold capacitor, CH, further reducing currenttransients seen at the op amp’s output.

The optimum size of this resistor is dependent on several factors,including the ADC sampling rate, the selected op amp, and theparticular application. In most applications, a 30 Ω to 100 Ωresistor is sufficient.

For noise-sensitive applications, the very high bandwidth of theAD9226 may be detrimental and the addition of a series resistor

and/or shunt capacitor can help limit the wideband noise at theADC’s input by forming a low-pass filter. The source imped-ance driving VINA and VINB should be matched. Failure toprovide matching will result in degradation of the AD9226’sSNR, THD, and SFDR.

CS

QS1

QH1

VINA

VINB

CS

QS1

CPIN

CPAR

CPIN

CPAR

QS2

CH

QS2

CH

Figure 3. Equivalent Input Circuit

10F

VINA

VINB

SENSE

AD9226

0.1F

VCC

VEE

RS33

VREF

REFCOM

15pFRS33

Figure 4. Series Resistor Isolates Switched-CapacitorSHA Input from Op Amp; Matching Resistors ImproveSNR Performance

OVERVIEW OF INPUT AND REFERENCECONNECTIONSThe overall input span of the AD9226 is equal to the potentialat the VREF pin. The VREF potential may be obtained fromthe internal AD9226 reference or an external source (seeReference Operation section).

In differential applications, the center point of the span isobtained by the common-mode level of the signals. In single-ended applications, the center point is the dc potential appliedto one input pin while the signal is applied to the opposite inputpin. Figures 5a–5f show various system configurations.

DRIVING THE ANALOG INPUTSThe AD9226 has a very flexible input structure allowing it tointerface with single-ended or differential input interface circuitry.

The optimum mode of operation, analog input range, and asso-ciated interface circuitry will be determined by the particularapplications performance requirements as well as power sup-ply options.

DIFFERENTIAL DRIVER CIRCUITSDifferential operation requires that VINA and VINB be simulta-neously driven with two equal signals that are 180 out of phasewith each other.

Differential modes of operation (ac- or dc-coupled input) providethe best THD and SFDR performance over a wide frequencyrange. They should be considered for the most demandingspectral-based applications (e.g., direct IF conversion to digital).

REV. B

AD9226

–15–

10F

VINA

VREF

AD9226

VINB

0.5V

SENSE

REFCOM0.1F

10F0.1F

0.1F15pF

1.5V

33

33

1V

0.1F

CAPT

CAPB

Figure 5a. 1 V Single-Ended Input, Common-ModeVoltage = 1 V

10F

VINA

VREF

AD9226

VINB

0.75V

SENSE

0.1F

10F0.1F

0.1F15pF

1.25V

33

33

1V

0.1F

49.9

1.25V

0.75V

CAPB

CAPT

Figure 5b. 1 V Differential Input, Common-ModeVoltage = 1 V

10F

VINA

VREF

AD9226

VINB

1.5V

SENSE

0.1F

10F0.1F

0.1F15pF

2.5V

33

33

2V

0.1F

49.9

2.5V

1.5V

CAPT

CAPB

Figure 5c. 2 V Differential Input, Common-ModeVoltage = 2 V

10F

VINA

VREF

AD9226

VINB

1.0V

SENSE

REFCOM0.1F

10F0.1F

0.1F15pF

3.0V

33

33

2V

0.1F

CAPT

CAPB

Figure 5d. 2 V Single-Ended Input, Common-ModeVoltage = 2 V

10F

VINA

VREF

AD9226(LQFP)

VINB

2.0V

SENSE

0.1F

10F0.1F

0.1F15pF

3.0V

33

33

2V

0.1F

49.9

3.0V

2.0V2.5V

2.5V

CMLEVEL0.1F

2.5V

CAPB

CAPT

Figure 5e. 2 V Differential Input, Common-ModeVoltage = 2.5 V

10F

VINA

VREF

AD9226

VINB

2.0V

SENSE

0.1F

10F0.1F

0.1F15pF

2.75V

33

33

1V

0.1F

49.9

2.75V

2.25V2.5V

2.5V

CAPT

CAPB

0.1F2.5V

AVDD10k10k

Figure 5f. 1 V Differential Input, Common-ModeVoltage = 2.5 V (Recommended for IF Undersampling)

The differential input characterization for this data sheet wasperformed using the configuration shown in Figure 7.

Since not all applications have a signal preconditioned fordifferential operation, there is often a need to perform a single-ended-to-differential conversion. In systems that do not need tobe dc-coupled, an RF transformer with a center tap is the bestmethod to generate differential inputs for the AD9226. It pro-vides all the benefits of operating the ADC in the differentialmode without contributing additional noise or distortion. An RFtransformer also has the added benefit of providing electricalisolation between the signal source and the ADC. An improvementin THD and SFDR performance can be realized by operatingthe AD9226 in the differential mode. The performance enhance-ment between the differential and single-ended mode is mostnoteworthy as the input frequency approaches and goes beyondthe Nyquist frequency (i.e., fIN > FS /2).

The circuit shown in Figure 6a is an ideal method of applyinga differential dc drive to the AD9226. It uses an AD8138 toderive a differential signal from a single-ended one. Figure 6billustrates its performance.

Figure 7 presents the schematic of the suggested transformercircuit. The circuit uses a Minicircuits RF transformer, modelT1-1T, which has an impedance ratio of four (turns ratio of 2).The schematic assumes that the signal source has a 50 Ω sourceimpedance. The center tap of the transformer provides a con-venient means of level-shifting the input signal to a desiredcommon-mode voltage. In Figure 7 the transformer centertapis connected to a resistor divider at the midsupply voltage.

REV. B

AD9226

–16–

1V p-pVINA

CAPB

AD9226

0.1F

1k

49.9

499

499

499

0.1F

10F0.1F

CAPT

0.1F

450

VINB

AD8138

10F

AVDD

0.1F

10F5V

0.1F

1k

0V

Figure 6a. Direct-Coupled Drive Circuit with AD8138Differential Op Amp

0

–20

–40

–60

–80

–100

–1200 4 8 12 16 20 24 28 32

MHz

SNR = 66.9dBcSFDR = 70.0dBc

dB

c

Figure 6b. FS = 65 MSPS, fIN = 30 MHz, Input Span = 1 V p-p

The same midsupply potential may be obtained from theCMLEVEL pin of the AD9226 in the LQFP package.

Referring to Figure 7, a series resistor, RS, is inserted between theAD9226 and the secondary of the transformer. The value of33 ohm was selected to specifically optimize both the THD andSNR performance of the ADC. RS and the internal capacitancehelp provide a low-pass filter to block high-frequency noise.

Transformers with other turns ratios may also be selected tooptimize the performance of a given application. For example, agiven input signal source or amplifier may realize an improve-ment in distortion performance at reduced output power levelsand signal swings. By selecting a transformer with a higherimpedance ratio (e.g., Minicircuits T16-6T with a 1:16 imped-ance ratio), the signal level is effectively “stepped up” thusfurther reducing the driving requirements of signal source.

VINA

VINB

AD922649.9

RS33

MINICIRCUITST1-1T

0.1F

RS33

0.1F

10F0.1F

0.1F

CAPB

CAPT

15pF1k

1k

AVDD

Figure 7. Transformer-Coupled Input

SINGLE-ENDED DRIVER CIRCUITSThe AD9226 can be configured for single-ended operation usingdc- or ac-coupling. In either case, the input of the ADC must bedriven from an operational amplifier that will not degrade theADC’s performance. Because the ADC operates from a singlesupply, it will be necessary to level-shift ground-based bipolarsignals to comply with its input requirements. Both dc- andac-coupling provide this necessary function, but each methodresults in different interface issues which may influence thesystem design and performance.

Single-ended operation requires that VINA be ac- or dc-coupledto the input signal source, while VINB of the AD9226 be biasedto the appropriate voltage corresponding to the middle of the inputspan. The single-ended specifications for the AD9226 are char-acterized using Figure 9a circuitry with input spans of 1 V and2 V. The common-mode level is 2.5 V.

If the analog inputs exceed the supply limits, internal parasiticdiodes will turn on. This will result in transient currents withinthe device. Figure 8 shows a simple means of clamping an input.It uses a series resistor and two diodes. An optional capacitor isshown for ac-coupled applications. A larger series resistor canbe used to limit the fault current through D1 and D2. Thiscan cause a degradation in overall performance. A similarclamping circuit can also be used for each input if a differen-tial input signal is being applied. A better method to ensurethe input is not overdriven is to use amplifiers powered by a single5 V supply such as the AD8138.

AVDD

AD9226

RS130

VCC

VEE

OPTIONALAC-COUPLINGCAPACITOR

D2

D1

RS220

Figure 8. Simple Clamping Circuit

AC-COUPLING AND INTERFACE ISSUESFor applications where ac-coupling is appropriate, the op ampoutput can be easily level-shifted by means of a couplingcapacitor. This has the advantage of allowing the op amp’s com-mon-mode level to be symmetrically biased to its midsupplylevel (i.e., (AVDD/2). Op amps that operate symmetrically withrespect to their power supplies typically provide the best acperformance as well as greatest input/output span. Various high-speed performance amplifiers that are restricted to +5 V/–5 Voperation and/or specified for 5 V single-supply operation can beeasily configured for the 2 V or 1 V input span of the AD9226.

Simple AC InterfaceFigure 9a shows a typical example of an ac-coupled, single-ended configuration of the SSOP package. The bias voltageshifts the bipolar, ground-referenced input signal to approxi-mately AVDD/2. The capacitors, C1 and C2, are 0.1 µF ceramicand 10 µF tantalum capacitors in parallel to achieve a lowcutoff frequency while maintaining a low impedance over awide frequency range. The combination of the capacitor and theresistor form a high-pass network with a high-pass –3 dB fre-quency determined by the equation,

f–3 dB = 1/(2 × π × R × (C1 + C2))

REV. B

AD9226

–17–

The low-impedance VREF output can be used to provide dcbias levels to the fixed VINB pin and the signal on VINA. Fig-ure 9b shows the VREF configured for 2.0 V, thus the inputrange of the ADC is 1.0 V to 3.0 V. Other input ranges couldbe selected by changing VREF.

When the inputs are biased from the reference (Figure 9b),there may be a slight degeneration of dynamic performance. Amidsupply output level is available at the CM LEVEL pin of theLQFP package.

10F

VINA

VINB

AD9226

VIN

VREF

15pF

0.1F

10F0.1F

0.1F

R

0.1F10F

RS

RS

C110F

CAPB

CAPT

RR+5V

–5VC2

0.1F

R0.1F

V V+1V

–1V0V

3.5

1.52.5

Figure 9a. AC-Coupled Input Configuration

10F

VINA

VINB

AD9226VIN

VREF

15pF

0.1F

10F0.1F

0.1F1k

1k

0.1F10F

0.1F

RS

RS10F

0.1F

CAPB

CAPT

Figure 9b. Alternate AC-Coupled Input Configuration

–84

–83

–82

–81

–80

–79

–78

–77

–765.0

dB

c

Volts4.54.03.53.02.52.01.51.00.50

Figure 10. THD vs. Common-Mode Voltage(2 V Differential Input Span, fIN = 10 MHz)

Figure 10 illustrates the relation between common-mode voltageand THD. Note that optimal performance occurs when thereference voltage is set to 2.0 V (input span = 2.0 V).

DC-COUPLING AND INTERFACE ISSUESMany applications require the analog input signal to be dc-coupledto the AD9226. An operational amplifier can be configured torescale and level-shift the input signal to make it compatiblewith the selected input range of the ADC.

The selected input range of the AD9226 should be consideredwith the headroom requirements of the particular op amp toprevent clipping of the signal. Many of the new high-performanceop amps are specified for only ±5 V operation and have limitedinput/output swing capabilities. Also, since the output of a dualsupply amplifier can swing below absolute minimum (–0.3 V),clamping its output should be considered in some applications(see Figure 8). When single-ended, dc-coupling is needed, theuse of the AD8138 in a differential configuration (Figure 9a) ishighly recommended.

Simple Op Amp BufferIn the simplest case, the input signal to the AD9226 will alreadybe biased at levels in accordance with the selected input range. Itis necessary to provide an adequately low source impedance forthe VINA and VINB analog pins of the ADC.

REFERENCE OPERATIONThe AD9226 contains an on-board bandgap reference thatprovides a pin-strappable option to generate either a 1 V or2 V output. With the addition of two external resistors, the usercan generate reference voltages between 1 V and 2 V. SeeFigures 5a-5f for a summary of the pin-strapping options for theAD9226 reference configurations. Another alternative is to usean external reference for designs requiring enhanced accuracyand/or drift performance described later in this section.

Figure 11a shows a simplified model of the internal voltage refer-ence of the AD9226. A reference amplifier buffers a 1 V fixedreference. The output from the reference amplifier, A1, appearson the VREF pin. The voltage on the VREF pin determinesthe full-scale input span of the ADC. This input span equals,

Full-Scale Input Span = VREF

The voltage appearing at the VREF pin, and the state of theinternal reference amplifier, A1, are determined by the voltageappearing at the SENSE pin. The logic circuitry contains com-parators that monitor the voltage at the SENSE pin. If theSENSE pin is tied to AVSS, the switch is connected to theinternal resistor network thus providing a VREF of 2.0 V. If theSENSE pin is tied to the VREF pin via a short or resistor, theswitch will connect to the SENSE pin. This connection will pro-vide a VREF of 1.0 V. An external resistor network will providean alternative VREF between 1.0 V and 2.0 V (see Figure 12).Another comparator controls internal circuitry that will disablethe reference amplifier if the SENSE pin is tied to AVDD.Disabling the reference amplifier allows the VREF pin to bedriven by an external voltage reference.

REV. B

AD9226

–18–

A2

LOGIC

A1

DISABLEA1

1V

TOA/D

AD9226

CAPT

CAPB

VREF

SENSE

REFCOM

2.5V

Figure 11a. Equivalent Reference Circuit

0.1F 10F

0.1F

0.1F

CAPT

CAPB

AD9226

VREF

0.1F10F

Figure 11b. CAPT and CAPB DC-Coupling

The actual reference voltages used by the internal circuitry of theAD9226 appear on the CAPT and CAPB pins. The voltageson these pins are symmetrical about the analog supply. Forproper operation when using an internal or external reference, itis necessary to add a capacitor network to decouple these pins.Figure 11b shows the recommended decoupling network. Theturn-on time of the reference voltage appearing between CAPTand CAPB is approximately 10 ms and should be evaluated inany power-down mode of operation.

USING THE INTERNAL REFERENCEThe AD9226 can be easily configured for either a 1 V p-p inputspan or 2 V p-p input span by setting the internal reference.Other input spans can be realized with two external gain-setting resistors as shown in Figure 12 of this data sheet, orusing an external reference.

Pin Programmable ReferenceBy shorting the VREF pin directly to the SENSE pin, the inter-nal reference amplifier is placed in a unity-gain mode and theresultant VREF output is 1 V. By shorting the SENSE pindirectly to the REFCOM pin, the internal reference amplifier isconfigured for a gain of 2.0 and the resultant VREF output is2.0 V. The VREF pin should be bypassed to the REFCOM pinwith a 10 µF tantalum capacitor in parallel with a low-inductance0.1 µF ceramic capacitor as shown in Figure 11b.

Resistor Programmable ReferenceFigure 12 shows an example of how to generate a referencevoltage other than 1.0 V or 2.0 V with the addition of two exter-nal resistors. Use the equation,

VREF = 1 V × (1 + R1/R2)

to determine appropriate values for R1 and R2. These resistorsshould be in the 2 kΩ to 10 kΩ range. For the example shown,R1 equals 2.5 kΩ and R2 equals 5 kΩ. From the equation above,the resultant reference voltage on the VREF pin is 1.5 V. Thissets the input span to be 1.5 V p-p. The midscale voltage canalso be set to VREF by connecting VINB to VREF. Alterna-tively, the midscale voltage can be set to 2.5 V by connectingVINB to a low-impedance 2.5 V source as shown in Figure 12.

VINA

VREF

AD9226

VINB

1.75V

SENSE

REFCOM0.1F

10F0.1F

0.1F15pF

3.25V 33

331.5V

0.1F

CAPT2.5V

10FR12.5k

R25k

CAPB

Figure 12. Resistor Programmable Reference (1.5 V p-pInput Span, Differential Input VCM = 2.5 V)

USING AN EXTERNAL REFERENCEThe AD9226 contains an internal reference buffer, A2 (seeFigure 11b), that simplifies the drive requirements of an externalreference. The external reference must be able to drive about5 kΩ (±20%) load. Note that the bandwidth of the referencebuffer is deliberately left small to minimize the reference noisecontribution. As a result, it is not possible to rapidly change thereference voltage in this mode.

Figure 13 shows an example of an external reference drivingboth VINB and VREF. In this case, both the common-modevoltage and input span are directly dependent on the value ofVREF. Both the input span and the center of the input span areequal to the external VREF. Thus the valid input range extendsfrom (VREF + VREF/2) to (VREF – VREF/2). For example,if the REF191, a 2.048 V external reference, is selected, theinput span extends to 2.048 V. In this case, 1 LSB of the AD9226corresponds to 0.5 mV. It is essential that a minimum of a 10 µFcapacitor, in parallel with a 0.1 µF low-inductance ceramiccapacitor, decouple the reference output to ground.

To use an external reference, the SENSE pin must be connectedto AVDD. This connection will disable the internal reference.

VINA

VREF

AD9226

VINB

SENSE0.1F

10F0.1F

0.1F15pF

VINA+VREF/2 33

33

0.1F

CAPT

CAPB

VINB–VREF/2

10F

VREF0.1F

5V

5V

Figure 13. Using an External Reference

REV. B

AD9226

–19–

MODE CONTROLSClock StabilizerThe clock stabilizer is a circuit that desensitizes the ADC fromclock duty cycle variations. The AD9226 eases system clockconstraints by incorporating a circuit that restores the internal dutycycle to 50%, independent of the input duty cycle. Low jitter onthe rising edge (sampling edge) of the clock is preserved whilethe noncritical falling edge is generated on-chip.

It may be desirable to disable the clock stabilizer, and may benecessary when the clock frequency speed is varied or completelystopped. Once the clock frequency is changed, over 100 clockcycles may be required for the clock stabilizer to settle to a dif-ferent speed. When the stabilizer is disabled, the internal switchingwill be directly affected by the clock state. If the external clock ishigh, the SHA will be in hold. If the clock pulse is low, the SHAwill be in track. TPC 16 shows the benefits of using the clockstabilizer. See Tables I and III.

Data Format Select (DFS)The AD9226 may be set for binary or two’s complement dataoutput formats. See Tables I and II.

SSOP PackageThe SSOP mode control (Pin 22) has two functions. It enables/disables the clock stabilizer and determines the output data format.The exact functions of the mode pin are outlined in Table I.

Table I. Mode Select (SSOP)

Mode DFS Clock Duty Cycle Shaping

DNC Binary Clock Stabilizer DisabledAVDD Binary Clock Stabilizer EnabledGND Two’s Complement Clock Stabilizer Enabled10 kΩ Two’s Complement Clock Stabilizer DisabledResistor To GND

LQFP PackagePin 35 of the LQFP package determines the output data format(DFS). If it is connected to AVSS, the output word will be straightbinary. If it is connected to AVDD, the output data format willbe two’s complement. See Table II.

Pin 43 of the LQFP package controls the clock stabilizer functionof the AD9226. If the pin is connected to AVSS, both clockedges will be used in the conversion architecture. When Pin 43is connected to AVDD, the internal duty cycle will be determinedby the clock stabilizer function within the ADC. See Table III.

Table II. DFS Pin Controls

DFS Function Pin 35 Connection

Straight Binary AVSSTwo’s Complement AVDD

Table III. Clock Stabilizer Pin

Clock Restore Function Pin 43 Connection

Clock Stabilizer Enabled AVDDClock Stabilizer Disabled AVSS

DIGITAL INPUTS AND OUTPUTSDigital OutputsTable IV details the relationship among the ADC input, OTR, andstraight binary output.

Table IV. Output Data Format

Two’sBinary Complement

Input (V) Condition (V) Output Mode Mode OTR

VINA–VINB < – VREF 0000 0000 0000 1000 0000 0000 1

VINA–VINB = – VREF 0000 0000 0000 1000 0000 0000 0

VINA–VINB = 0 1000 0000 0000 0000 0000 0000 0

VINA–VINB = + VREF – 1 LSB 1111 1111 1111 0111 1111 1111 0

VINA–VINB ≥ + VREF 1111 1111 1111 0111 1111 1111 1

Out of Range (OTR)An out-of-range condition exists when the analog input voltageis beyond the input range of the converter. OTR is a digitaloutput that is updated along with the data output correspondingto the particular sampled analog input voltage. Hence, OTR hasthe same pipeline delay (latency) as the digital data. It is LOWwhen the analog input voltage is within the analog input range.It is HIGH when the analog input voltage exceeds the inputrange as shown in Figure 14. OTR will remain HIGH until theanalog input returns within the input range and another conversionis completed. By logical ANDing OTR with the MSB and itscomplement, overrange high or underrange low conditions can bedetected. Table V is a truth table for the over/underrangecircuit in Figure 15, which uses NAND gates. Systems requiringprogrammable gain conditioning of the AD9226 input signalcan immediately detect an out-of-range condition, thus elimi-nating gain selection iterations. Also, OTR can be used fordigital offset and gain calibration.

Table V. Out-of-Range Truth Table

OTR MSB Analog Input Is

0 0 In Range0 1 In Range1 0 Underrange1 1 Overrange

1111 1111 1111

1111 1111 1111

1111 1111 1110

OTR

–FS +FS

–FS +1/2 LSB

+FS – 1/2 LSB–FS – 1/2 LSB

+FS – 1 1/2 LSB

0000 0000 00010000 0000 00000000 0000 0000

1

0

0

001

OTR DATA OUTPUTS

Figure 14. OTR Relation to Input Voltage and Output Data

OVER = 1

UNDER = 1

MSB

OTR

MSB

Figure 15. Overrange or Underrange Logic

REV. B

AD9226

–20–

Digital Output Driver ConsiderationsThe AD9226 output drivers can be configured to interface with5 V or 3.3 V logic families by setting DRVDD to 5 V or 3.3 Vrespectively. The output drivers are sized to provide sufficientoutput current to drive a wide variety of logic families. However,large drive currents tend to cause glitches on the supplies and mayaffect converter performance. Applications requiring the ADC todrive large capacitive loads or large fan outs may require externalbuffers or latches.

OEB Function (Three-State)The LQFP-packaged AD9226 has Three-State (OEB) ability. Ifthe OEB pin is held low, the output data drivers are enabled. Ifthe OEB pin is high, the output data drivers are placed in a highimpedance state. It is not intended for rapid access to buss.

Clock Input ConsiderationsHigh-speed, high-resolution ADCs are sensitive to the quality ofthe clock input. The clock input should be treated as an analogsignal in cases where aperture jitter may affect the dynamicperformance of the AD9226. Power supplies for clock driversshould be separated from the ADC output driver supplies toavoid modulating the clock signal with digital noise. Low-jittercrystal controlled oscillators make the best clock sources.

The quality of the clock input, particularly the rising edge, iscritical in realizing the best possible jitter performance of thepart. Faster rising edges often have less jitter.

Clock Input and Power DissipationMost of the power dissipated by the AD9226 is from the analogpower supplies. However, lower clock speeds will reduce digitalcurrent. Figure 16 shows the relationship between power andclock rate.

SAMPLE RATE – Msps

5 15

PO

WE

R D

ISS

IPA

TIO

N –

mW

250

20025 35

300

350

400

450

500

550

600

45 55 65 75

DRVDD = 3V

DRVDD = 5V

Figure 16. Power Consumption vs. Sample Rate

GROUNDING AND DECOUPLINGAnalog and Digital GroundingProper grounding is essential in any high-speed, high-resolutionsystem. Multilayer printed circuit boards (PCBs) are recom-mended to provide optimal grounding and power schemes. Theuse of ground and power planes offers distinct advantages:

1. The minimization of the loop area encompassed by a signaland its return path.

2. The minimization of the impedance associated with groundand power paths.

3. The inherent distributed capacitor formed by the powerplane, PCB insulation, and ground plane.

It is important to design a layout that prevents noise from cou-pling onto the input signal. Digital signals should not be run inparallel with input signal traces and should be routed away fromthe input circuitry. While the AD9226 features separate analogand driver ground pins, it should be treated as an analog com-ponent. The AVSS and DRVSS pins must be joined togetherdirectly under the AD9226. A solid ground plane under theADC is acceptable if the power and ground return currents arecarefully managed.

0.1F

AVDD

AVSS

AD922610F

Figure 17. Analog Supply Decoupling

Analog and Digital Driver Supply DecouplingThe AD9226 features separate analog and digital supply andground pins, helping to minimize digital corruption of sensitiveanalog signals. In general, AVDD (analog power) should bedecoupled to AVSS (analog ground). The AVDD and AVSSpins are adjacent to one another. Also, DRVDD (digital power)should be decoupled to DRVDD (digital ground). The decouplingcapacitors (especially 0.1 µF) should be located as close to thepins as possible. Figure 17 shows the recommended decouplingfor the pair of analog supplies; 0.1 µF ceramic chip and 10 µFtantalum capacitors should provide adequately low impedanceover a wide frequency range.

0.1F

CMLAD9226 0.1F

VR

Figure 18. CML Decoupling (LQFP)

Bias DecouplingThe CML and VR are analog bias points used internally by theAD9226. These pins must be decoupled with at least a 0.1 µFcapacitor as shown in Figure 18. The dc level of CML is approxi-mately AVDD/2. This voltage should be buffered if it is to beused for any external biasing. CML and VR outputs are onlyavailable in the LQFP package.

0.1F

DRVDD

DRVSSAD922610F

Figure 19. Digital Supply Decoupling

CMLThe LQFP-packaged AD9226 has a midsupply reference point.This midsupply point is used within the internal architecture ofthe AD9226 and must be decoupled with a 0.1 µF capacitor. Itwill source or sink a load of up to 300 µA. If more current isrequired, it should be buffered with a high impedance amplifier.

REV. B

AD9226

–21–

VRVR is an internal bias point on the LQFP package. It must bedecoupled to ground with a 0.1 µF capacitor.

The digital activity on the AD9226 chip falls into two generalcategories: correction logic and output drivers. The internalcorrection logic draws relatively small surges of current, mainlyduring the clock transitions. The output drivers draw largecurrent impulses while the output bits are changing. The sizeand duration of these currents are a function of the load on theoutput bits: large capacitive loads are to be avoided.

For the digital decoupling shown in Figure 19, 0.1 µF ceramicchip and 10 µF tantalum capacitors are appropriate. Reason-able capacitive loads on the data pins are less than 20 pF perbit. Applications involving greater digital loads should considerincreasing the digital decoupling proportionally and/or usingexternal buffers/latches.

A complete decoupling scheme will also include large tantalumor electrolytic capacitors on the power supply connector toreduce low-frequency ripple to negligible levels.

EVALUATION BOARD AND TYPICAL BENCHCHARACTERIZATION TEST SETUPThe AD9226 evaluation board is configured to operate uponapplying both power and the analog and clock input signals. Itprovides three possible analog input interfaces to characterizethe AD9226’s ac and dc performance. For ac characterization, itprovides a transformer coupled input with the common-modeinput voltage (CMV) set to AVDD/2. Note, the evaluationboard is shipped with a transformer coupled interface and a 2 Vinput span. For differential dc coupled applications, the evalua-tion board has provisions to be driven by the AD8138 amplifier.If a single-ended input is desired, it may be driven through theS3 connector. The various input signal options are accessible bythe jumper connections. Refer to the Evaluation Board schematic.

The clock input signal to the AD9226 evaluation board can beapplied to one of two inputs, CLOCK and AUXCLK. TheCLOCK input should be selected if the frequency of the inputclock signal is at the target sample rate of the AD9226. Theinput clock signal is ac-coupled and level-shifted to the switch-ing threshold of a 74VHC02 clock driver. The AUXCLK inputshould be selected in applications requiring the lowest jitter andSNR performance (i.e., IF Undersampling characterization). Itallows the user to apply a clock input signal that is 4× the targetsample rate of the AD9226. A low-jitter, differential divide-by-4counter, the MC100EL33D, provides a 1× clock output that issubsequently returned back to the CLOCK input via JP7. Forexample, a 260 MHz signal (sinusoid) will be divided down toa 65 MHz signal for clocking the ADC. Note, R1 must beremoved with the AUXCLK interface. Lower jitter is oftenachieved with this interface since many RF signal generatorsdisplay improved phase noise at higher output frequencies andthe slew rate of the sinusoidal output signal is 4× that of a 1×signal of equal amplitude.

Figure 20 shows the bench characterization setup used to evalu-ate the AD9226’s ac performance for many of the data sheetcharacterization curves. Signal and Clock RF generators A andB are high-frequency, “very” low-phase noise frequency sources.These generators should be phase locked by sharing the same10 MHz REF signal (located on the instruments back panel) toallow for nonwindowed, coherent FFTs. Also, the AUXCLKoption on the AD9226 evaluation board should be used toachieve the best SNR performance. Since the distortion andbroadband noise of an RF generator can often be a limitingfactor in measuring the true performance of an ADC, a high Qpassive bandpass filter should be inserted between the generatorand AD9226 evaluation board.

5V5V 3V 3V

AVDD GND GND DUTDVDD

DVDDDUTAVDD

DSPEQUIPMENT

S4INPUTxFMR

S1INPUTCLOCK

AD9226EVALUATION BOARD

1MHzBANDPASS FILTER

SIGNAL SYNTHESIZER65(OR 260MHz), 4V p-p

HP8644 OUTPUTWORD

(P1)

S4AUX CLOCK

(4)

REFIN

CLK SYNTHESIZER65(OR 260MHz), 4V p-p

HP8644

10MHzREFOUT

Figure 20. Evaluation Board Connections

REV. B

AD9226

–22–

U1

11

12

13

16

17

18

19

27

26

25

20

21

24

28

D20

D30

D40

D50

D60

D70

D80

D90

D100

D110

D120

D130

OTR0

47

46

45

42

41

40

39

4

1

2

38

37

36

3

D10

48

9

8

10D00

44

7

43

35

15

14

JP2

JP1

JP6

AVDD

C20.1F

R421k

R61k

R101k

DUTCLK

WHTTP6

C400.001F

C370.1F

29

23

22

31

34

30

C310F

10V

33

5

6

32

C410.001F

C380.1F

C2310F

10V

DUTAVDD

VINA

VINBSHEET 3

C500.1F

C330.1F

C2010F

10V

C320.1F

C340.1F

C390.001F

C360.1F

C110F

10V

DUTAVDDJP22JP23

JP25

JP24

C350.1F

C2110F

10V

R410k

R310k

TP5WHT

OTR

MSB-B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

LSB-B14

NC3

OEB

VR

DUTY

CLK

NC4

DRVDD2

DRVSS2

DFS

AVDD1

AVDD2

AVSS1

AVSS2

SENSE

VREF

REFCOM

CAPB1

CAPB2

CAPT1

CAPT2

CML

VINA

VINB

NC1

NC2

AVSS3

AVSS4

AVDD3

AVDD4

DRVSS3

DRVDD3

DRVDD1

DRVSS1

DUTDRVDD

AD9226LQFP

NC = NO CONNECT

C590.1F

C5822F

25V

2TB1

3TB1AGND

FBEAD2

L11

TP2RED

DUTAVDDDUTAVDDIN

C530.1F

C4822F

25V

5TB1

4TB1AGND

FBEAD2

L31

TP3RED

DUTDRVDDDRVDDIN

C520.1F

C4722F

25V

1TB1

FBEAD2

L21

TP1RED

AVDDAVDDIN

C140.1F

C622F

25V

6TB1

FBEAD2

L41

TP4RED

DVDDDVDDIN

TP11BLK

TP12BLK

TP13BLK

TP14BLK

Figure 21. AD9226 Evaluation Board

REV. B

AD9226

–23–

U7

20VCC

17Y2

10GND

18Y1

G1

16Y3

15Y4

14Y5

13Y6

12Y7

11Y8

19G2

2D5 A1

3D4 A2

4D3 A3

5D2 A4

6D1 A5

7D0 A6

8OTR A7

9A8

1

10F1

10V2

C5

C110.1F

74VHC541

U6

20VCC

17Y2

10GND

18Y1

G1

16Y3

15Y4

14Y5

13Y6

12Y7

11Y8

19G2

2D13 A1

3D12 A2

4D11 A3

5D10 A4

6D9 A5

7D8 A6

8D7 A7

9A8

1

10F1

10V2

C4

C120.1F

74VHC541

D6

DVDD

RP1221 16

RP1224 13

RP1223 14

RP1222 15

RP1225 12

RP1226 11

RP1227 10

RP1228 9

1 P1

3 P1

5 P1

7 P1

9 P1

11 P1

13 P1

15 P1

2P1

4P1

6P1

8P1

10P1

12P1

14P1

16P1

RP2221 16 17 P1 18P1

RP2222 15 19 P1 20P1

RP2223 14 21 P1 22P1

RP2224 13 23 P1 24P1

RP2225 12 25 P1 26P1RP2226 11 27 P1 28P1

29 P1 30P1

31 P1 32P1RP2228 9 33 P1 34P1

35 P1 36P1

37 P1 38P1RP2227 10 39 P1 40P1

R922JP4

JP321

8c

74VHC04

10118b

74VHC04

R722 DUTCLK

12138a

74VHC04

TP7

JP171

2AB

3

C130.10F

R149.9

R194k

R25k

R184k

AVDD

JP7

R1590

R13113 C19

0.1F

AVDD

R1490

R12113

C170.1F

AVDD

U3

1NC

2INA

3INB

4INCOM

8AVDD VCC

7OUT

6REF

5VEE

T2

1

2

3

6

5

4

T1–1T

2

2D2

D1

1N5712

1N5712

R1149.9

CLOCKS1

2

1

2

1

AUXCLKS5

MC100EL33D

WHT

NC = NO CONNECT

C180.1F

C2610F10V

U3DECOUPLING

AVDD

C100.1F

C310F10V

U8DECOUPLING

AVDD89

8d

74VHC04

658e

74VHC04

438f

74VHC04

Figure 22. AD9226 Evaluation Board

REV. B

AD9226

–24–

1

2

JP5

C90.33F

R549.9

SINGLEINPUT

S3

R411k

R401k

C70.1F

AVDD

2

1

8U2

6AD8138

5

VDCVO–

VO

VCC

VEEW

–W

3

4

R37499

R36499

R34523

R35499

AMP INPUTS2

1

2 R3149.9

C690.1F

C1510F10V

21

AVDD

R3310k

R3210k

AVDD

C80.1F

JP42

JP40

JP45R2122

C44TBD

VINA

JP46

JP41

JP43

R2222

C43TBD

VINB

C2450pF SHEET 1

T2

1

2

3

6

5

4

T1–1T

R2449.9

1

2

XFMR INPUTS4

DUTAVDD

R381k

C250.33F

C160.1F

R81k RP6

22 81 D3D30RP622 72 D2D20RP622 63 D1D10RP622 54 D0D00

RP522 81 D6D60RP522 72 D5D50RP522 63 D4D40RP522 54

RP422 81 D10D100RP422 72 D9D90RP422 63 D8D80RP422 54 D7D70

RP322 81 OTROTRORP322 72 D13D130RP322 63 D12D120RP322 54 D11D110

Figure 23. AD9226 Evaluation Board

Figure 24. Evaluation Board Component Side Layout (Not to Scale)

REV. B

AD9226

–25–

Figure 25. Evaluation Board Solder Side Layout (Not to Scale)

Figure 26. Evaluation Board Power Plane

REV. B

AD9226

–26–

Figure 27. Evaluation Board Ground Plane

Figure 28. Evaluation Board Component Side (Not to Scale)

REV. B

AD9226

–27–

Figure 29. Evaluation Board Solder Side (Not to Scale)

REV. B–28–

AD9226

C01

027–

0–3/

01(B

)P

RIN

TE

D IN

U.S

.A.

OUTLINE DIMENSIONSDimensions shown in inches and (mm).

28-Lead Shrink Small Outline(RS-28)

0.009 (0.229)0.005 (0.127)

0.03 (0.762)0.022 (0.558)

8°0°0.008 (0.203)

0.002 (0.050)

0.07 (1.79)0.066 (1.67)

0.078 (1.98)0.068 (1.73)

0.015 (0.38)0.010 (0.25)

SEATINGPLANE

0.0256(0.65)BSC

0.31

1 (7

.9)

0.30

1 (7

.64)

0.21

2 (5

.38)

0.20

5 (5

.21)

28 15

141

0.407 (10.34)0.397 (10.08)

PIN 1

48-Lead Thin Plastic Quad Flatpack(ST-48)

TOP VIEW(PINS DOWN)

1

1213

2524

363748

0.019 (0.5)BSC

0.276(7.00)BSCSQ

0.011 (0.27)0.006 (0.17)

0.354 (9.00) BSC SQ

0.063 (1.60)MAX

0.030 (0.75)0.018 (0.45)

0.008 (0.2)0.004 (0.09)

0MIN

COPLANARITY0.003 (0.08)

SEATINGPLANE

0.006 (0.15)0.002 (0.05)

70

0.057 (1.45)0.053 (1.35)