A 74.33 dB SNDR 20 MSPS 2.74 mW Pipelined ADC using a ...

A 74.33 dB SNDR 20 MSPS 2.74 mWPipelined ADC using a Dynamic

Deadzone Ring Amplifier

May 1, 2017

by Spencer Leuenberger, Jason Muhlestein, Hyuk Sun, Praveen Kumar Venkatachala, and Un-Ku Moon

Oregon State University

Table of Contents

May 1, 2017

1

• Introduction & Motivation

• Prior Work – Ring Amplifiers

• Current-Starved Inverter

• Ring Amplifier w/ Dynamic Deadzone

• Pipeline Architecture

• Measurements

Introduction & Motivation

May 1, 2017

2

• High-performance amplifiers necessary for high-precision ADCs requiring residue amplifiers.

• Traditional OpAmps power inefficient with respect to scaling trends

• Ring amplifiers introduced recently as a scalable amplifier.

Introduction to Ring Amplifiers

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3

• Inverter based amplifier with intentionally embedded offsets paths.

• Offsets ‘biases’ output transistors into low-BW and high-gain.

• Has large initial slewing capability.

• Dynamic gain-bandwidth during amplification.

Prior Work – Cap Embedded Dead Zone

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4

• Capacitors store opposite polarity offsets.

• Often combined with input-offset canceling capacitor.

• Power-gated when off.

• Often used as a ‘coarse’ ring amplifier.

B. Hershberg [JSSCC Dec 2012, ISSCC Feb 2012]

Prior Work – Fine Ring Amplifier

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5

• Designed for fine settling.

• Operated in parallel with coarse ring amplifier.

• Deadzone implemented before 3rd stage.

• Differential-to-single ended input.

B. Hershberg [VLSI 2013]

Prior Work – Self-Biased Ring Amplifier

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6

Y. Lim [JSSCC OCT 2015,JSSCC DEC 2015]

• Resistor embedded in second-stage implements deadzone.

• Does not require external voltage control.

• First ring amplifier with fully-differential implementation

Motivation

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7

• Unknown noise performance of ring amplifiers.

• Coarse and fine ring amplifiers take up extra area.

Want

• A ring-amplifier noise limited ADC

• A continually tunable dead zone.

What is the capacitive deadzone doing?

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8

• Comparator can be thought of as an OpAmp

• Trigger point of inverter function as reference.

• Capacitive deadzone changes the trigger point.

Current-Starved Inverters (CSI)

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9

• Control node allows for a tunable trigger point.

• Can only change trigger point in one direction.

Current-starved inverters for output transistors

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10

• NMOS control only effective for PMOS output path.

• PMOS control added for NMOS output path.

CSI Trigger points when swept

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11

• PMOS & NMOS have Vth difference.

• Has a ‘default’ trigger point.

CSI Ring Amplifier

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12

• Will be the first stage amplifier of pipeline.

• Majority power is burned in first stage.

CSI Ring Amplifier with dynamic deadzone

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13

• Dynamic control allows ring amplifier to go between two different deadzones.

• Amplifier goes from coarse to fine operation in this design.

Ring Amplifier Noise Simulations?

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14

• Noise at end of amplification is what sampled.

• Transient noise simulations take large-signal effects into account.• Fmin = 1 KHz, Fmax = 10G

• Important to include equivalent DAC resistance.

Effect of DAC Resistance on settling

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15

• Small amount of DAC resistance has a large effect on settling

• Time constant of DAC = 0.28n

• CSI voltages are referenced differentially from their common-mode.

Ring Amplifier Noise simulations

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16

• Same simulations as previously but looking at instantaneous integrated output noise.

• Larger deadzones (less BW) does not guarantee lowest noise.

Ring Amplifier Noise Sweep

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17

• Without DAC resistance greater variability in noise.

• Both have approximately same local minimum.

Pipeline Architecture

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18

• 8 pF sampling capacitance (16 pF differential).

• High gain of 1st stage (16) isolates noise performance of first amplifier.

• 1.2V Reference

• Lower resolution per-stage at back end.

Hi and Low Frequency PSDs

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19

• SFDR drop at high-frequency related to input network

Measurements vs Input Amplitude

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20

• MDAC and ring amplifier allow for slightly higher than full-scale input

Measurements vs Control Voltage

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21

• Measurements peak and then fall off rapidly with increasing control voltage (less BW/more gain).

NF Sweep vs Control Voltage measurement

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22

• No signal applied.

• Noise minimum found.

• Amplifier not used in region where noise increases.

Noise floor measurements vs simulations

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23

• Both simulations and measurements show noise minimum.

Die Photo

May 1, 2017

24

• Core amplifier area of 1st stage is ~70µx40µ.

ADC Summary

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25

• With a 2.5 Vpk-pk (~ 0.3dBFS) integrated input-referred noise is ~159 µVrms.

• Close to noise floor measurements.

• 1st stage amplifier consumes 690 µW.

• Amplifier noise limited not sampling.

Comparison with other ring amplifiers

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26

• Comparable with other ring amplifiers despite sampling noise overdesign.

Conclusions

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27

Acknowledgements

• Thanks to Asahi Kasei Microdevices for fabrication and packaging

• Current-starved inverter ring amplifier introduced.

• Dynamic deadzone that automatically increases deadzoneduring amplification was presented.

• Transient noise simulations verified to capture large-signal behavior of ring amplifiers.

Backup

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28

CSI Output v1

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29

• Change sizes to embed different ‘default’ deadzones.

CSI Output v2

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30

• Change opposite transistor in inverter changes default behavior but not with

large control signal.

Standard Vs Dynamic Gate Voltages

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31

• Gate voltages of PMOS and NMOS output transistors for onedifferential output.

• Dynamic deadzone provides consistent slewing behavior.

BACKUP for Slide 16

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32

• Let the 200mV case from Slide 16 settle for MUCH longer.

• Eventually converge to same output voltage.

Standard Vs Dyanmic Mode

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33

• Peak performance is roughly the same between modes.

• Less sensitive to control voltage in dynamic mode.

Noise Floor setups.

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34

• Balun includes a centertap to common-mode voltage.

• Above: Input network used for noise floor in main slides

• Below: Input network used for noise floor in following slides.

Noise Floor versus sampling frequency.

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35

• Noise floor also depends weakly on sampling frequency.

• Different input network has measurements below simulations.