8255&82531

Peripheral Controllers• Intel has developed several peripheral controller chips

designed to support its processors.• The goal is to give a complete I/O interface in one

chip. • Examples:

– 8255 is Programmable Peripheral Interface (PPI).– 8253/8254 is Programmable Interval Timer (PIT)– 8279 is Programmable Keyboard/Display interface.– 8259 is Programmable Interrupt Controller (PIC)– 8251 is Serial Communication Interface

8255A• Is one of the peripheral controller chips

designed to support its processors.

• 8255 is Programmable Peripheral Interface (PPI).

• It is a general purpose parallel I/O Interfacing device.

• It provides 24 I/O lines organized in three 8-bit I/O ports in one 40-pin package.

• The ports are usually labeled A,B, and C.

Size of ports• Ports A and B can be programmed as an 8-bit

input or output port.

• In port C each nipple (four bits) can be programmed separately to be a 4-bit input or output port.

• Only the above size of ports (byte or nipple) can be programmed. For Example, individual bit in a port cannot be programmed.

• However, what make 8255 a versatile devise is its programming modes

8255

Port A

CU

Port C

Port B

CL

Programming modes

• BSR mode – Bit Set Reset mode

• I/O mode- Input /Output mode– Mode 0– Mode 1– Mode 2

Programming modes• Mode 0: the 8255A is programmed to look like

three simple I/O ports.

• Mode 1: the 8255A is programmed to have two handshaking I/O ports.

• Mode 2: the 8255A is programmed to have one bidirectional port with five handshaking signals.

• The modes can be intermixed, for example, port A is programmed to operate in mode 2, while port B operates in mode 0.

• bit set/reset mode allows individual bits of port C to be set or reset for control purposes.

FIGURE 8-11 8255 programmable peripheral interface (PPI). Twenty-four I/O pins are provided grouped as three 8-bit I/O ports. There is one 8-bit control port. (Courtesy of Intel Corporation.)

John UffenbeckThe 80x86 Family: Design, Programming, and Interfacing, 3e

Copyright ©2002 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

FIGURE 8-12 Interfacing the 8255 to the 386/486 processors. The four PPI ports are mapped to addresses 0, 4, 8, and C.

John UffenbeckThe 80x86 Family: Design, Programming, and Interfacing, 3e

Copyright ©2002 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

8255

A1 A0 RD WR CS Data flow Direction0 0 0 1 0 PORT A to data bus0 1 0 1 0 PORT B to data bus1 0 0 1 0 PORT C to data bus

0 0 1 0 0 data bus to PORT A0 1 1 0 0 data bus to PORT B1 0 1 0 0 data bus to PORT C1 1 1 0 0 data bus to control

x x x x 1 data bus in 3rd state1 1 0 1 0 illegal conditionx x 1 1 0 data bus in 3rd state

FIGURE 8-13 Two types of 8255A control bytes. (a) When bit 7 = 0, a bit set/reset operation is indicated; (b) When bit 7 = 1, any of the modes 0, 1, or 2 can be programmed. (From J. Uffenbeck, Microcomputers and Microprocessors: The 8080, 8085 and Z 80, Prentice Hall, Englewood Cliffs, NJ, 1991.)

John UffenbeckThe 80x86 Family: Design, Programming, and Interfacing, 3e

Copyright ©2002 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

8255 Programmable Peripheral Interface

Data bus

8085

D[7:0]

A0A1

RDWR

RESET

CS

Control port

PA[7:0]

PB[7:0]

PC[7:0]

A7A6A5A4A3A2

IO/MA1 A0 Port

0 00 11 01 1

PAPBPCControl

8255 Programmable Peripheral Interface

Programming 8255

8255 has three operation modes: mode 0, mode 1, and mode 2

Programming 8255

Mode 0:

— Ports A, B, and C can be individually programmed as input or output ports— Port C is divided into two 4-bit ports which are independent from each other

Mode 1:

— Ports A and B are programmed as input or output ports— Port C is used for handshaking

PA[7:0]

STBA

IBFA

INTRAPC3PC5PC4

PB[7:0]

STBB

IBFB

INTRBPC0PC1PC2

PC6, 7

8255

PA[7:0]

OBFA

ACKA

INTRAPC3PC6PC7

PB[7:0]

OBFB

ACKB

INTRBPC0PC1PC2

PC4, 5

8255

Mode 1Input configuration

Mode 1Output configuration

Programming 8255 contd…. Mode 2:

— Port A is programmed to be bi-directional— Port C is for handshaking— Port B can be either input or output in mode 0 or mode 1

PA[7:0]

OBFA

ACKA

INTRA

PC4

PC6PC7

STBA

IBFA

PC0

PC3PC58255

PC2

PC1

PB[7:0]

In Out In OutIn Out

Mode 0

STBB OBFB IBFB ACKB

INTRB INTRB

Mode 1

1. Write the instructions that set 8255 into mode 0, port A as input, port B as output, PC0-PC3 as input, PC4-PC7 as output ?

Programmable Timer 8254

8254 Programming

Modes of operation

• Mode 0: – Event counter (example: timer for interrupt)– When the counter initiated it will start decrement

count from the next T.– Out is low for time of count: (n+1)T.– Gate should be high for the counter to decrement.

• Mode 1: – Hardware initiated counter using Gate (positive

pulse).– When the counter initiated it will start decrement

count.– Out is low for time of count: nT.

• Mode 2: – The counter will generate a series of continuous

pulses.– Out will pulse low for one period low at the end of

the count.– f= clk/n duty cycle=(n-1)/n– Gate should be high.

• Mode 3: – Square wave generator.– Like mode2– Half of the count, out is high and low in the other

half.

• Mode 4: – The counter will generate a series of continuous

pulses.– Out will have one active low pulse when at the end

of the count.– out is high for (n+1)T and then one active low pulse– Gate should be high.

• Mode 5: – Like mode4– But hardware imitated by Gate.– out is high for nT and then one active low pulse

8254 Read Back Command

8254 Read Back Command

1 1 COUNT STATUS CNT2 CNT1 CNT0 0

NULL COUNT: goes low when the new count written to a counter is actually loaded into the counter

8254 status word format

OUTPUTNULL

COUNT RW1 RW0 M2 M1 M0 BCD

PROGRAMMABLE INTERRUPT CONTROLLER - INTEL 8259

FEATURES OF 8259:

1. It is programmed to work with either 8085 or 8086 processor.

2. It manage 8-interrupts according to the instructions written into its control registers.

3. Vector an interrupt request anywhere in the memory map. However all eight interrupts are spaced at the interval of either four or eight locations.

4. The interrupts can be masked or unmasked individually.

5. The 8259s can be cascaded to accept a maximum of 64 interrupts.6. Resolve eight levels of interrupt priorities in a variety of modes, such

as fully nested mode, automatic rotation mode, and specific rotation mode.

7. Read the status of pending interrupts, in-service interrupts, and masked interrupts.

8. Can be set up to accept either the level-triggered or the edge-triggered interrupt request.

FUNCTIONAL BLOCK DIAGRAM OF 8259:

It has eight functional blocks. They are,• Control logic • Read Write logic • Data bus buffer • Interrupt Request Register (IRR) • In-Service Register (ISR) • Interrupt Mask Register (IMR) • Priority Resolver (PR) • Cascade buffer.

FUNCTIONAL BLOCK DIAGRAM OF 8259:

• The processor uses the RD (low), WR (low) and A0 to read or write 8259.

• The 8259 is selected by CS (low).

• The IRR has eight input lines (IR0-IR7) for interrupts. When these lines go high, the request is stored in IRR. It registers a request only if the interrupt is unmasked.

• Normally IR0 has highest priority and IR7 has the lowest priority. The priorities of the interrupt request input are also programmable.

• First the 8259 should be programmed by sending Initialization Command Word (ICW) and Operational Command Word (OCW). These command words will inform 8259 about the following,    – Type of interrupt signal (Level triggered / Edge triggered). – Type of processor (8085/8086). – Call address and its interval (4 or 8) – Masking of interrupts. – Priority of interrupts. – Type of end of interrupts.

• The interrupt mask register (IMR) stores the masking bits of the interrupt lines to be masked. The relevant information is send by the processor through OCW.

• The in-service register keeps track of which interrupt is currently being serviced.

• The priority resolver examines the interrupt request, mask and in-service registers and determines whether INT signal should be sent to the processor or not.

• The cascade buffer/comparator is used to expand the interrupts of 8259.

• In cascade connection one 8259 will be directly interrupting 8086 and it is called master 8259.

• To each interrupt request input of master 8259 (IR0-IR7), one slave 8259 can be connected. The 8259s interrupting the master 8259 are called slave 8259s.

FIGURE 9-11 8259A initialization control word format. (Courtesy of Intel Corporation.)

John UffenbeckThe 80x86 Family: Design, Programming, and Interfacing, 3e

Copyright ©2002 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

FIGURE 9-13 8259A operation control word format. (Courtesy of Intel Corporation.)

John UffenbeckThe 80x86 Family: Design, Programming, and Interfacing, 3e

Copyright ©2002 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458

All rights reserved.

KEYBOARD/DISPLAY CONTROLLER - INTEL 8279

• The INTEL 8279 is specially developed for interfacing keyboard and display devices to 8085/8086/8088 microprocessor based system.

The important features of 8279 are,

• Simultaneous keyboard and display operations. • Scanned keyboard mode. • Scanned sensor mode. • 8-character keyboard FIFO. • 16-character display. • Right or left entry 16-byte display RAM. • Programmable scan timing.

Block diagram of 8279:

Keyboard section:• The keyboard section consists of eight return lines RL0 - RL7 that can be

used to form the columns of a keyboard matrix. • It has two additional input : shift and control/strobe. The keys are

automatically debounced. • The two operating modes of keyboard section are 2-key lockout and N-key

rollover. • In the 2-key lockout mode, if two keys are pressed simultaneously, only the

first key is recognized. • In the N-key rollover mode simultaneous keys are recognized and their codes

are stored in FIFO. • The keyboard section also have an 8 x 8 FIFO (First In First Out) RAM. • The FIFO can store eight key codes in the scan keyboard mode. The status of

the shift key and control key are also stored along with key code. The 8279 generate an interrupt signal when there is an entry in FIFO. The format of key code entry in FIFO for scan keyboard mode is,

• In sensor matrix mode the condition (i.e., open/close status) of 64 switches is stored in FIFO RAM. If the condition of any of the switches changes then the 8279 asserts IRQ as high to interrupt the processor.

Display section:

• The display section has eight output lines divided into two groups A0-A3 and B0-B3.

• The output lines can be used either as a single group of eight lines or as two groups of four lines, in conjunction with the scan lines for a multiplexed display.

• The output lines are connected to the anodes through driver transistor in case of common cathode 7-segment LEDs.

• The cathodes are connected to scan lines through driver transistors.

• The display can be blanked by BD (low) line. • The display section consists of 16 x 8 display RAM.

The CPU can read from or write into any location of the display RAM.

Scan section:• The scan section has a scan counter and four

scan lines, SL0 to SL3. • In decoded scan mode, the output of scan

lines will be similar to a 2-to-4 decoder. • In encoded scan mode, the output of scan

lines will be binary count, and so an external decoder should be used to convert the binary count to decoded output.

• The scan lines are common for keyboard and display.

• The scan lines are used to form the rows of a matrix keyboard and also connected to digit drivers of a multiplexed display, to turn ON/OFF.

CPU interface section:• The CPU interface section takes care of data transfer

between 8279 and the processor. • This section has eight bidirectional data lines DB0 to

DB7 for data transfer between 8279 and CPU. • It requires two internal address A =0 for selecting

data buffer and A = 1 for selecting control register or status register of 8279.

• The control signals WR (low), RD (low), CS (low) and A0 are used for read/write to 8279.

• It has an interrupt request line IRQ, for interrupt driven data transfer with processor.

• The 8279 require an internal clock frequency of 100 kHz. This can be obtained by dividing the input clock by an internal prescaler.

• The RESET signal sets the 8279 in 16-character display with two -key lockout keyboard modes.

• Two ways of interfacing I/O devices– Serial

• Cheaper• Slower

– Parallel• Faster• Expensive • Limited to small distances

Basic requirements in serial I/O• Interfacing requirements

– Read , write , address decoding – peripheral i/o , memory mapped i/o.– Can be interfaced either program control (status check) or interrupt

control

• Alphanumeric codes -ASCII• Transmission format

– Synchronous, Asynchronous – 1 Start bit , character byte , 2 stop bits– Simplex , Duplex – half duplex, full duplex– Baud – bits /second 50 – 9600 baud . With 1200 baud - .83ms bit time

• Error checks in data communication – parity , checksum , CRC

• Data communication over telephone lines –MODEM , FSK, PSK

• Standards in serial I/O – RS232

• Software vs. programmable hardware approaches

Two basic modes of data transmission

• Serial transmission– Asynchronous

• Each byte is encoded for transmission– Start and stop bits

• No need for sender and receiver synchronization

– Synchronous• Sender and receiver must synchronize

– Done in hardware using phase locked loops (PLLs)

• Block of data can be sent• More efficient

– Less overhead than asynchronous transmission

• Expensive

Asynchronous transmission

Software controlled asynchronous serial I/O

• The program should perform the following tasks

1. Output a start bit2. Convert the character to be sent in a stream of

serial bits with appropriate delay3. Add parity information if necessary4. Output one or two stop bits

• Serial data transmission• Serial data reception – flow charts

8085 serial I/O lines :SID & SOD• SOD

– SIM Instruction

– RIM Instruction

D7 SDE D5 D4 D3 D2 D1 D0

For INTERRUPTS

SDE –Serial Data Enable

1 - Enable SOD

0 – Diable SOD

Serial output data (SOD)

Not used

D7 D6 D5 D4 D3 D2 D1 D0

Interrupt StatusSerial input data (SID)

INTERFACING WITH INTEL 8251A (USART)

• The 8251A is a programmable serial communication interface chip designed for synchronous and asynchronous serial data communication.

• It supports the serial transmission of data.

• It is packed in a 28 pin DIP.

Functional block diagram of 8251The functional block diagram of 8251A consists five

sections. They are:• Read/Write control logic

– Interfaces the chip with MPU– Determine the functions according to the control word– Monitors data flow

• Transmitter – Converts parallel word received from MPU into serial bits – Transmits serial bits over TXD line to a peripheral.

• Receiver – Receives serial bits from peripheral– Converts serial bits into parallel word– Transfers the parallel word to the MPU

• Data bus buffer • Modem control

– Used to establish data communication modems over telephone line

Functional block diagram of 8251A-USART

Read/Write control logic:• The Read/Write Control logic interfaces the 8251A with CPU,

determines the functions of the 8251A according to the control word written into its control register.

• It monitors the data flow.

• This section has three registers and they are control register, status register and data buffer.

• The active low signals RD, WR, CS and C/D are used for read/write operations with these three registers.

• When C/D is high, the control register is selected for writing control word or reading status word.

• When C/D is low, the data buffer is selected for read/write operation.

• When the reset is high, it forces 8251A into the idle mode.

• The clock input is necessary for 8251A for communication with CPU and this clock does not control either the serial transmission or the reception rate.

• Read/Write Control Logic and Registers • This section includes

R/W Control LogicSix input signalsThree buffer registers

– Data register– Control Register

• 16-bit register• First byte is called mode instruction• Second byte is called command instruction• This register can be accessed an output port

– Status Register• Checks ready status of a peripheral

Transmitter Section• Accepts parallel data and converts it into serial

data • Two registers

Buffer Register • To hold eight bits

Output Register • Converts eight bits into a stream of serial bits

• Transmits data on TxD pin with appropriate framing bits (Start and Stop)

Signals Associated with Transmitter Section

• TxD – Transmit Data – Serial bits are transmitted on this line

• TxC – Transmitter Clock – Controls the rate at which bits are transmitted

• TxRDY – Transmitter Ready – When it is high, it indicates that buffer register is empty – Can be used either to interrupt the MPU or indicate the status – This signal is reset when a data byte is loaded into the buffer

• TxE – Transmitter Empty – Logic 1 on this line indicate that the output register is empty – This signal is reset when byte is transferred from buffer to the

output registers

Transmitter section:• The transmitter section accepts parallel data from CPU and

converts them into serial data.

• The transmitter section is double buffered, i.e., it has a buffer register to hold an 8-bit parallel data and another register called output register to convert the parallel data into serial bits.

• When output register is empty, the data is transferred from buffer to output register. Now the processor can again load another data in buffer register.

• If buffer register is empty, then TxRDY is goes to high.

• If output register is empty then TxEMPTY goes to high.

• The clock signal, TxC controls the rate at which the bits are transmitted by the USART.

• The clock frequency can be 1,16 or 64 times the baud rate.

Receiver Section

• Accepts serial data from peripheral and converts it into parallel data

• The section has two registers – Input Register – Buffer Register

Signals Associated with Receiver Section

• RxD – Receive Data – Bits are received serially on this line and converted

into parallel byte in the receiver input

• RxC – Receiver Clock • RxRDY – Receiver Ready

– It goes high when the USART has a character in the buffer register and is ready to transfer it to the MPU

Receiver Section:• The receiver section accepts serial data and convert them into parallel data

• The receiver section is double buffered, i.e., it has an input register to receive serial data and convert to parallel, and a buffer register to hold the parallel data.

• When the RxD line goes low, the control logic assumes it as a START bit, waits for half a bit time and samples the line again.

• If the line is still low, then the input register accepts the following bits, forms a character and loads it into the buffer register.

• The CPU reads the parallel data from the buffer register.

• When the input register loads a parallel data to buffer register, the RxRDY line goes high.

• The clock signal RxC controls the rate at which bits are received by the USART.

• During asynchronous mode, the signal SYNDET/BRKDET will indicate the break in the data transmission.

• During synchronous mode, the signal SYNDET/BRKDET will indicate the reception of synchronous character.

MODEM Control:

• The MODEM control unit allows to interface a MODEM to 8251A and to establish data communication through MODEM over telephone lines.

• This unit takes care of handshake signals for MODEM interface.

Programming 8251

8251 mode register

7 6 5 4 3 2 1 0 Mode register

Number of Stop bits

00: invalid01: 1 bit10: 1.5 bits11: 2 bits

Parity0: odd1: even

Parity enable0: disable1: enable

Character length

00: 5 bits01: 6 bits10: 7 bits11: 8 bits

Baud Rate

00: Syn. Mode01: x1 clock10: x16 clock11: x64 clock

Programming 8251

8251 command register

EH IR RTS ER SBRK RxE DTR TxE command register

TxE: transmit enableDTR: data terminal ready, DTR pin will be lowRxE: receiver enableSBPRK: send break character, TxD pin will be lowER: error resetRTS: request to send, CTS pin will be lowIR: internal resetEH: enter hunt mode

Programming 8251

8251 status register

DSR SYNDET FE OE PE TxEMPTY RxRDY TxRDY status register

TxRDY: transmit readyRxRDY: receiver readyTxEMPTY: transmitter emptyPE: parity errorOE: overrun errorFE: framing errorSYNDET: sync. character detectedDSR: data set ready

Simple Serial I/O Procedures

Read

start

Check RxRDY

Is it logic 1?

Read data register*

end

Yes

No

* This clears RxRDY

Write

start

Check TxRDY

Is it logic 1?

Write data register*

end

Yes

No

* This clears TxRDY

Errors

– Parity error: Received data has wrong error -- transmission bit flip due to noise.

– Framing error: Start and stop bits not in their proper places.

• This usually results if the receiver is receiving data at the incorrect baud rate.  

– Overrun error: Data has overrun the internal receiver FIFO buffer.

• Software is failing to read the data from the FIFO.