Introduction to VLSI Design, VLSI I, Fall 2011 4. CMOS Transistor Theory 1 4. CMOS Transistor Theory J. A. Abraham Department of Electrical and Computer Engineering The University of Texas at Austin EE 382M.7 – VLSI I Fall 2011 September 7, 2011 ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 1 / 31 Electrical Properties Necessary to understand basic electrical properties of the MOS transistor to design useful circuits Deal with non-ideal devices Ensure that the circuits are robust Create working layouts Predict delays and power consumption As circuit dimensions scale down, electrical effects become more important, even for digital circuits 1.65 GHz square wave from an HDMI Interface (Source: Dunnihoo, EE Times Asia, 8/25/2005) ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 1 / 31 Department of Electrical and Computer Engineering, The University of Texas at Austin J. A. Abraham, September 7, 2011
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Introduction to VLSI Design, VLSI I, Fall 20114. CMOS Transistor Theory 1
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4. CMOS Transistor Theory
J. A. Abraham
Department of Electrical and Computer EngineeringThe University of Texas at Austin
EE 382M.7 – VLSI IFall 2011
September 7, 2011
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 1 / 31
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Electrical Properties
Necessary to understand basic electrical properties of the MOStransistor to design useful circuits
Deal with non-ideal devices
Ensure that the circuits are robust
Create working layouts
Predict delays and power consumption
As circuit dimensionsscale down, electricaleffects become moreimportant, even fordigital circuits
1.65 GHz square wavefrom an HDMI Interface
(Source: Dunnihoo, EE
Times Asia, 8/25/2005)
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 1 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 7, 2011
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The nMOS Transistor
Terminal Voltages
Modes of operation depend on Vg, Vd, VsVgs = Vg − VsVgd = Vg − VdVds = Vd − Vs = Vgs − Vgd
Source and drain are symmetric diffusion terminals
By convention, source is terminal at lower voltage, so Vds ≥ 0
nMOS body is grounded for simple designs; assume source is 0
Three regions of operation: Cutoff, Linear, Saturated
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Modes in nMOS Structure
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 3 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 7, 2011
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nMOS Transistor Operation
Positive voltage on Gate produces electric field across substrate –attracts electrons to the Gate and repels holes
With sufficient voltage, region under Gate changes from p- ton-Type – conducting path between the Source and Drain
Inversion layer is field-induced junction, unlike a PN junctionwhich is metallurgical
Horizontal component of electric field associated with Vds > 0is responsible for sweeping electrons from channel to drain
Threshold Voltage
The gate voltage at which conduction takes place is theThreshold Voltage, Vt
Current flow occurs when the drain to source voltage Vds > 0,and consists almost entirely of majority-carriers (electrons),that flow through the channel
A depletion region insulates the channel from the substrateECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 4 / 31
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Conducting nMOS Transistor
Conduction when Vgs > Vt and Vds > 0No significant current through the substrate because of reversebiased PN junction with the channelAs the voltage from drain to source is increased, the resistivedrop along the channel begins to change the shape of thechannel characteristicAt source end of the channel, the full gate voltage is effectivein inverting the channelAt drain end of the channel, only the difference between thegate and the drain voltage is effective
If Vds > Vgs − Vt, then Vgd < Vt, and the channel is “pincheddown” (the inversion layer no longer reaches the drain)
In this case, conduction is brought about by the driftmechanism of electrons under the influence of positive drainvoltage; as the negative electrons leave the channel, they areaccelerated towards the drain
Voltage across the pinchdown channel tends to remain fixedat (Vgs − Vt), and the channel current remains constant withincreasing Vds
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 5 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 7, 2011
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nMOS Device Behavior
Vgs > Vt, Vds = 0
Saturated Mode(Vds > Vgs − Vt)
Nonsaturated ModeVds < Vgs − Vt
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The pMOS Transistor
Moderately doped n- typesubstrate (or well) in whichtwo heavily doped p+ regions,the Source and Drain, arediffused
Application of a negative gate voltage (w.r.t. source) drawsholes into the region below the gate; channel changes from nto p-type (source-drain conduction path)
Conduction due to holes; negative Vd sweeps holes fromsource (through channel) to drain
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 7 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 7, 2011
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Current in the Channel
In the Linear region, Ids depends on how much charge there is inthe channel and how fast the charge is moving
Channel Charge
MOS structure looks like parallel plate capacitor whileoperating in inversion (Gate – Oxide – Channel)
Qchannel = CV
C = Cg = εoxWL/tox = CoxWL (Cox = εox/tox)
V = Vgc − Vt = (Vgs − Vds/2)− Vt
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Carrier Velocity
Charge is carried by electrons
Carrier velocity ν proportional to lateral E- field betweensource and drain
ν = µE
µ is called mobility
E = Vds/L
Time for carrier to cross channel: t = L/ν
ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 9 / 31
Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 7, 2011
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I-V Characteristics
nMOS Linear I-V
Current can be obtained from charge in channel and the time teach carrier takes to cross
Ids =Qchannel
t
= µCoxW
L(Vgs − Vt − Vds/2)Vds
= β (Vgs − Vt − Vds/2)Vds
nMOS Saturation I-V
If Vgd < Vt, channel pinches off near drain
when Vds > Vdsat = Vgs − VtNow drain voltage no longer increases with current
Ids = β (Vgs − Vt − Vdsat/2)Vdsat
=β
2(Vgs − Vt)2
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Example 1, Cont’d
Vdd = 5V , Vtn = 1V and |Vtp| = 0.7V
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Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 7, 2011
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Example 2
Assume: initial voltage of 0.5V on all the internal nodes
Vdd = 1.0V , Vtn = 0.2V and |Vtp | = 0.2V
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Example 2, Cont’d
Assume: initial voltage of 0.5V on all the internal nodes
Vdd = 1.0V , Vtn = 0.2V and |Vtp | = 0.2V
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Department of Electrical and Computer Engineering, The University of Texas at AustinJ. A. Abraham, September 7, 2011
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Effective Resistance
Resistance of a bar of uniform material
R = ρ×LA =
(ρt
) (LW
)where ρ = resistivity of the materialA = cross-section of the resistort,W = thickness, width of the material
The channel resistance of a MOS transistor in the linearregion, Rc = k
(LW
),
where k = 1µCox(Vgs−Vt)
Resistance values depend on the technology
Obtain the information from the technology files
Sheet resistance (Ω/)Lowest for metal, increases for poly, active, highest for Well
Contact (via) resistance becomes more important asprocesses scale down
Channel (turned-on transistor) on the order of 1000 Ω/ECE Department, University of Texas at Austin Lecture 4. CMOS Transistor Theory J. A. Abraham, September 7, 2011 26 / 31