1 Lucas-Lehmer Primality Tester Presentation 6 March 1st 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design Manager: Prateek Goenka Overall Objective: Modular Arithmetic unit with a creative use This is my presentation, there are others like it but this one is mine
1 Lucas-Lehmer Primality Tester Presentation 6 March 1st 2006 Team: W-4 Nathan Stohs W4-1 Brian Johnson W4-2 Joe Hurley W4-3 Marques Johnson W4-4 Design.
Dec 20, 2015
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1
Lucas-Lehmer Primality TesterPresentation 6March 1st 2006
Team: W-4
Nathan Stohs W4-1
Brian Johnson W4-2
Joe Hurley W4-3
Marques Johnson W4-4
Design Manager:
Prateek Goenka
Overall Objective: Modular Arithmetic unit with a creative use
This is my presentation, there are others like it but this one is mine
2
Status• Finished
– Project Chosen– C simulations– Behavioral Verilog– Structural Verilog– Revised Floor Plan– Schematics ( 98%)
• In Progress– Top Level Simulations– Layout– Layout Simulations
• To Do– Continue Layout– Layout Simulations– Pathmill Simulation on Top Level
3
Design Decisions• Optimization
– Got rid of universal Shifter– Implemented Shifter_Left Shifter_Right– Stressed special cases over universal parts– Cut out 4,000 transistors
4
Transistor Counts (Old)Module Transistor Count
FSM 300
Mod Calc 2440
Counter 1656
Mod Multiply 15302
Mod_Add
Shifters
Registers 1848
Compare for zero 92
Total 21638
5
Transistor Counts (New)Module Transistor Count
Count 2,664
Mod_Multiply 11,120
Mod_Add 1282
Partial Products 8,676
Counter 266
Dff_re (16) 896
Sub_16 704
Compare 36
Mod_P 1,280
Top Level Flops 896
FSM 700
Total 17,400
6
Power ConsumptionModule Power
Count 53.81 uW
Mod_Multiply ?
Mod_Add 128.8 uW
Partial Products 368 uW
Counter 36.77 uW
Dff_re (16) 260 uW
Compare 149.2 pW
Mod_P 397.6 uW
Top Level Flops 39.6 uW
FSM ?
7
Shift_Left
8
9
10
Shift_Right
11
12
13
Mod_P
14
15
16
Partial Product
17
18
19
Pathmill Results
• Shift_Left = .610 ns
• Shift_Right = .610 ns
• Mod_P = .610 ns
• Mod_Add = 8.993 ns
• Partial_Products = 5.135 ns
20
Initial Layout
21
More Layout
22
Block Area Estimates (Old)
Module Area (μm2)
FSM 900
Mod Calc 3500
Counter 6000
Mod Multiply 75000
Registers 3000
Compare for zero 300
Total 88300
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Block Area Estimates (Updated)
Module Area (μm2)
Count 13,200
Mod_Mult 54,500
Sub_16 3,500
Compare 200
Mod_P 6,500
Top Level Flops 4,400
FSM 3,500
24
Updated Floorplan
25
What’s Next
• Continue Layout
• Pathmill Simulations for Top Level
• Simulate Layout
26
Questions?
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