Intel s Low Power Technology With High-K Dielectric Balapradeep Gadamsetti.

Intel’s Low Power Technology

With High-K Dielectric

Balapradeep Gadamsetti

Why this is required? Continuation of Moore’s Law

Transistor scaling with increased performance and Reduced Power Consumption

Introduction Silicon Industry is scaling SiO2 for the

past 15 years and still continuing.

SiO2 is running out of atoms for further scaling but still scaling continues.

What is a Transistor ?

A simple switch- current flows from source to drain when gate is at certainvoltage; otherwise it doesn’t flow

Gate dielectrics (SiO2) are only a few atomic layers thick at this thickness even being insulator current leaks through.

Now Leakage Power became an Issue !!

Seeking new materials to drive Moore’s Law

Replacing SiO2 a challenge?

Materials chosen for replacing SiO2 should be thicker (to reduce leakage power) but should have a “high-K” value.

What is High-K ? A measure of how much charge a material can hold.

“AIR” is the reference with “K=1”.

"High-k" materials, such as hafnium dioxide (HfO2), zirconium dioxide (ZrO2) and titanium dioxide (TiO2) inherently have a dielectric constant or "k" above 3.9, the "k" of silicon dioxide.

Dielectric reduces Leakage power

Problem’s with High-K Threshold Voltage Pinning- high-K and Polysilicon gate are

incompatible due to Fermi level pinning at the High-K and Polysilicon interface which causes high threshold voltages in transistors

Phonon scattering - High-K/ Polysilicon transistors exhibit severely degraded channel mobility due to the coupling of phonon modes in high-K to the inversion channel charge carriers.

Both the above problems limit the transistor switching speed !!!

High-K and PolySi are Incompatible

Mobility degradation in High-k\PolySi

Phonon Scatterings

Solution- Metal Gates

Metal gate electrodes are able to decrease phonon scatterings and reduce the mobility degradation problem.

Challenges with Metal Gates

Requires metal gate electrodes with “CORRECT” work functions on High-K for both nMOS and pMOS transistors for high performance.

Work functions for nMOS and pMOS

Breakthroughs with Metal Gates

N-Type metal and P-Type metal with the CORRECT work functions on high-K have been engineered.

High-K\metal-gate stack achieves nMOS and pMOS channel mobility close to SiO2's.

High-K\metal-gate stack shows significantly lower gate leakage than SiO2.

High-Metal-gate reduces leakage

pMOS mobility graph

nMOS mobility graph

Conclusion Intel achieved 20 percent improvement in

transistor switching speed

Reduced transistor gate leakage by over 10 fold.

Integration of more than 400 million transistors for dual-core processors and more than 800 million for quad-core in Intel® 45nm high-k metal gate silicon technology.

References http://www.intel.com/technology/silicon/hi

gh-k.htm

http://www.physorg.com/news80.html

http://www.eetimes.com/conf/iedm/showArticle.jhtml?articleID=18305166&kc=5012