Documents A flash high-precision Time-to-Digital Converter implemented in FPGA technology Topical Workshop on....

Slide 1A flash high-precision Time-to-Digital Converter implemented in FPGA technology Topical Workshop on Electronics for Particle Physics Paris, 25 September 2009 Paolo…

Documents Fig.2: Carry chain delay line: (a) logic block diagram;

Fig.2: Carry chain delay line: (a) logic block diagram; (b) Layout obtained using a Xilinx Virtex 5 FPGA; (c) simplified block diagram of the Virtex 5 slice. [email protected],…