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Slide 1 High-Speed and Low-Power On-Chip Global Link Using Continuous-Time Linear Equalizer Yulei Zhang 1, James F. Buckwalter 1, and Chung-Kuan Cheng 2 1 Dept. of ECE, 2…

Documents On-Chip Interconnect Trend and Design Optimization Chung-Kuan Cheng UC San Diego, La Jolla, CA.

On-Chip Interconnect Trend and Design Optimization Chung-Kuan Cheng UC San Diego, La Jolla, CA Outlines Global Interconnect Technologies RC Trees and Transmission Lines Prefix…