Technology LOW POWER-AREA DESIGNS OF 1BIT FULL ADDER IN CADENCE VIRTUOSO PLATFORM

1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.4, No.4, August 2013 DOI : 10.5121/vlsic.2013.4406 55 LOW POWER-AREA DESIGNS OF 1BIT FULL…

Documents array multiplier using

ANALYSIS AND MODELING OF LOW POWER ARRAY MULTIPLIERS USING CADENCE VIRTUOSO SIMULATOR IN 45 nm TECHNOLOGY B. VAMSI KRISHNA 1 & K. DHANUNJAYA 2 1 PG Student, Department…