80Z
Z80 Microprocessor- 1 -
Dept. of Information & Communication Myung-Eui Lee
Z80 Microprocessor
80Z
Z80 Microprocessor- 2 -
Z80 CPU
Long life cycle over 30 year Microchip PIC, Motorola 6805, Intel MCS51
Bus master/arbitration Multiprocessor, DMA support
10 addressing modesVarious Interrupts
Maskable, Non-Maskable, Daisy chain
DRAM refresh circuitZ8 Single chip instruction compatible
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Z80 Microprocessor- 3 -
Programming
LanguageMachine Language : binaryAssembly Language : Assembler
• 3 fields : Label, Operation/operand, comments
• Pseudo Instruction : ORG, EQU, DB, DW, DS, ENDHigh Level Language : Compiler
Assembly Language1. Register2. Memory, I/O Address Map3. Addressing Modes
Label : op code operand ; commentspseudo instruction
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Z80 Microprocessor- 4 -
Assembler
SymbolA, B, C, D, E, H, L, AF, BC, DE, HL, IX, IY, SP Z, NZ, C, NC, PO, PE, P, M
Constant/Literal
DirectivesORG, EQU, DB, DW, DS, ENDMacro : savreg
• Macro : Assembly time facility (Preprocessor)• Subroutine : Execution time facility
LD A, 0LD A, FFhLD A, 11110000b LD A, ‘A’
LD A, ‘5’LD A, 5hLD A, (5)
savreg MACROPUSH AFPUSH BCPUSH DEPUSH HLENDM
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Z80 Microprocessor- 5 -
Registers
Main/Alternate RegisterGeneral/Special Purpose Register
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Z80 Microprocessor- 6 -
Register
Main Register : A, F, B, C, D, E, H, LA (ACC) :
• holds the results of arithmetic or logical operations• Input/Output with peripheral devices.
F (Flag) : indicates specific conditions for operations• S (Sign) : 1(-)/0(+)• Z (Zero) : 1(0)/0(others)• H (Half carry) : 1(carry or borrow at bit 3), BCD operation• P/V (Parity/Overflow)
– P (Logical operation) : 1(1's Even parity)/0(Odd)– V (Arithmetic operation) : 1(overflow)/0(normal)
• N (Negation) - 1(sub)/0(add)• C (Carry) - 1(carry or borrow at bit 7)
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Z80 Microprocessor- 7 -
Register
ADD A, B ( A ← A + B )A : Destination (Result), B : SourceFlag
affected according to the result of the operationnot affected
Alternate Register : A', F', B', C', D', E', H', L'EX AF, AF'
• A ↔ A', F ↔ F'EXX
• B ↔ B', C ↔ C', D ↔ D', E ↔ E',H ↔ H', L ↔ L'
0VCNP/VHZS
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Z80 Microprocessor- 8 -
RegisterGeneral purpose Register
8 bit : B, C, D, E, H, L, B', C', D', E', H', L'16 bit : BC, DE, HL, BC', DE', HL'
Special function Register : PC, SP, IX/IY, I, RPC (Program Counter)
• holds the 16-bit address of the current instruction being fetched from memory.
• automatically incremented after its contents have been transferred.
• the new value is automatically placed in the PC when a program jump occurs.
SP (Stack Pointer)• holds the 16-bit address of the current top of a stack (TOS).• the Stack is located anywhere in external system RAM memory. • The external stack memory is organized as a last-in first-out
(LIFO) file. • pushed onto the stack from specific CPU registers (PUSH). • popped off of the stack to specific CPU registers (POP).
• DecrementCALL, PUSH, Interrupt• IncrementRET, POP
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Z80 Microprocessor- 9 -
RegisterSpecial Function Register
Index Registers (IX/IY)• hold a 16-bit base address used in indexed addressing modes. • index register is used as a base to point to a region in memory.• additional byte is to specify a displacement from this base.• greatly simplifies the tables of data.
Interrupt Register (I)• allows interrupt routines to be dynamically located anywhere in
memory.• stores the high order eight bits of the indirect address.• the interrupting device provides the lower eight bits of the
address.Refresh Register (R)
• Used as the memory refresh counter when the DRAM is used for memory.
• The low order 7 bits of R is automatically incremented for each instruction fetch.
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Z80 Microprocessor- 10 -
Register Notations
n : 8 bits immediate datann' : 16 bits immediate datad : displacement (8 bit : -128 ~ +127 )e : effective address (8 bit : -128 ~ +127 )r, r' : A, B, C, D, E, H, Lss : BC, DE, HL, SPpp : BC, DE, IX, SPrr : BC, DE, IY, SPqq : AF, BC, DE, HLb : 0, 1, 2, 3, 4, 5, 6, 7 (bits)cc : Z, NZ, C, NC, PO, PE, P, M (conditions)
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Z80 Microprocessor- 11 -
Instruction Types
8/16 bit Data Transfer (memory and register read/write)
Exchange, Block Transfer and Search8 bit Arithmetic and Logical (16 bit Arithmetic)
General purpose Arithmetic (DAA, CPL, NEG)
CPU Control (CCF, SCF, NOP, HALT, EI, DI, IM)
Rotate and ShiftBit Manipulation (SET, RESET, TEST)
Jump, Call, and ReturnInput/Output
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Z80 Microprocessor- 12 -
Instructions
8 bit Memory Read/WriteLD A, (nn‘) A ← (nn’)
LD (nn‘), A (nn’) ← A
16 bit Memory Read/WriteLD HL, (nn') L ← (nn’), H ← (nn’+1)
LD (nn'), HL (nn’) ← L, (nn’+1) ← H
PUSH qqPUSH HL (SP - 1) ← H, (SP - 2) ← L, SP ← SP - 2
POP qqPOP HL L ← (SP), H ← (SP + 1), SP ← SP + 2
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Z80 Microprocessor- 13 -
Instructions
Subroutine CALL CALL nn‘ (SP - 1)← PCH, (SP - 2) ← PCL, SP ← SP – 2, PC ← nn’
Subroutine RETURNRET PCL ← (SP), PCH ← (SP + 1), SP ← SP + 2
Stack Operation
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Z80 Microprocessor- 14 -
Instructions
LDIHL : source, DE : destination, BC : countOperation (DE) ← (HL), HL ← HL + 1, DE ← DE + 1, BC ← BC - 1
P/V (Parity)• PE (=1) : branch if BC has not been decremented to 0 (BC ≠ 0)• PO (=1) : branch if BC has been decremented to 0 (BC= 0)
Block Transfer• 10 bytes from 4000h to 40A0h
LD HL, 4000hLD DE, 40A0hLD BC, 0Ah
LOOP: LDIJP PE , LOOP
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Z80 Microprocessor- 15 -
Instructions
CPIA : search pattern, HL : memory address, BC : countOperation A – (HL), HL ← HL + 1, BC ← BC - 1
P/V (Parity)• PE (=1) : branch if BC has not been decremented to 0 (BC ≠ 0)• PO (=1) : branch if BC has been decremented to 0 (BC= 0)
Pattern Search• Pattern 23h from 40B0h to 40B9h (10 bytes)
LD A, 23hLD HL, 40B0hLD BC, 10
LOOP: CPIJR Z, FOUNDJP PO, NOFNDJP LOOP;
FOUND: DEC HLNOFND: ;
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Z80 Microprocessor- 16 -
Decimal Adjustment
DAAHexadecimal : CY=0, A=9Bh
Decimal : CY=1, A=01
LD A, 34hLD B, 67hADD B
LD A, 34hLD B, 67hADD BDAA
0011 0100 ( 34h )
+ 0110 0111 ( 67h )
1001 1011 ( 9Bh )
C =0 H=0
1001 1011 ( 9Bh )
+ 0110 0110 ( 66h ) ; adjust 66h
0000 0001 ( 0101 )
C =11 H=1
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Z80 Microprocessor- 17 -
Rotate/Shift
Rotate Left/Right Circular : RLC/RRC
Rotate Left/Right : RL/RR
Shift Left/Right Arithmetic : SLA/SRA
Shift Left/Right Logical : SRL (no SLL = SLA)
b7 b0CYb7 b0CY0
Sign unchanged
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Z80 Microprocessor- 18 -
Jump / Hand AssembleJump types
Absolute Jump : JP nn’Conditional Jump : JP NZ, nn’Relative Jump : JR e
Address Op. Code Instruction0C71 2004 JR NZ, PLAY0C73 CBF9 SET 7, C0C75 3E12 LD A, 12h0C77 E63F PLAY: AND 3Fh -128 ~ +127 → -126 ~ +129
LD A, 0LD B, 3
LOOP: INC A;;
DJNZ LOOP
LD A, 0LD B, 3
LOOP: INC A;
DEC BJR NZ, LOOP
DJNZ e : B ← B -1, if B≠ 0 then PC ← PC + e
JR e : PC ← PC + e ( = e – 2)
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Z80 Microprocessor- 19 -
I/O Read and Write
RST p PCL ← p, PCH ← 0
I/O ReadIN A, (n) A7~ A0← n, A15~ A8← 0, A ← (n)INI A7~ A0← C, A15~ A8← B, (HL) ← (C), B ← B -1, HL ← HL + 1
• C : port #, HL: memory buffer address, B: counterINIR
I/O WriteOUT (n) , A A7~ A0← n, A15~ A8← A, (n) ← AOUTI A7~ A0← C, A15~ A8← B, (C) ← (HL), B ← B -1, HL ← HL + 1OTIR
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Z80 Microprocessor- 20 -
Addressing Mode
1. Implied/Implicit CPL XOR 30h
2. Immediate ADD A, 20h XOR 30h8 bit constant
3. Extended Immediate LD HL, 1234h16 bit constant
4. Register AND B LD A, B
5. Indirect (register indirect) LD A, (BC) LD A, (1234h)
6. Absolute/Direct JP 1234h LD HL, (1234h)16 bit memory address (nn’)
7. Modified Page Zero Addressing RST
8. Relative JR
9. Indexed LD A, (IX + 3)
10. Bit SET 0, A RES 3, (IX + 2)
Addressing Mode Combination
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Z80 Microprocessor- 21 -
Instruction Byte Length
1 byte CPL DAA LD A, B
2 byte CPDR INIR
CP 50h LD B, 5
3 byte AND (IX + 3)
LD HL, 1234h
4 byte LD IX, (1234h)
BIT 1, ( IX + 2 )
Op. CodeOp. Code 2F2F 2727 7878
Op. Code 2Op. Code 1 Op. Code 2Op. Code 1 D9EB D9EB B2ED B2ED
50FE 50FE 0506 0506Operand 1Op. Code 1 Operand 1Op. Code 1
Op. Code 2 Operand 1Op. Code 1 Op. Code 2 Operand 1Op. Code 1 A6 03DD A6 03DD
Operand 1 Operand 2Op. Code 1 Operand 1 Operand 2Op. Code 1 34 1221 34 1221
Operand 1Op. Code 2 Operand 2Op. Code 1 Operand 1Op. Code 2 Operand 2Op. Code 1 3421 12DD 3421 12DD
disp.Op. Code 2 Operand 1Op. Code 1 disp.Op. Code 2 Operand 1Op. Code 1 02CB 4EDD 02CB 4EDD
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Z80 Microprocessor- 22 -
Z80 Overview
Z80 CPU 특징158 Instruction Sets10 Addressing Modes2 Interrupt Inputs
• NMI : Non-Maskable Interrupt• INT : Maskable Interrupt
– Mode 0, 1, 2Alternate Registers2 Index RegistersDRAM Refresh8080 Instruction Compatible
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Z80 Microprocessor- 23 -
I/O Pin Configuration
Address/Data/Control Bus : 40 pins
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Z80 Microprocessor- 24 -
Block Diagram
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Z80 Microprocessor- 25 -
CPU Timing
Instruction Cycle1 Instruction Cycle = 1 ~ 6 Machine Cycle1 Machine Cycle = 3 ~ 6 T Cycle
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Z80 Microprocessor- 26 -
Instruction Cycle
1. Op. Code Fetch = M1
2. Memory Read3. Memory Write4. I/O Read5. I/O Write6. Bus Request / Acknowledge7. INT Request / Acknowledge8. NMI Request / Acknowledge9. HALT Exit
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Z80 Microprocessor- 27 -
Op. Code Fetch = M1
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Z80 Microprocessor- 28 -
Memory Read / Write
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Z80 Microprocessor- 29 -
Input and Output Device Read / Write
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Z80 Microprocessor- 30 -
Bus Request / Acknowledge
* Sampled on the rising edge of the last T clock
* Sampled on the rising edge of each Tx
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Z80 Microprocessor- 31 -
INT Request / Acknowledge
* Sampled on the rising edge of the last T clock
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Z80 Microprocessor- 32 -
NMI Request / Acknowledge
* NMI signal is detected in any timing of each instruction.
* NMI F/F is sampled on the rising edge of the last T clock.
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Z80 Microprocessor- 33 -
HALT Exit
Exit Conditions : INT, NMI, Reset
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Z80 Microprocessor- 34 -
Reset Timing
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Z80 Microprocessor- 35 -
CPU Reset
Cold Reset : Power On Reset (POR)Warm Reset : Reset SwitchSoft Reset : Jump to 0000h
(PC = 0000h)
VIH = 2.0V
Time Period = e-(1/RC)t
Cold Reset
Power-On
Min. 3 Clocks
Warm Reset
Reset S/W
Min. 3 Clocks
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Z80 Microprocessor- 36 -
Bus / Interrupt Request Timing
Bust RequestThe rising edge of the last T clock of any machine cycle.
INT RequestThe rising edge of the last T clock of each instruction.
NMI RequestDetected in any timing of each instructionSampled on the rising edge of the last T clock of each instruction
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Z80 Microprocessor- 37 -
Instruction Cycle Example
LD A, (nn) : LD A, (8123h)1. M1 : Op. Code Fetch M1, RD, MREQ
• Address : 4000h• Data : 3Ah
2. M2 : Memory Read RD, MREQ• Address : 4001h• Data : 23h
3. M3 : Memory Read RD, MREQ• Address : 4002h• Data : 81h
4. M4 : Memory Read RD, MREQ• Address : 8123h• Data : AAh
Memory
Address4000h4001h4002h
8123h
3A2381
AA
ACC
AA
Memory Write = M4LD (8123h), A
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Z80 Microprocessor- 38 -
Instruction Cycle Example
OUT (n), A : OUT (80h), A1. M1 : Op. Code Fetch M1, RD, MREQ
• Address : 4000h• Data : D3h
2. M2 : Memory Read RD, MREQ• Address : 4001h• Data : 80h
3. M3 : I/O Write WR, IORQ• Address : 80h• Data : 55h
Memory
Address4000h4001h
I/O Address80h
D380
ACC
55
I/O
I/O Read = M3IN A, (80h)
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Z80 Microprocessor- 39 -
Pin Functions
Pin Function Summary : p. 8 Tab. 1-2 & p. 28 Tab. 1-2
Address A0 – A15 : output, active high
• 16 bit address for memory ( 64KB )• 8 bit address for I/O ( 256 )• Refresh address during M1 ( A0 – A6 : 7 bit )
Data D0 – D7: input/output, active high
• 8 bit exchange with memory & I/O.• Interrupt vector
RD / WR: output, active low
• Indicates that the CPU wants to read / write data from / to memory or I/O.
M1: output, active low
• together with MREQ, indicates that the current machine cycle is the opcode fetch cycle
• together with IORQ, indicates an interrupt acknowledge cycle.
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Z80 Microprocessor- 40 -
Pin Functions
MREQ : output, active low LD
• indicates that the address bus holds a valid address for a memory read / write operation.
• Also active low during memory refresh ( RFSH ).IORQ : output, active low IN, OUT
• indicates that the lower half of the address bus (A0 – A7) holds a valid I/O address for an I/O read / write operation.
• also generated concurrently with M1 during an interrupt acknowledge cycle.
RFSH : output, active low
• together with MREQ during M1, indicates that the lower seven bits of the system’s address bus (A0 – A7) can be used as a refresh address to the system’s dynamic memories.
I/O Mapped I/O : IntelMemory Mapped I/O : Motorola
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Z80 Microprocessor- 41 -
HALT : output, active low
• indicates that the CPU has executed a HALT instruction..• During HALT, the CPU executes NOPs to maintain memory
refresh.• HALT exit : INT, NMI, RESET
WAIT : input, active low
• This signal indicates to the CPU that the addressed memory or I/O device is not ready for data transfer.
• Always sampled at T2.NMI : input, active low
• higher priority than INT. • always recognized at the end of the current instruction,
independent of the status of the interrupt enable flip-flop (IFF).• automatically forces the CPU to restart at location 0066H.
Pin Functions
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Z80 Microprocessor- 42 -
INT : input, active low
• Acknowledged a INT request at the end of the current instructionif the internal software-controlled interrupt enable flip-flop (IFF) is enabled.
• EI / DI Instruction• Mode 0, 1, 2
BUSREQ : input, active low
• higher priority than NMI and is always recognized at the end of the current machine cycle.
• BUSREQ forces the CPU address bus, data bus, and control signals MREQ, IORQ, RD, and WR to go to a high-impedance state so that other devices can control these lines.
BUSACK : output, active low
• indicates to the requesting device that the CPU address bus, data bus, and control signals MREQ, IORQ RD, and WR have entered their high-impedance states.
• The external circuitry can now control these lines.
Pin Functions
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Z80 Microprocessor- 43 -
RESET : input, active low
• initializes the CPU as follows– Reset the interrupt enable flip-flop ( IFF = 0 )– Clear the PC ( PC = 0000h ) – Clear registers I and R
• sets the interrupt status to Mode 0. • the address and data bus go to a high-impedance state• all control output signals go to the inactive state.• RESET must be active for a minimum of three full clock cycles
before the reset operation is complete.CLK : input
• Normally 5 – 20 Mhz according to data sheetVCC / GND : input
Pin Functions
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Z80 Microprocessor- 44 -
Timer Delay
LD r, n : M = 2, T = 71 T cycle = 1 / clock
10 MHz : 100 ns500 KHz : 2 us
# of T cycle loop countTIMER: LD D, 40H 7 7 x 1TT2: LD E, 10H 7 7 x 64TT1: DEC E 4
NOP 4 18 x 16 x 64 JP NZ, TT1 10DEC D 4 4 x 64NOP 4 4 x 64JP NZ, TT2 10 10 x 64RET 10 10 x 1
20,04920,049 x 100 ns = 2 ms
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Z80 Microprocessor- 45 -
Interrupt
I/O Transfer Modes1. Programmed I/O2. Interrupt driven I/O3. DMA4. I/O Processor
DMA (Direct Memory Access)
A. Transfer between memory and I/OB. Transfer between memoriesC. Transfer between I/O and I/OD. Memory searchE. I/O search
A
B C
D EDMA
Memory
I/O
I/O
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Z80 Microprocessor- 46 -
IFF : Interrupt Flip FlopIFF 1 : Enable/Disable Interrupt RequestIFF 2 : Temporary storage location for IFF1
Interrupt
Action IFF1 IFF2 Comments
CPU ResetDIINT acknowledge
“0” “0” INT Disable
EI “1” “1” INT Enable
RETI N.C N.C No change
RETN IFF2 “1” IFF2 → IFF1 restore
NMI acknowledge “0” IFF1 IFF1 → IFF2 save, INT disable
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Z80 Microprocessor- 47 -
Interrupt
NMINMI cannot be disabled by program.When a NMI has been accepted, the CPU performs the following processing:
• NMI F/F (latch) is set to “1” : refer to NMI cycle• IFF1 is reset to “0” : disable INT• IFF1 is copied into IFF2 : save EI/DI status• PC is saved into the stack : return address• Jump to 66h
RETN instruction performs the followings:• IFF2 is copied into IFF1 : restore• PC is restored from the stack
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Z80 Microprocessor- 48 -
Interrupt
INTINT can be enabled or disabled by program.When a INT has been accepted, the CPU performs the following processing:
• Both IFF1 and IFF2 are reset to “0” : disable nested INT• PC is saved into the stack : return address• Serviced in one of the three modes : 0, 1 and 2• A mode is selected by executing the instruction
– IM0, IM1, IM2
Mode 0The interrupting peripheral device puts a restart instruction (RST) on the data bus.RST p
1 1 t 1 1 1
7 6 5 4 3 2 1 0
t p000 00h001 08h010 10h011 18h100 20h101 28h110 30h111 38h
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Z80 Microprocessor- 49 -
Interrupt
Mode 0 using priority encoder
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Z80 Microprocessor- 50 -
Interrupt
Mode 1Restart from address 0038h
Mode 2Requires a 16-bit interrupt service address
• High order 8 bits = I register LD I, ABh• Low order 8 bits = Z80 family I/O peripheral device IV reg.
msb lsb
16 bit address
I register DATA bus
ABh C0h
Memory
ABC0h
ABC1h
34h
12h
ISR
1234h EI PUSH A : :
: : POP A RETI
high 8 low 8
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Z80 Microprocessor- 51 -
Daisy Chain
Daisy Chain using Mode 2
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Z80 Microprocessor- 52 -
Interrupt
Interrupt Priority Mode Vector AddressReturn
Instruction
NMI 1
2
0066hnone
Mode 0
Mode 1
Instruction from peripheral devices* RST instruction
0038h
Mode 2Indirect 16 bit address specified by * I register : high order* Peripheral device : low order
RETN
INT RETI
Interrupt Summary
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Z80 Microprocessor- 53 -
Minimum Z80 Computer System
CPU, Memory (ROM), I/O (Digital Data)
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Z80 Microprocessor- 54 -
Hardware Interface
Peripheral InterfacePIO, SIO, DMAC, CTC, FDC, HDC, CRTC, ADC/DAC, USB, Ethernet, Bluetooth etc…
CPU
Interface Chip
Peripheral Devices
Address
Data
RD
IORQ
M1
WR
INT
Data
Control
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Z80 Microprocessor- 55 -
Hardware Interface
Interface Chips
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Z80 Microprocessor- 56 -
Microcomputer Design
Memory Interface
Address Map Address Decode
32 K x 8 bitROM
32 K x 8 bitSRAM
Address0000h
7FFFh8000h
FFFFh
A0 - A14
CE
A0 - A14
CE
ROM
SRAM
A0 - A14
A 15
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Z80 Microprocessor- 57 -
ROM / RAM 256 K bit = 32 K Byte x 8 bit
27256 ROM 62256 RAM
Microcomputer Design
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Z80 Microprocessor- 58 -
ROM / RAM Read
Microcomputer Design
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Z80 Microprocessor- 59 -
RAM Write
Microcomputer Design
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Z80 Microprocessor- 60 -
Memory Control Signal
Microcomputer Design
RD
MREQ
WR
MRD
MWR
HHHLH
HHHHL
LHLLH
HLLHL
MWRMRDMREQWRRD
OutputInput
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Z80 Microprocessor- 61 -
Memory Interface Circuit
Microcomputer Design
D0 - D7
A0 - A14
A15
RD
MREQ
WR
(32K)
A0 - A14 D0 - D7
CE
OE
WE
(32K)
A0 - A14 D0 - D7
CE
OE
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Z80 Microprocessor- 62 -
I/O Address Map
Microcomputer Design
Port C82h
Port B81h
Port A80h
Control Port83h
8255 PPI
Counter #28Ah
Counter #189h
Counter #088h
Control Port8Bh
8253 PIT
Control Port85hData Port84h8251 SIO
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Z80 Microprocessor- 63 -
I/O Address Decode
Microcomputer Design
1 1 1
0 0 0
0 0 0
0 0 0
0 0 1
0 1 0
x x x
x x x
b7
b6
b5
b4
b3
b2
b1
b0
80h 88h
84h
G1 Y7
G2A Y6
G2B Y5
Y4
Y3
C Y2
B Y1
A Y0
A7
A6
A5
A4
A3
A2
A1
A0
8253PIT
CS
A1
A0
8251SIO
CS
C/D
8255PPI
CS
A1
A0
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Z80 Microprocessor- 64 -
I/O Control Signal
Microcomputer Design
RD
IORQ
WR
IORD
IOWRHHHLH
HHHHL
LHLLH
HLLHL
IOWRIORDIORQWRRD
OutputInput
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Z80 Microprocessor- 65 -
I/O Interface Circuit
Microcomputer Design
D0 - D7
A2 - A7
A1
A0
RD
IORQ
WR
CS D0 - D7
C/D
RDWR
CS D0 - D7
A1A0
RDWR
CS D0 - D7
A1A0
RDWR
8
6138
DECODER
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Z80 Microprocessor- 66 -
8255 PIO/PPIParallel Input Output / Programmable Peripheral Interface
Group A
Group A
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Z80 Microprocessor- 67 -
8255 PIOPin Configuration
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Z80 Microprocessor- 68 -
8255 PIO
8255 Port Address
8255 I/O ModesMode 0 : Input or Output Only (Unidirectional), No HandshakeMode 1 : Input or Output Only (Unidirectional), HandshakeMode 2 : Input and Output (Bidirectional), Handshake
80h
81h
82h
80h
81h
82h
83h
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Z80 Microprocessor- 69 -
8255 PIOControl Register (83h)
D7 : 1 = Mode & I/O setting / 0 = Port C bit set & resetD6 D5 : Group A Mode Definition
• 0 0 = Mode 0 / 0 1 = Mode 1 / 1 x = Mode 2D4 : Port A I/O Definition
• 0 = Output / 1 = InputD3 : Port C High Order I/O Definition
• 0 = Output / 1 = InputD2 : Group B Mode Definition
• 0 = Mode 0 / 1 = Mode 1D1 : Port B I/O Definition
• 0 = Output / 1 = InputD0 : Port C Low Order I/O Definition
• 0 = Output / 1 = Input
1
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Z80 Microprocessor- 70 -
8255 PIOControl Register (83h)
D7 : 0 = Port C bit set & resetD6 D5 D4 : Don’t CareD3 D2 D1 : Port C bit selection
• 0 0 0 = PC0• 0 0 1 = PC1• 0 1 0 = PC2• 0 1 1 = PC3• 1 0 0 = PC4• 1 0 1 = PC5• 1 1 0 = PC6• 1 1 1 = PC7
D0 : Bit Set / Reset• 0 = Reset / 1 = Set
0
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Z80 Microprocessor- 71 -
8255 PIO
Mode 0 : Basic Input/Output
80h
9Bh
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Z80 Microprocessor- 72 -
8255 PIO
Mode 1 : Strobe Input / Output (Unidirectional)Internal Interrupt Enable Flip/Flop
• INTEA : 1 when the rising edge of ACKA.• INTEB : 1 when the rising edge of STBB.
Port A Output Port B Input
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Z80 Microprocessor- 73 -
8255 PIO
Mode 1 : Port B Input
Mode 1 : Port A Output
STB
IBF
INTR
RD
Port B
D0~D7
WR
OBF
ACK
INTR
D0~D7
Port A
Interrupt condition
Interrupt condition
STB = IBF = 1
OBF = ACK = 1
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Z80 Microprocessor- 74 -
8255 PIO
Mode 1 Combination Example
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Z80 Microprocessor- 75 -
8255 PIO
Port A = Output, Port B = Input
D7 : 1 = Mode & I/O settingD6 D5 : Group A Mode 1 = 0 1D4 : Port A Output = 0D3 : Port C High Order I/O Definition ( PC4, PC5 )
0 = Output / 1 = InputD2 : Group B Mode 1 = 1D1 : Port B Input = 1 D0 : Port C Low Order I/O Definition ( not used x)
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Z80 Microprocessor- 76 -
8255 PIO
Mode 2 : Strobe Bidirectional Input/Output
WR
OBF
ACK
INTR
Port A
STB
IBF
RD
Output
Input
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Z80 Microprocessor- 77 -
8255 PIO
Mode 2 : Strobe Bidirectional Input/OutputPort A only : Port A = Mode 2, Port B = Mode 1 Input
D7 : 1 = Mode & I/O settingD6 D5 : Group A Mode 2 = 1 xD4 : Port A Output = xD3 : Port C High Order I/O Definition = xD2 : Group B Mode 1 = 1D1 : Port B Input = 1 D0 : Port C Low Order I/O Definition = x
80Z
Z80 Microprocessor- 78 -
8251 SIO
Serial Communication System
Network
Network
Null Modem
CPU
SIO
DTE
Terminal Modem
DCE
Modem
DCE
CPU
SIODTE
Terminal
80Z
Z80 Microprocessor- 79 -
8251 SIO
SIO8250 UART : Universal Asynchronous Receiver / Transmitter8251 USART : Universal Synchronous-Asynchronous Receiver / Transmitter
Asynchronous Serial Communication
Synchronous (Clock/Data) Serial CommunicationCharacter OrientedBit Oriented : HDLC (High-level Data Link Control)
80Z
Z80 Microprocessor- 80 -
8251 SIO
Block Diagram
80Z
Z80 Microprocessor- 81 -
8251 SIO
Pin Group1. CPU Interface Pin2. Modem Control Pin3. Transmit & Transmit Control Pin4. Receive & Receive Control Pin
CPU Interface Pin D0 ~ D7, RD, WR, CS, C/D, CLK, RESETCLK : internal timing clock
• must be greater that Baud rate clock (RxC/TxC)– Asynch x1 & Synch mode : 30 배이상– Asynch x16 & Asych x64 mode : 5 배이상
C/D : Control = 1, Data = 0 A0
80Z
Z80 Microprocessor- 82 -
8251 SIO
SIO Port Address
Modem Control PinDTR (Data Terminal Ready) / DSR (Data Set Ready)
• 1. DTR : terminal tells modem ready to send • 2. DSR : modem tells terminal ready to transmit
RTS (Request To Send) / CTS (Clear To Send)• 3. RTS : terminal sets this when ready to send • 4. CTS : modem ready to transmit
– Carrier를상대편 modem에송출하고, 안정되면 CTS=0
85h
85h
84h
84h
Terminal
Modem RTS
CTS
DTR
DSR
80Z
Z80 Microprocessor- 83 -
8251 SIO
Transmit/Receive & Transmit/Receive Control PinTxD / RxD : Transmit / Receive Data LineTxC / RxC : Data Transfer Rate Clock (Ex.= 9600bps)
• x1 : 9600bps x 1= 9.6Khz• x16 : 9600bps x 16 = 153.6Khz• x64 : 9600bps x 64 = 614.4Khz
TxRDY / RxRDY : Ready for Transmit/Receive • Can be used as an interrupt to the CPU• Can be read as a Status Bit (= Polling)• TxRDY pin signal is different from the TxRDY Status Bit.
– TxRDY [Status Bit] = (Transmit Data Buffer Empty)– TxRDY [Pin] = (Transmit Data Buffer Empty) • (CTS = 0) •
(TxEN = 1)
CPU
INTTxRDY
80Z
Z80 Microprocessor- 84 -
8251 SIO
TxEMPTY : No character to send• Can be read as a Status Bit
SYDET / BD• Asynchronous Mode : BD (Break Detect) Output
– Output upon the detection of a “break” character– Command Register : SBRK command
• Synchronous Mode : SYDET (Synch Detect) Input/Output– Internal Synchronous : output
» sync characters are received and synchronized– External Synchronous : synch input
» start receiving data characters.Vcc / GND
80Z
Z80 Microprocessor- 85 -
8251 SIO
Asynch Transmit Timing
SIO Register : Data Register / Control RegisterData Register : Data Input (84h) / Data Output (84h)
80Z
Z80 Microprocessor- 86 -
8251 SIOControl Register
1. Mode instruction (setting of function)2. Command (setting of operation)
Mode Instruction (85h)
Synch
Inhibit
Asynch Synch
80Z
Z80 Microprocessor- 87 -
8251 SIO
Command Register (85h)
1 ... Hunt Mode (Synch)
2 … Normal Operation
80Z
Z80 Microprocessor- 88 -
8251 SIO
Status Register (85h)
Different from TxRDYpin
Refer to the slide # 83
Same as RxRDYpin
Refer to the slide # 84
•Asynch Mode Only.
•Stop bit can not be detected in Synch Mode.
80Z
Z80 Microprocessor- 89 -
8251 SIO
SIO Program Example - 2 stop bit- Odd parity- Parity Enable- 8 bit data- x1 baud rate
- Error reset- RxEn- TxEn
80Z
Z80 Microprocessor- 90 -
8253 PIT/CTC
Timer (Desired Delay)Software TimerHardware Timer
Hardware TimerPIT (Programmable Interval Timer)CTC (Counter Timer Controller)
8253 PITThree independent 16-bit countersSix Programmable Counter ModesBinary or BCD countingMax. Clock : 5~10Mhz
80Z
Z80 Microprocessor- 91 -
8253 PIT
Pin ConfigurationClock, Gate, Out : Timer pinD0-D7, RD, WR, CS, A0, A1 : CPU Interface pin
80Z
Z80 Microprocessor- 92 -
8253 PIT
PIT Port Address
Control Register
88h
89h
8Ah
8Bh
88h
89h
8Ah
Counter 0 Data OUT
Counter 1 Data OUT
Counter 2 Data OUT
Control Register
Counter 0 Data IN
Counter 1 Data IN
Counter 2 Data IN
(8Bh)
80Z
Z80 Microprocessor- 93 -
8253 PITControl Register
SC1 SC0 : Counter Selection• 0 0 = Counter # 0• 0 1 = Counter # 1• 1 0 = Counter # 2• 1 1 = Invalid
RL1 RL0 : Read/Load Format Setting• 0 0 = Counter Latch• 0 1 = Reading/Loading of Least Significant Byte• 1 0 = Reading/Loading of Most Significant Byte • 1 1 = Least Significant Byte first, then Most Significant Byte
M2 M1 M0 : Mode Selection• 0 0 0 = Mode 0 (Interrupt on Terminal Count)• 0 0 1 = Mode 1 (Programmable One-Shot)• x 1 0 = Mode 2 (Rate Generator)• x 1 1 = Mode 3 (Square Wave Generator)• 1 0 0 = Mode 4 (Software Triggered Strobe)• 1 0 1 = Mode 5 (Hardware Triggered Strobe)
BCD : Count Mode Setting• 0 = Binary Count (16-bit Binary)• 1 = BCD Count (4-decade Binary Coded Decimal)
80Z
Z80 Microprocessor- 94 -
8253 PIT
Mode 0 : Interrupt on Terminal CountOUT pin will be initially low after the mode set operation.OUT pin will remain low, after the count is loaded into the counter registerOUT pin will go high and remain high until the counter register is reloaded, when terminal count is reached.
80Z
Z80 Microprocessor- 95 -
8253 PIT
Mode 1: Programmable One-Shot
Mode 2 : Rate Generator
80Z
Z80 Microprocessor- 96 -
8253 PIT
Mode 3 : Square Wave GeneratorEven Number
• Counter decremented by 2Odd Number
• The first clock pulse decrements the count by 1• Subsequent clock pulses decrement the counter by 2• After time out, the output goes low and the full count is reloaded (5)• Subsequent clock pulses decrement the counter by 3.• Subsequent clock pulses decrement the counter by 2.
80Z
Z80 Microprocessor- 97 -
8253 PIT
Mode 4 : Software Triggered Strobe
Mode 5 : Hardware Triggered Strobe
80Z
Z80 Microprocessor- 98 -
8253 PIT
8253 PIT Mode 0 Example“Interrupt on terminal count” after 40usInput CLK = 200 Khz = 5 usCounter Register Value = 8
- Counter 0- LSB first- Mode 0- Binary