Alfons Weber
Towards Electronics for a
Long Baseline Neutrino Detector
Alfons WeberSTFC & University of Oxford
ν
Dec 2007 Alfons Weber 2
Issues Introduction State of the Art
MINOS/OPERA NOVA T2K/MINERVA
Requirements physics photo detectors
R&D needs
Dec 2007 Alfons Weber 3
There are N Detectors At least 2N different electronics have been
used to read them out No unique solution
Solutions have been adapted from existing ASICS driven by cost, timescale, physics. not ideal But get the job done
Introduction
Dec 2007 Alfons Weber 4
Tensions Near Detectors
high rate beam synchronisation limited channel count
Far Detectors low rate no beam signal available huge channel count
Performance high dynamic range, precise timestamps 100% lifetime low cost
Dec 2007 Alfons Weber 5
What the following is about Electronics, need to integrate with
DAQ photo detectors
Photo-detectors PMT, APD, MPPC
DAQ PCs?
Detector scintillator with WLS fibre large PMT arrays?
Dec 2007 Alfons Weber 6
Solution: MINOS ND
Based on existing QIE ASIC dead-timeless for up to 20 μsec (spill)
QIE FADC FIFO
Input current
Analog Voltage
8-bit FADC value
3 bit range code2 bit CAP-ID code
CAP-ID: QIE has 4 copies of current divider/integrator 4 capacitor IDs
Every channel in the detector (9240) produces, every 18.87 nsec:{FADC, RANGE, CAP-ID}1.4fC lowest count sensitivity, 16-bit effective dynamic range Input charge
QIE
out
put v
olta
ge
Dec 2007 Alfons Weber 7
Solution: MINOS ND (II)
Front End(MINDER/MENUS)
Readout(MASTER)
Data Acquisition
AnaloguePMT Pulse
Fast readout of digital data in response to trigger
PVIC Transfers to PCs
Timing System
44 MINDER crates 8 MASTER crates
Dec 2007 Alfons Weber 8
Solution: MINOS FD/OPERA MINOS developed an ASIC chip for PMT
readout with IDEAS 32 channels VA32_HDR11 shaping amplification sample & hold output driver to ADC
Excellent product fast shaping 500 nsec noise < 2 fC linear> 20 pC 6 ASICs multiplexed
onto 1 ADC
Dec 2007 Alfons Weber 9
Trigger-less DAQ system ASIC close to PMT ADC in VME crate fast PVIC-bus to PC trigger farm search for hits correlated in space and time
1
DCPDCP
TP0
TP0TP
N
TPN TP
1
TP1
VARC0
VARC0VARC
1
VARC1VARC
2
VARC2 VARC
0
VARC0VARC
1
VARC1
ROPROP
0
VARC2
VARC2
VME
VFBVFB
2 1 0
DAQLAN
serial
Ether.ROP
ROP
15
TRCTRC
VME
VFBVFB
PVIC
DAQLAN
serial
Ether.
3
40 Mbytes/sPVIC Bus
10-100 Kbytes/s
DAQLAN
VME Readout Crates
0 Optical PVIC Bus
2.5 MB/s
To Persistent StoreTo Dispatcher
DAQLAN
TimingCentral
unitGPS
antenna
TimingPC
TimingPC
Timing System
Timestamp Clock1 sec GPS ticks
DAQLAN
3
TRCTRC
PVIC
2 1 02 1 02 1 0
BRP
BRP
BRP
BRP
PMTsHVHV HV HV
RCRC
2
TriggerProcessors
Branch Readout
Processors
Front End Electronics
• Timing System– Absolute time from GPS
(tabs= 200 nsec)
– optical distribute along large detector (trel= 4 nsec)
Solution: MINOS FD (system)
Dec 2007 Alfons Weber 10
Solution: T2K/280m & MINERVA
8 (15) batches Separated by 540 (241) nsec charge integrated in batches
Bunch Structure
Spill Structure
58ns 58ns
540ns
58ns
540ns
58ns
540ns
58ns
540ns
58ns
540ns
58ns
540ns
58ns
540ns540ns
58ns
2-3.53s
4.2µs 4.2µs 4.2µs
integration resetChip Time Structure
2-3.53s
Dec 2007 Alfons Weber 11
preampvery simplified –
neglecting features not relevant to ND280 operation
integrate/reset
gain = 1 or 4
gain adjust1,2,3,…8
x10
Vth
analogue pipeline
disc. O/P
Qin
discriminator
1pF
3pF
reset
TRIP-t Front-end architecture
only preamp gain affects signal feeding discriminator no fine control (x1 or x4)
discriminator threshold Vth common to all channels on chip
analogue bias settings gain, Vth, etc. programmable via serial interface
Dec 2007 Alfons Weber 12
SiP
M0
TFB0
… SiP
M63
SiP
M0
TFB1
… SiP
M63
SiP
M0
TFB47
… SiP
M63
…
RMM0
TPSPower distribution
Clk
& t
rg
da
ta
CTM
Trig
ge
r P
rimiti
ves
MCM
Co
smic
tr
igg
er
Sp
ill t
rig &
#
GP
S 1
Hz/
10
0M
Hz
(Acc
. R
F)
Clk
& t
rg
FPN
Gig
ab
it/E
the
rne
t
Gig
ab
it/E
the
rne
t
Acronyms:Acronyms:TFB: TFB: TRIP-t front-end boardTRIP-t front-end boardRMM:RMM: r/o merger moduler/o merger moduleCTM:CTM: global trigger moduleglobal trigger moduleMCM:MCM: master clock modulemaster clock moduleSCM:SCM: slave clock moduleslave clock moduleTPS:TPS: TRIP-t power supplyTRIP-t power supplyFPN:FPN: front-end proc. node (PC)front-end proc. node (PC)
SCM
Sp
eci
al
trig
ge
r
Clk & trg
Gigabit/Ethernet Gigabit/
Ethernet
Clk
& t
rg
Solution: T2K (System Overview)
Dec 2007 Alfons Weber 13
Dec 2007 Alfons Weber 14
Dec 2007 Alfons Weber 15
Solution: NOvA
Dec 2007 Alfons Weber 16
Common Thread Different solutions for near and far
detectors developed around different existing ASICs heavy use of FPGAs huge variation in cost
$20 - $300 per channel DAQ and electronics can’t be developed
independently later solutions move towards commercial
back ends
Dec 2007 Alfons Weber 17
Requirements high QE photo detectors
bigger detectors cheaper low noise electronics
low readout thresholds bigger detectors dynamic range
limited? 1:1000 Timing
O(1nsec) low trigger threshold low and high rate environment
Dec 2007 Alfons Weber 18
Requirements (II) Will take a long time for community to
settle on detector photo detector requirements
Try to develop multi-purpose ASIC test beam near detector
external trigger, limited lifetime far detector
cheap, scalable, ~100% lifetime, self-triggering
Dec 2007 Alfons Weber 19
Ingredients ADC
1:1000 TDC
1 nsec Trigger
local/global clock distribution cheap HV supply
30-1000 V monitoring commercial interfaces
Dec 2007 Alfons Weber 20
The Pass Resume
Performance is not leading edge Cost is main driving factor multi purpose device
Work needed requirements capture design multi-purpose readout system
Electronics DAQ
Develop ASIC develop test system
Dec 2007 Alfons Weber 21
Who and Where? Who is driving this?
which community physicists vs. electronics engineers
Where can the work be done? major labs Universities
Has to be user driven.
Many questions, few answers.