School of Information Technology and Electrical Engineering
Digital Fibre-Optic System
By
Ng Kok Leong
The School of Information Technology and
Electrical Engineering
The University of Queensland
Submitted for the degree of Bachelor of Engineering (Honours) in
the division of Electrical Engineering
29th October 2003
i
Statement of Original Authorship
STATEMENT OF ORIGINAL AUTHORSHIP
Head of School
School of Information Technology and Electrical Engineering
University of Queensland,
St. Lucia, QLD 4072
Dear Professor Kaplan,
In accordance with the requirements of the degree of Bachelor of Engineering
(Honours) in the division of Electrical Engineering, I submitted the following thesis
entitled
“Digital Fibre Optic Link”.
This thesis was performed under the supervision of Dr. Alekansandar Rakic.
I declare that the work submitted in this thesis is my own, except as acknowledged in
the text and references, and has not been previously submitted for a degree at the
University of Queensland or any other institutions.
Yours faithfully,
______________
Ng Kok Leong
(40217774)
i
Acknowledgenents
ii
ACKNOWLEDGEMENTS
I would like to acknowledge all friends and family who have given me great support
and encouragement throughout the course of my research.
I would also like to express my gratitude to my fellow thesis mates namely, Edmund,
Dani, Dickson, Leong, Tey and Jeff for their guidance and patience in making our
thesis. I would also like to specifically thank Dr. Alekansander Rakic for his
encouragement and guidance
Last but not least, I would like to thank all my friends whom have offered me their
selfless assistance throughout this course. Special thanks to those in particularly for
their utmost assistance and guidance.
Abstract
iii
ABSTRACT
Over the years, optical communication systems have been seen as one of the attractive
solutions to the increasing high data rate in telecommunication systems. There also
has been a tremendous increase in usage of transferring information like Internet and
multimedia applications. As this applications require high gigabyte bandwidths over
distances of hundred of meters, larger bandwidth, shorter interconnection delays,
lower levels of power consumption and smaller channel cross talk compared to
convectional electrical counterparts. By using digital fiber optics, signal consistency is
guaranteed over the entire transmission path. Over short or long distances, video,
audio and data signals arrive at their destination in the same perfect quality as they
originated and best of all it does so for the same price or less than analog systems of
yesterday. Another unique property of fiber optic transmission is its security. Fiber
does not radiate any of the signals it communicates the way copper based
transmissions do. It cannot be proximity monitored nor cause interference to any
adjacent electronic equipment. Sensitive military and corporate applications are now
widely deploying fiber for even the shortest transmission distances. It is also used in
many applications such as high speed cable internet access and optical storage
systems.
Contents
IV
CONTENTS STATEMENT OF ORIGINAL AUTHORSHIP........................................................... I ACKNOWLEDGEMENTS.......................................................................................... II ABSTRACT.................................................................................................................III
Contents ........................................................................................................................................IV Figures............................................................................................................................................V List of Tables ................................................................................................................................VI
CHAPTER 1 INTRODUCTION ............................................................................1 1.1 DESCRIPTION OF A DIGITAL FIBRE-OPTIC LINK SYSTEM........................1 1.2 AIMS........................................................................................................................2 1.3 OVERVIEW OF THE THESIS...............................................................................2 CHAPTER 2 BACKGROUND...............................................................................3 2.1 OVERVIEW OF OPTIC LINK DESIGN ...........................................................3 2.1.1 Link Design ......................................................................................................4 2.2 OPTICAL SOURCE............................................................................................6 2.2.1 Comparison between LED and Laser Diode ...................................................7 2.2.2 LED .................................................................................................................8 2.3 ADVANTAGES OF FIBRE-OPTIC COMMUNICATIONS [1] .......................9 2.4 OPTICAL MODULE.........................................................................................10 2.4.1 Optical transmitter [5] ....................................................................................11 2.4.2 Optical receiver [5].........................................................................................12 2.4.3 Optical cable ...................................................................................................12 2.5 POWER BUDGET ............................................................................................13 2.6 RISE TIME BUDGET.......................................................................................14 CHAPTER 3 HARDWARE DESIGN AND IMPLEMENTATION.....................17 3.1 OVERVIEW ......................................................................................................17 3.2 HARDWARE IMPLEMENTATION................................................................17 3.2.1 Optical Module (Transmitter/Receiver circuitry)...........................................18 3.3 POWER MEASUREMENT ..............................................................................19 3.3.1 Overview ........................................................................................................19 3.3.2 Attenuation [6]................................................................................................20 3.3.3 Bending Loss [6] ............................................................................................20 3.3.4 Mechanical Misalignment ..............................................................................22 3.4 JITTER TESTING.............................................................................................23 3.4.1 Concept of Jitter..............................................................................................23 3.4.2 Implementation of Jitter..................................................................................26 3.5 USB MODULE......................................................................................................28 3.5.1 Overview..........................................................................................................28 3.5.2 Concept of transmitter link .............................................................................29 3.5.3 Concept of receiver link .................................................................................30 3.6 METHOD OF TRANSMISSION......................................................................31 3.6.1 Line Coding [1] .............................................................................................31 3.6.2 Data coding.....................................................................................................36 3.6.3 Data communication scheme..........................................................................36
Contents
V
3.6.4 Asynchronous Transmission...........................................................................36 3.6.5 Synchronous Transmission.............................................................................37 3.6.4 Parallel to Serial Conversion ..........................................................................38 3.6.5 SHIFT REGISTERS.......................................................................................40 3.6.6 Serial and Parallel Transfers and Conversion.................................................40 3.7 NRZ/RZ CIRCUIT DESIGN.............................................................................41 3.7.1 RZ transmitter module....................................................................................41 3.7.2 Multiplier Circuit............................................................................................42 3.7.3 Return-Zero receiver module..........................................................................44 3.7.4 Software Testing.............................................................................................46 3.7.5 Hardware Testing ...........................................................................................47 CHAPTER 4 SOFTWARE DESIGN AND IMPLEMENTATION ......................49 4.1 OVERVIEW OF SOFTWARE DESIGN..........................................................49 4.2 BER (BIT-ERROR-RATIO) .............................................................................50 4.2.1 Bit Error Ratio................................................................................................50 4.2.2 Bit Error Ratio Tester [12]..............................................................................51 4.3 PSEUDO RANDOM GENERATOR................................................................54 4.3.1 Concept...........................................................................................................54 4.4 EYE DIAGRAM................................................................................................56 4.4.1 Concept...........................................................................................................56 4.4.2 Setup of Eye diagram [16]..............................................................................58 4.5 MASK MEASUREMENT ................................................................................59 CHAPTER 5 PRESENTATION AND DISCUSSION OF RESULTS..................61 5.1 OVERVIEW OF THIS CHAPTER...................................................................61 5.2 POWER MEASUREMENT RESULTS............................................................61 5.3 JITTER RESULTS ............................................................................................61 CHAPTER 6 CONCLUSION AND FUTURE DEVELOPMEMENT .................63 6.1 FURTHER DEVELOPMENT...........................................................................64 REFERENCES ............................................................................................................65 Appendix A – Results and Simulations .......................................................................68 Power measurement .....................................................................................................68 Jitter Measurement (Eye diagram)...............................................................................73 Appendix B –Flowchart of Software Implementation.................................................76 Appendix C – Schematic Drawing ..............................................................................84
List of Figures
V
FIGURES FIGURE 1: GENERIC OPTIC COMMUNICATION SYSTEM [17]..........................2 FIGURE 2: TYPICAL INTERFACE CIRCUIT FOR FIBRE-OPTIC LINK (5MBPS) [3]…...............................................................................................................................4 FIGURE 3: SET-UP OF VPI LINK DESIGN CIRCUIT..............................................6 FIGURE 4: LED/LASER DIODE CONVERTING ELECTRICAL SIGNAL TO LIGHT SIGNAL [2] ......................................................................................................6 FIGURE 5: CURRENT VS. LIGHT OUTPUT ............................................................7 FIGURE 6: RISE TIME BUDGET TIME PERIOD ...................................................15 FIGURE 7: TRANSMITTER MODULE....................................................................18 FIGURE 8: RECEIVER MODULE ............................................................................18 FIGURE 9: BENDING OF FIBRE..............................................................................21 FIGURE 10: LATERAL DISPLACEMENT (AXIAL) [6].........................................22 FIGURE 11: VARIABLE OPTICAL ATTENUATOR..............................................23 FIGURE 12: CALCULATION OF JITTER [13]........................................................24 FIGURE 13: BLOCK DIAGRAM OF JITTER CIRCUIT .........................................26 FIGURE 14: PCB CIRCUIT OF JITTER ...................................................................26 FIGURE 15: GENERATION OF JITTER WAVEFORM..........................................27 FIGURE 17: CONCEPT OF TRANSMITTER LINK ................................................30 FIGURE 18: CONCEPT OF RECEIVER LINK.........................................................30 FIGURE 19: LINE CODING PATTERN ...................................................................32 FIGURE 20: RZ MODULATION...............................................................................32 FIGURE 21: NRZ MODULATION............................................................................32 FIGURE 22: RZ SIGNAL GENERATION ................................................................33 FIGURE 23: RETURN-ZERO CODING (RECEIVER) ............................................34 FIGURE 24: GENERATION OF NRZ SIGNAL ......................................................35 FIGURE 25: RECEIVING NRZ SIGNAL..................................................................36 FIGURE 26: ASYNCHRONOUS TRANSMISSION [7]...........................................37 FIGURE 28: PARALLEL AND SERIAL COMMUNICATION [7] .........................38 FIGURE 29: PARALLEL TO SERIAL CONVERSION [8]......................................39 FIGURE 30: SHIFT REGISTER [8] ...........................................................................39 FIGURE 31: PARALLEL TO SERIAL CONVERSION TIMING DIAGRAM [8] ..39 FIGURE 32: CIRCUIT DESIGN FOR RETURN-ZERO TRANSMITTER MODULE. ...................................................................................................................41 FIGURE 33: MULTIPLEXER CIRCUIT ...................................................................43 FIGURE 35: ILLUSTRATION OF RZ INPUT AND OUTPUT................................45 FIGURE 36: ILLUSTRATION OF SOFTWARE DESIGN.......................................46 FIGURE 37: ILLUSTRATION OF HARDWARE TESTING CIRCUIT ..................47 FIGURE 38: OUTPUT DIAGRAM OF OSCILLOSCOPE........................................47 FIGURE 39: OVERVIEW OF SOFTWARE DESIGN ..............................................49 FIGURE 40: BASIC BIT ERROR RATIO TESTER..................................................51 FIGURE 41: PSEUDO RANDOM GENERATOR REGISTER WITH FEEDBACK [12]…...........................................................................................................................54 FIGURE 42: AN IDEALIZED EYE DIAGRAM [16]................................................56 FIGURE 43: CONCEPT OF AN EYE DIAGRAM [12] ............................................57 FIGURE 44: DEFINITION OF Q FACTOR [20].......................................................57 FIGURE 45: EYE DIAGRAM SET-UP......................................................................58
List of Figures
VI
FIGURE 46: CONCEPT OF MASK TESTING [21]..................................................59 FIGURE A-1: BIT ERROR RATIO AGAINST RECEIVER INPUT POWER.........68 FIGURE A-2: NO. OF BIT ERRORS AGAINST RECEIVER INPUT POWER......69 FIGURE A-3: LATERAL MISALIGNMENT AGAINST OPTICAL POWER LOSS…........................................................................................................................70 FIGURE A-4: BIT ERROR RATE AGAINST LATERAL MISALIGNMENT........71 FIGURE A-4: OPTICAL POWER LOSS AGAINST BENDING RADIUS OF CURVATURE .............................................................................................................71 FIGURE A-5: 0% JITTER...........................................................................................73 FIGURE A-6: 0.17 % JITTER.....................................................................................73 FIGURE A-7: 0.23% JITTER......................................................................................74 FIGURE A-8: 0.3% JITTER........................................................................................74 FIGURE A-9: 0.4% JITTER........................................................................................74 FIGURE A-10: BER RATIO VS JITTER COMPARE ..............................................75 FIGURE B-1: FLOWCHART OF TRANSMITTER MODULE................................76 FIGURE B-2: FLOWCHART OF RECEIVER MODULE ........................................77 FIGURE B-3: PSEUDO RANDOM GENERATOR FLOWCHART.........................78 FIGURE B-4: FLOWCHART OF BERT TESTING ..................................................79 FIGURE B-5: BER TESTER SCREEN SHOT...........................................................80 FIGURE B-6: FILE TRANSFER PROGRAM SCREEN SHOT................................80 FIGURE B-7: GUI FOR TRANSFERRING FILE .....................................................81 FIGURE B-8: GUI FOR TRANSMITTER PC ...........................................................81 FIGURE B-9: ATTENUATION HELP MENU..........................................................82 FIGURE B-10: JITTER HELP MENU .......................................................................82 FIGURE B-11: TRANSMITTER/RECEIVER HELP MENU....................................82 FIGURE B-12: EYE DIAGRAM HELP MENU ........................................................83 FIGURE C-1: PCB OF RZ-TRANSMITTER.............................................................84 FIGURE C-2: SCHEMATIC OF RZ-TRANSMITTER .............................................84 FIGURE C-2: SCHEMATIC OF RETURN-ZERO MODULE (RECEIVER)...........85 FIGURE C-3: PCB OF RZ-RECEIVER .....................................................................85 FIGURE C-4: EYE DIAGRAMS FOR BER RATIO .................................................86 FIGURE C-5: SIMULATED VPI BER VS RECEIVED POWER.............................86
List of Tables
VI
LIST OF TABLES
TABLE 1: COMPARISON OF LED AND LD [3].......................................................8 TABLE 2: FUNCTION TABLE OF MONSTABLE VIBRATOR ............................27 TABLE 3: TRUTH TABLE OF RZ TRANSMITTER MODULE.............................42 TABLE 4: ASCII TABLE [15]...................................................................................55 TABLE A-1: OUTPUT POWER (DBM) VS. NRZ/RZ (NO. OF BITS) ...................68 TABLE A-2: UPWARD ALIGNMENT MEASUREMENT......................................69 TABLE A-3: DOWNWARD ALIGNMENT MEASUREMENT ..............................69 TABLE A-4: LATERAL ALIGNMENT MEASUREMENT.....................................70 TABLE A-5: BENDING RADIUS MEASUREMENT DATA..................................71
Chapter 1: Introduction
- 1 -
1
INTRODUCTION 1.1 Description of a Digital Fibre-Optic Link system
The fibre optic link system is similar in concept to any type of communication
system. Information source provides an electrical signal to a transmitter comprising an
electrical stage which drives an optical source to give modulation of the lightwave
carrier. The optical source provides the electrical-optical conversion maybe either a
semiconductor laser or light emitting diode (LED). The transmission medium consists
of an optical fibre cable and the receiver consists of an optical detector which drives a
further electrical stage and hence provides demodulation of the optical carrier. A
transmission link is a point to point line that has a transmitter on one end and a
receiver on the other, as shown in figure 1. [1]
Chapter 1: Introduction
- 2 -
Optical Transmitter
OpticalReceiver
Input
CommunicationChannel
Output
Figure 1: Generic optic communication system [17]
1.2 Aims
The aim of this thesis is to design and build an inexpensive low bit-rate digital link
(1Mbps) as a scaled down model of a 1Gbps digital fibre-optic link. This link will be
used as a demonstrator for principles of digital optical communications for students to
perform a number of measurement techniques commonly used in digital optical
communication system.
1.3 Overview of the thesis
Chapter 1 as stated above serves as a general introduction to digital fibre-optic communication. Chapter 2 provides the background of the thesis, a basic introduction of the link, type of source used, as well as the advantages of using the digital fibre link. Chapter 3 will emphasis on the hardware design implementation of a computer controlled optical transmitter/receiver of this link, including NRZ/RZ, power measurement and jitter testing modules.
Chapter 4 shows the method of implementing the software modules such as BER testing, MCU controller and the pseudo random generator
Chapter 5 discusses the results measuring power attenuation, BER ratio and jitter testing.
Chapter 6 concludes the thesis with a final regard to the findings and suggests improvements for future development.
Chapter 2: Background
- 3 -
2
BACKGROUND 2.1 Overview of Optic Link Design The design of an optical link involves many interrelated variables among the fibre,
source, and photodetector operating characteristics, so that the actual link design and
analysis may require several iterations before they are completed satisfactorily. Since
performance and cost constraints are very important factors, components are chosen
wisely to ensure the desired performance level can be met over the expected system
lifetime without over specifying the component characteristics.
The following key system requirements are needed in analysing a link:
1. The desired (or possible) transmission distance
2. The data rate or channel bandwidth
3. The bit-error rate (BER)
Chapter 2: Background
- 4 -
2.1.1 Link Design
The work will include a preliminary design of a low bit-rate digital link (1MB/s) as a
scaled down model of a 1GB/s digital fiber optic link. The design is based on a
Transistor-Transistor Logic (TTL) Compatible HFBR-1412 transmitter and HFBR-
2412 receiver from Agilent Technologies. The wide bandwidth of the transmitter and
receiver allows high speed fiber optic links to be built at lower prices than formerly
possible. It will also include a simulation and final design of the link in Virtual
Photonics Suite.
The typical optical communication system consists of a transmitter, optical source,
transmission media, a detector and a receiver. In such a system, transmitter is one of
the key components, when it performs as the interface between electronics and the
emitters.
Figure 2: Typical interface circuit for fibre-optic link (5Mbps) [3]
In order to pass electrical information through a fiber, an optical transmitter, is used to
convert electrical impulses into modulated light, which is then launched, or focused,
by the transmitter into the fiber.
The transmitter generally consists of a silicon integrated circuit that converts input
voltage levels from a computer, into current pulses. These current pulses, in turn,
drive a light-emitting diode (LED). The output light from the diode is then focused by
one or more lenses into the fiber. The link budget makes it possible to calculate how
far the link will carry signals without a repeater in attenuation limited systems or how
many connectors and splices can be used at a given distance in dispersion-limited
links [4]. Another aspect of the link will be the consideration of choosing the type of
fiber.
In view of the fact that the system is used for laboratory usage, the length of the link
will be short. Therefore all-plastic fiber which is a multi-mode is used because it’s
Chapter 2: Background
- 5 -
cheaper to make and easier to handle. Since all-plastic fiber has a large core and
cladding diameters, there is a reduced requirement for a buffer jacket for fiber
protection and strengthening. Its large size allows easier coupling of light into the
fiber from a multi-source source. But the optical transmission is restricted so it has
limited use in communications applications [1].
Demountable fibre connectors are more difficult to achieve than optical fibre splices.
This is because they must maintain similar tolerance requirements to splices in order
to couple light between fibres efficiently, but they must accomplish it in a removable
fashion. The connector design must allow for repeated connection and disconnection
without problems of fibre alignment, which may lead to degradation in the
performance of the transmission line at the joint.
In order to maintain an optimum performance, the connection must also protect the
fibre ends from damage that may occur due to handling (connection and
disconnection), must be insensitive to environmental factors (eg. Moisture and dust)
must cope with tensile load on the cable. Additionally the connector should ideally be
a lost cost component that can be fitted with relative ease. Hence optical fibre
connectors may be considered in three major areas:
• The fibre termination, which protects and locates the fibre ends;
• The fibre end alignment to provide optimum optical coupling;
• The outer shell, which maintains the connection and the fibre alignment,
protects the fibre ends from the environment and provides adequate strength at
the joint.
Use of index matching material in the connector between two jointed fibres can
increase light transmission while keeping dust and dirt away from the fibres.
The design is using ST series multimode fibre connector which exhibits an optimised
cylindrical sleeve with a cross section designed to expand uniformly when the ferrules
are inserted. Hence, the constant circumferential pressure provides accurate alignment
even when the ferrule diameters differ slightly. In addition, the straight ceramic
ferrule may be observed which contrasts with the stepped ferrule.
The average loss obtained using this connector with multimode graded index fibre
(i.e. core/cladding 62.5/ µ125 m) was 0.22db with less than 0.1dB change in loss after
1000 reconnections.
Chapter 2: Background
- 6 -
2.1.2 VPI Simulation
Figure 3: Set-up of VPI link design circuit
The VPI software is used to simulate the exact link of our link design. From the figure
above, we set the following parameters:-
Fiber length 1000m
Drive current 60mA
Bit rate 5Mbit/sec
The interpretation of results is shown in appendix C.
2.2 Optical Source Light emitters are a key element in any fiber optic system. This component converts
the electrical signal into a corresponding light signal that can be injected into the
fiber. The light emitter is an important element because it is often the most costly
element in the system, and its characteristics often strongly influence the final
performance limits of a given link. There are two types of light emitters in widespread
use: laser diodes and light-emitting diodes (LEDs).
.
Figure 4: LED/Laser diode converting electrical signal to light signal [2]
Chapter 2: Background
- 7 -
Both devices work by emitting photons as electrons fall from the conduction to the
valence bands, the essential difference being that the laser diode gives rise to
stimulated emission, whereas LEDs work solely by spontaneous emission.
LEDs and laser diodes are complex semiconductors that convert an electrical current
into light. The conversion process is fairly efficient in that it generates little heat
compared to incandescent lights. LEDs and laser diodes are of interest for fiber optics
because of five inherent characteristics:
1. Overall small size
2. High radiance (i.e., they emit a lot of light in a small area.)
3. Small emitting area (The area is comparable to the dimensions of optical fibers.)
4. Very long life
5. Can be modulated (turned on and off) at high speeds.
2.2.1 Comparison between LED and Laser Diode
The LED outputs light that is approximately linear with the drive current. Nearly all
LEDs exhibit a “drop” in the curve as shown in Figure 3a. This nonlinearity in the
LED limits its usefulness in analog applications. The droop can be caused by a
number of factors in the LED semiconductor physics but is often largely due to self-
heating of the LED chip.
All LEDs drop in efficiency as their operating temperature increases. Thus, as the
LED is driven to higher currents, the LED chip gets hotter causing a drop in
conversion efficiency and the droop apparent in Figure 3a. LEDs are typically
operated at currents to about 100 mA peak. Only specialized devices operate at higher
current levels.
.
Figure 5: Current vs. Light Output
Chapter 2: Background
- 8 -
LED is directly modulated with electrical digital signals as optical sources in
transmitters are modulated by optical modulators biased with the electrical digital
signals. The electrical digital signals are rectangular pulsed signals and thus the
modulated optical signals are also rectangularly shaped pulses. Photodiodes receive
the transmitted signals and covert them into electrical signals. When the electrical
input is a digital signal, the signal can directly be transmitted to the receiver. The
electrical input, however, is ordinarily an analog signal proportional to the intensity of
the information such as voice. The received optical digital signal is converted into an
electrical digital and then translated into an electrical analog signal (decoding). The
coding signals are generally multiplexed and then the LEDS is modulated by the
multiplexed signals. The multiplexed signals transmitted are demultiplexed before
decoding. The signal multiplication results in the increase in bit-rate of the signal
transmitted, and thus the LED is required to operate at high frequencies. Table 1
summarizes the comparison of LEDs and Lasers.
Table 1: Comparison of LED and LD [3]
2.2.2 LED
Optical power generated by a LED must be coupled into a fibre to be useful for
communication purposes. Parameters that determine the efficiency of the coupling are
the ratio of the fibre core area to the active area to the active area of the LED, the fibre
NA, and the far-field emission pattern of the light source. Far-field characteristics of
light sources were discussed in detail. If the fibre core is significantly larger than the
active area of the source, focusing optics can be used to increase the coupling
efficiency. Without such optics, the coupling efficiency for surface emitting LED is
proportional to the square of the fibre NA. Thus one desires fibres with a large NA to
Chapter 2: Background
- 9 -
increase the coupling efficiency between the LED and the fibre. However, the pulse
spreading associated with modal distortion also increases proportional to the square of
the fibre NA.
Low bit rate applications uses generally use a large NA and large core diameter fibre.
Long haul, moderate to high bit rate systems use the smaller core, lower NA fibre.
Temperature influences the output power of an LED through its effects on the internal
quantum efficiency of the device, which decreases exponentially with increasing
temperature. The modulation bandwidth of LEDs and laser diodes depends on the
electrical characteristics of the driving circuit and the carrier recombination lifetimes.
Light-emitting diodes are often used for low-cost, short-distance local area network
(LAN) connections. Disadvantages, however, preclude use of the LED as a
transmitter for telecommunications systems: its broad spectral bandwidth allows the
coexistence of many optical modes, and it cannot operate at wavelengths of the
second and third optical windows.
Communication using an optical carrier wave guided along a glass fibre has a number
of attractive features. Furthermore, the advances in the technology to date have
surpassed even the most optimistic predictions, creating additional advantages. The
list below summarizes one of the many advantages.
2.3 Advantages of fibre-optic communications [1]
i. Low transmission loss
The development of optical fibres over the last twenty years has resulted in
production of optical fibre cables which exhibit very low attenuation or
transmission loss in comparison with the best copper conductors.
ii. Small size and weight
Optical fibres have very small diameters as such they are far smaller and much
lighter even if they are covered with protective coatings. This is a tremendous
boost towards easing of duct congestion in cities.
Chapter 2: Background
- 10 -
iii. Electrical isolation
Optical fibres which are fabricated from glass, or sometimes a plastic polymer, are
electrical insulators and therefore unlike their counterparts, they do not exhibit
earth loop and interface problems.
iv. Large bandwidth
The optical carrier frequency yields a far greater potential transmission bandwidth
than metallic cable systems. Information-carrying capacity of optical fibre system
has proved far superior to the best copper cable systems. By comparison the losses
in wideband coaxial cable systems restrict the transmission distance to only a few
kilometres at bandwidths over one hundred megahertz.
v. System reliability
These features involves stem from the low loss property of optical fibre cables
which reduces the requirement for intermediate repeaters to boost the transmitted
signal strength. Hence with fewer repeaters, system reliability is generally
enhanced in comparison with conventional electrical conductor systems. It also
tend to reduce the maintenance time and cost.
vi. Low cost
Optical fibres offer potential for low cost line communication compared to those
with copper conductors. Overall system cost when utilizing optical fibre
communication on long-haul links is substantially less than those for equivalent
electrical line systems.
2.4 Optical Module
To fulfil the requirements of a standard optic fibre link, the designer has a choice of
the following components and their associated characteristics:
I. Multimode or single-mode optical fiber
a. Core size
b. Core refractive-index profile
c. Bandwidth or dispersion
d. Attenuation
Chapter 2: Background
- 11 -
II. Led
a. Emission wavelength
b. Spectral line width
c. Output power
d. Effective radiating area
e. Emission pattern
f. Number of emitting modes
III. Photodiode
a. Responsively
b. Operating wavelength
c. Speed
d. Sensitivity
2.4.1 Optical transmitter [5]
The HFBR-1412 fibre optic transmitter contains an 820nm AIGaAs emitter capable of
efficiently launching optical power into four different optical fibre sizes. This allows
the designer flexibility in choosing the fibre size. The HFBR-1412 is designed to
work with HFBR-2412 fibre optic receiver.
The HFBR-1412 transmitter high coupling efficiency allows the emitter to be driven
at low current levels resulting in low power consumption and increased reliability of
the transmitter.
The transmitter’s high coupling efficiency allows the emitter to be driven at low
current levels resulting in low power consumption and increased reliability of the
transmitter. Its high power transmitter is optimized for small size fiber and typically
can launch -15.8 dBm optical power at 60 mA into 50/125 mm fiber and -12 dBm into
62.5/125 mm fiber. The standard transmitter typically can launch -12 dBm of optical
power at 60 mA into 100/140 mm fiber cable. It is ideal for large size fiber such as
100/140 mm. The high launched optical power level is useful for systems where star
couplers, taps, or inline connectors create large fixed losses.
Chapter 2: Background
- 12 -
Consistent coupling efficiency is assured by the double-lens optical system. Power
coupled into any of the three fiber types varies less than 5 dB from part to part at a
given drive current and temperature. Consistent coupling efficiency reduces receiver
dynamic range requirements which allows for longer link lengths.
2.4.2 Optical receiver [5]
The HFBR-2412 fiber optic receiver is designed to operate with the Hewlett-Packard
HFBR-1412 fiber optic transmitter and 62.5/125 mm HCS® fiber optic cable.
Consistent coupling into the receiver is assured by the lensed optical system (Figure
1). Response does not vary with fiber size £ 0.100 mm.
The HFBR-2412 receiver incorporates in integrated photo IC containing a
photodetector and dc amplifier driving an open collector Schottky output transistor.
The HFBR-24X2 is designed for direct interfacing to popular logic families. The
absence of an internal pull-up resistor allows the open-collector output to be used with
logic families such as CMOS requiring voltage excursions much higher than VCC.
Both the open-collector “Data” output Pin 6 and VCC Pin 2 are referenced to “Com”
Pin 3, 7. The “Data” output allows busing, stroking and wired “OR” circuit
configurations. The transmitter is designed to operate from a single
+5 V supply. It is essential that a bypass capacitor (0.1 mF ceramic) be connected
from Pin 2 (VCC) to Pin 3 (circuit common) of the receiver.
2.4.3 Optical cable
In order to plan the use of optical fibres in a variety of line communication
applications, it is necessary to consider the various optical fibres currently available.
The performance characteristics of the various fibre types discussed vary considerably
depending upon the materials used in the fabrication process and the preparation
technique involved.
Multimode step index fibres may be fabricated from either multicomponent glass
compounds or doped silica. These fibres can have reasonably large core diameters and
numerical apertures to facilitate efficient coupling to incoherent light sources such as
Chapter 2: Background
- 13 -
Light Emitting Diodes (LEDs). The performance characteristics of this fibre type may
vary considerably depending on the materials used and the method of preparation.
Plastic-clad fibres are multimode and have either a step index or a graded index
profile. They have a plastic cladding (often a silicone rubber) and a glass core that is
frequently silica. Plastic-clad fibres are generally cheaper than corresponding glass
fibres but have more limited performance characteristics. They are inexpensive and
have a large core (~1mm) for easy coupling. It is simple “crimp and cut” termination
and a wavelength of 650nm. It has major advances in bandwidth and attenuation. It
also has “perception” advantages over glass and copper.
2.5 Power Budget
This purpose of carrying out the power budget is to confirm the transmitter module;
HFBR-1414T is able to the design specifications. From the data sheet, optical power
budget with a 62.5/125 um fiber is 15 dB and fiber attenuation, α is 3 dB/km @
820nm and 25 degrees C. Hence, allowable power loss is 15 dB. Assuming connector
loss is 2 dB each at the transmitter side and receiver side, with system margin of 6 dB,
Loss = 2*connector loss + αL + system margin
15 dB = 2( 2 dB) + αL + 6 dB
αL = 5
L = 1.67km
From the above equation calculation, we can see that power is able to reach the
receiver to maintain reliable performance. For a given set of system requirements, we
carried out a power budget analysis to determine whether the fibre optic link meets
the attenuation requirements or if an amplifier is required for the power level.
Chapter 2: Background
- 14 -
2.6 Rise time budget
The purpose of the rise time budget is to ensure system is able to perform the intended
bit
The power and rise time budget are used to obtain a rough estimate of the
transmission distance and the bit rate.
This analysis is performed to determine the dispersion limitation of the optical fibre
link. The system rise time is given by the equation below:
Tsys2 = Ttx
2 + T modal 2
+ T material2 + T rx
2
= Ttx2 + (440Lq / B)2 + D2σ2L2 + (350 / Brx)2
where L is the transmission length.
Since the transmission medium has length, L of a few metres, the transmitter and
receiver rise time dominates and the system rise time can approximate to be:
Tsys2 = Ttx
2 + T rx2
Ttx ~ 72 nsec
Trx ~ 65 nsec
Therefore Tsys ~ 97 nsec
For NRZ, rise time is given by the equation, Tsys ≤ 0.7/ Bit rate ≤ 0.7 usec
For RZ, rise time is given by the equation, Tsys ≤ 0.35/ Bit rate
≤ 0.35 usec
The calculated rise time is below the 0.35usec for bit rate of 1 Mbits/s. Hence, the
choice of components chosen was adequate to meet the system design criteria.
The purpose of the rise time budget is to ensure system is able to perform the intended
bit
Chapter 2: Background
Fall Time
Width
Period
Figure 6: Rise time budget time p
- 15 -
Amplitud
90
50
10
eriod
Chapter 3: Hardware Design and Implementation
- 16 -
Chapter 3: Hardware Design and Implementation
- 17 -
3
HARDWARE DESIGN AND IMPLEMENTATION 3.1 Overview This chapter will discuss the overall design of hardware design and implementation of
the digital fibre-optic link.
3.2 Hardware Implementation
Basically, there are four PCBs
For hardware design, we have divided into the following modules:-
1) Optical module (transmitter/receiver)
2) Power Measurement module
3) Return-to-Zero module (transmitter/receiver)
4) Jitter source module
5) Variable optical attenuator module
Chapter 3: Hardware Design and Implementation
- 18 -
3.2.1 Optical Module (Transmitter/Receiver circuitry)
Figure 7: Transmitter module This block diagram shown above is the whole view of the transmitter module.
Basically the NRZ/RZ converter, USB module and the jitter circuitry is implemented
in this module.
Figure 8: Receiver module
The block diagram above illustrates RZ to RZ converter module after data has been
transmitted from the transmitter module. It is then converted from serial to parallel
output before sending to the destination PC.
Chapter 3: Hardware Design and Implementation
- 19 -
3.3 Power Measurement 3.3.1 Overview
The design and installation of an optical fibre communication system require
measurement techniques for verifying the operational characteristics of the essential
components. Optical Power measurement is the basis of fibre optic. Optical power is
defined on the basis of electrical power, because electrical power can be precisely
measured through current and voltage. Therefore, all optical power measurements
should be traceable to electrical power measurements. Two types of power
measurements can be distinguished: absolute and relative power measurement.
Relative power measurements are important for the measurement of attenuation, gain,
and return loss. In this thesis, we will be using absolute power measurement is needed
in conjunction with optical sources, detectors and receivers. Two main groups of
optical power meters can be identified: power meters with thermal detectors, in which
temperature rise caused by optical radiation is measured, and photo detectors, in
which the incident photons generate electron-hole pairs. Although photo detector-type
power meters suffer from relatively small wavelength coverage and the need for
absolute calibration, their astounding sensitivity usually makes them the preferred
choice.
A big advantage of photo detectors is that they can measure power levels down to less
than -90dBm. High modulation frequency response is another advantage. They are
usually categorized into small-area power meters and use only when power from a
fibre is to be measured [1].
The AQ1135E Optical Power Meter is used as it easily handles measurement of light
emitted from general-purpose (even plastic) fibres. For glass fibres, the sensitivity of
power measurement is from 0 dBm down to -90 dBm. With a resolution of 1/1000
dB, the unit is ideal for measuring connector insertion loss or the tiniest variations of
power level in optical fibres.
Chapter 3: Hardware Design and Implementation
- 20 -
3.3.2 Attenuation [6]
The attenuation also known as transmission loss of optical fibres has proved to be one
of the most important factors in bringing about their wide acceptance in
telecommunications. As channel attenuation largely determined the maximum
transmission distance prior to signal restoration, optical fibre communications became
especially attractive when the transmission losses of the fibres were reduced below
those of competing metallic conductors. Signal attenuation also known as fibre loss or
signal loss is one of the most important properties of an optical fibre, largely because
it determines the maximum unamplified or repeaterless separation between a
transmitter and receiver. Since amplifiers and repeaters are expensive to fabricate,
install, and maintain, the degree of attenuation in a fibre has a large influence on
system cost. Of equal importance is signal distortion. The distortion mechanisms in a
fibre cause optical signal pulses to broaden as they travel along a fibre. If these pulses
travel sufficiently far, they will eventually overlap with neighbouring pulses thereby
creating errors in the receiver output. The signal distortion mechanisms thus limit the
information-carrying capacity of a fibre. Signal attenuation is usually expressed in the
logarithmic unit of the decibel. The decibel which is used for comparing two power
levels, may be defined for a particular optical wavelength as the ratio of the input
(transmitted) optical power Pi into a fibre to the output (received) optical power Po
from the fibre as:
Number of decibels (dB) = 10log10
o
i
PP
Attenuation of a light signal as it propagates along a fibre is an important
consideration in the design of an optical communication system, since it plays a major
role in determining the maximum transmission distance between a transmitter and a
receiver
3.3.3 Bending Loss [6]
Radiative Losses occur when optical fibre undergoes a bend of finite radius of
curvature. Fibres can be subject to two types of bends: (a) macroscopic bends having
radii that are large compared with the fibre diameter, for example, such as those that
occur when a fibre cable turns a corner, and (b) random microscopic bends of the
fibre axis that can arise when the fibres are incorporated into cables. For macroscopic
Chapter 3: Hardware Design and Implementation
- 21 -
bends, the excess loss is extremely small and is unobservable. As the radius of
curvature decreases, the loss increases exponentially until at a certain critical radius
the curvature loss becomes noticeable. If the bend radius is made a bit smaller once
this threshold point has been reached, the losses suddenly become extremely large.
When a fibre is bent, the field tail on the far side of the center of curvature must move
faster to keep up with the field in the core, seen in Figure 8, for the lowest order fibre
mode. At a certain critical distance x from the center of the fibre, the field tail would
have to move faster than the speed of light to keep up with the core field. Since this is
not possible the optical energy in the field tail beyond x radiates away.
Figure 9: Bending of fibre
The amount of optical radiation from a bent fibre depends on the filed strength x and
on the radius of curvature R. Since higher order modes are bound less tightly to the
fibre core than lower-order modes, the higher-order modes will radiate out of the fibre
first. Thus, the total number of modes that can be supported by a curved fibre is less
than in a straight fibre. Gloge has derived the following expression for the effective
number of modes Neff that are guided by a curved multimode fibre of radius a:
( )2/3
22 321 2 2eff aN N R n kR∞
∞+= − + + ∞∆
where defines the graded-index profile, ∞ ∆ is the core-cladding index difference,
is the cladding refractive index, 2n 2 /k π λ= is the wave propagation constant, and
Chapter 3: Hardware Design and Implementation
- 22 -
( )212N n kaα
α∞ = ∆+
∆ is the total number of modes in a straight fibre.
Another form of radiation loss in optical waveguide results from mode coupling
caused by random microbends of the optical fibre. Microbends are repetitive small-
scale fluctuations in the radius of curvature of the fibre axis, as is illustrated. They are
caused either by nonuniformities in the manufacturing of the fibre or by non uniform
lateral pressures created during the cabling of the fibre. The latter effect is often
referred to as cabling or packaging losses. An increase in attenuation results from
microbending because the fibre curvature causes repetitive coupling of energy
between the guided modes ant the leaky or nonguided modes in the fibre.
3.3.4 Mechanical Misalignment
Radiation losses result from mechanical misalignments because of the radiation cone
of emitting fibre does not match the acceptance cone of the receiving fibre. The
magnitude of radiation loss depends on the degree of misalignment. The three
fundamental types of misalignment between fibres are shown
Longitudinal separation occurs when the fibres have the same axis but have a gap s
between their end faces. Angular misalignment results when the two axes form an
angle so that the fibre end faces are no longer parallel. Lateral displacement takes
place when the axes of the two fibres are separated by a distance d.
The most common misalignment occurring in practice which also causes the greatest
power loss is lateral displacement. We would be performing this test in this thesis.
This axial offset reduces the overlap area of the two fibre-core end faces, as illustrated
in figure 9 and consequently, reduces the amount of optical power that can be coupled
from one fibre into the other.
D
Figure 10: Lateral displacement (Axial) [6]
Chapter 3: Hardware Design and Implementation
- 23 -
Figure 11: Variable Optical Attenuator
To create a fibre loss in the optical fibre, we can adjust the lateral misalignment
distance of the two fibre ends by using the Variable Optical Attenuator (VOA) as
shown in figure above, The optical loss can be measured using the Power meter, while
the bit error ratio can be observed from the BER tester from the GUI. Eye diagrams
can also be captured using the digital Tektronix oscilloscope.
3.4 Jitter Testing
3.4.1 Concept of Jitter
Definition of Unit Interval (UI)
Jitter is traditionally measured in Unit Interval (UI) where one UI corresponds to the
phase deviation of one clock period and is graphically illustrated below. Timing jitter
(also referred to as edge jitter or phase distortion) in an optical fibre system arises
from noise in the receiver and pulse distortion in the optical fibre. If the signal is
sampled in the middle of the time interval (i.e., midway between the times when the
signal crosses the threshold level), then the amount of distortion T∆ at the threshold
level indicates the amount of jitter. Timing jitter is thus given by
Chapter 3: Hardware Design and Implementation
- 24 -
Timing jitter (%) = bT
T∆ x 100%
where T is a bit interval b
Figure 12: Calculation of jitter [13]
Traditionally, the rise time is defined as the time interval between the point where the
rising edge of the signal reaches 10 percent of its final amplitude and the time it
reaches 90 percent of its final amplitude. However, when measuring optical signals,
these points are often obscured by noise and jitter effects. Thus, the more distinct
values at the 20 percent and 80 percent threshold points are normally measured. To
convert from the 20-to-80 percent, one can use the approximate relationship
10 90T − = 1.25 x T 20 80−
A similar approach is used to determine the fall time. Any nonlinearities of the
channel transfer characteristics will create an asymmetry in the eye pattern. If a purely
random data stream is passed through a pure linear system, all the eye openings will
be identical and symmetrical.
Controlling jitter is important because jitter can degrade the performance of a
transmission system introducing bit errors and uncontrolled slips in the digital signals.
Chapter 3: Hardware Design and Implementation
- 25 -
Jitter causes bit errors by preventing the correct sampling of the digital signal by the
clock recovery circuit in a regenerator or line terminal unit. In addition, jitter can
accumulate in a transmission network depending on the jitter generation and transfer
characteristics of the interconnected equipment. Measurement of timing jitter
It basically involves the detection and measurement of timing displacements of the
leading and or trailing edges of digital signals and of the zero-crossings of the
rectangular clock pulses. Measurements may generally be made directly using time or
phase measurement techniques. In most applications, the jitter to be measured will
cover a considerable bandwidth and may contain components down to dc, thus require
extremely good low frequency performance of the equipment.
Jitter can be detected and measured as either phase or frequency modulation, with the
choice of technique whichever was capable of giving the most accurate results.
There are several categories of jitter measurement. Jitter tolerance is defined in terms
of an applied sinusoidal jitter component whose amplitude, when applied to an
equipment input, causes a designated degradation in error performance. Jitter transfer
is the ratio of the amplitude of equipment’s output jitter relative to an applied
sinusoidal jitter component. Jitter generation is a measure of the jitter at equipment’s
output in the absence of an applied input jitter. A related jitter noise measurement is
output jitter, which is a measure of the jitter at a network node or output port [13].
Jitter can also degrade the performance of the fibre-optic system by causing bit errors.
The faster and more complex the system becomes, management of jitter is
increasingly critical. This is because; at higher data rates bits are placed more closely
together.
This thesis is to design and implement a feasible method of jitter testing for the fibre-
optic communication system. Jitter testing will test the designed network under
simulated, non-laboratory conditions. In order to accomplish this, a jitter emulator is
created and integrated into the system. This jitter emulator is designed to be tuneable,
so the amount of jitter injected into the system can be altered. By observing the
reliability of the system and how it behaves under the influence of jitter, designers can
problems that may occur in real world application of the system [14].
Chapter 3: Hardware Design and Implementation
- 26 -
3.4.2 Implementation of Jitter
Source
Figure 13: Block diagram of jitter circuit
Figure 14: PCB circuit of Jitter
Jitter is implemented by introducing this dual retriggerable monostab
74HCT123. It is dual programmed by selection of external resistor
capacitor (Cext). Once triggered, the basic output pulse width may be e
retriggering the gated active high LOW-going edge input (nA) or the ac
going edge input (nB). By repeating this process, the output pulse pe
HIGH, nQ = LOW) can be made as long as desired.
Alternatively an output delay can be terminated at any time by a LOW-go
input nRD, which also inhibits the triggering. An internal connection from
the input gates makes it possible to trigger the circuit by a positive-goin
input nRD as shown in the function table.
Jitter Circuit
le vibrator
(Rext) and
xtended by
tive HIGH-
riod (nQ =
ing edge on
nRD to
g signal at
Chapter 3: Hardware Design and Implementation
Monostable output
Actual data Final Data
0 0 0 0 1 1 1 0 1 1 1 0
Table 2: Function table of monstable vibrator
Jitter Data
F
w
Actual Data
- 27 -
Figure 15: Generation of Jitter waveform
rom this figure 15 above, we can see there is a shift in data from the actual data
aveform. This shift in data is call the Jitter data generated from monostable vibrator.
Figure 16: Monstable vibrator circuit
Chapter 3: Hardware Design and Implementation
- 28 -
In the circuit shown above Figure 16, a Low-to-High transition is used on the
monostable chip.
From the truth table, we can see that if the monotable data and actual data are high
“1”, the final result will become a low “0”. In order to prevent the scenario, either the
resistor or capacitor is changed to adjust the monostable circuit. The basic output pulse width is essentially determined by the values of the external
timing components REXT and CEXT . For pulse widths, when CEXT < 10 000 pF . When
CEXT > 10 000 pF, the typical output pulse width is defined as:
tW = 0.45 x REXT x CEXT (typ.)
where:
tW = pulse width in ns;
REXT = external resistor in kW; CEXT = external capacitor in pF.
In this thesis, the REXT represented by variable resistor so that the length can be adjust
to have different jitter length.
3.5 USB Module
3.5.1 Overview
A USB port is used to establish communication between the PC and the
Transmitter/Receiver modules. The FTDI USB module is implemented in the
transmitter / receiver circuit.
The FT8U245AM provides an easy cost-effective method of transferring data to /
from a peripheral and a host P.C. at up to 8 Million bits (1 Megabyte) per second. Its
simple FIFO-like design makes it easy to interface to any PC either by mapping the
device into the Memory / IO map of the CPU, using DMA or controlling the device
via IO ports. To send data from the peripheral to the host P.C. simply write the byte
wide data into the device when the transmitter empty status bit is not active. If the
(384 byte) transmit buffer fills up, the device de-asserts transmit empty in order to
stop further data being written to the device until some of the FIFO data has been
transferred over USB. When the host P.C. sends data to the peripheral over USB, the
Chapter 3: Hardware Design and Implementation
- 29 -
device will assert the receiver full status bit to let the peripheral know that data is
available. The peripheral then reads the data until the receiver full status bit goes
inactive, indicating no more data is available to read. By using FTDI’s virtual COM
Port drivers, the peripheral looks like a standard COM Port to the application at its
fastest rate regardless of the application’s baud rate setting [10].
Since the USB modules has parallel output and the link in only a path for the data
signals, 8 bits parallel in/serial out shift registers is use to serialise the data signals at
the transmitter module and 8 bits serial in/parallel out shift registers is use to de-
serialise the output over the receiver module. Micro-controller will be required to
retrieve the data from the USB module clock the shift register on the transmitter
module. Another Micro-controller will also be required to clock the shift register
while retrieving the data via the photo detector and strobe the data to the USB module
into the PC.
3.5.2 Concept of transmitter link
An 8-bit parallel-in/serial-out shift register (74HCT166) is used. It is used to serialize
the parallel data into serial format because there is only one optical path on the fibre
optic link. USB will detect data, USB will send out a “1”. When the controller detects
a “1”, it will strobe the USB module so that data will be sent to the shift register.
The PIC 16F876 microcontroller will also send a start bit to receiver controller. The
controller acts as a clock to the shift register so that parallel data can be sent into the
shift register to ensure it is being moved out in serial then into the LED driver.
When the USBMOD detects data from the computer, the /RXIF pin will send a low to
the micro controller notifying there is data available in the FIFO, which can be read
by stroking RD# low then high again. By doing this, the data from FIFO will be
available at D0 to D7. As the Shift register is directly connected to the USB module,
the data at the USB module will be stored into the shift register.
After receiving the data from the USBMOB2, the PIC microcontroller will send a low
to the CE# pin on the shift register so that the parallel data will be stored into the shift
register. Eight clock pulses will be implemented to push the data out in serial format
out from the shift register.
Chapter 3: Hardware Design and Implementation
USB MOD
Shift Reg MOD
PC
0 1
Start Bit Microcontroller
Figure 17: Concept of Transmitter Link
3.5.3 Concept of receiver link
The concept of the receiver on the PC link is just the inverse concept of the
transmitter. The MCU (PIC16F876) at the receiver will monitor continuously the
inputs until it notes a zero-to-one transition. The MCU will detect the start bit from
the transmitter controller. Controller will clock the shift register 8 times so that data
from the transimpedence circuit will store into the shift register (74HCT164 8-bit
serial-in/parallel-out shift register). When the data is ready in the shift register, the
MCU will strobe the USB module #WR and data will be transmitted into the
destination PC. This process will continue until the module is switched off.
USB MOD
Shift Reg MOD
Microcontroller
PC
Figure 18: Concept of Receiver link
- 30 -
Chapter 3: Hardware Design and Implementation 3.6 Method of Transmission
Either serial or parallel transmission can be used to transmit binary signals. In parallel
transmission, multiple channels are used to transmit several bits simultaneously, while
a single channel is used in serial transmission. Data communication over more than
very short distances is generally serial to reduce the number of channels needed [7].
To ensure that data can be transmitted over the fibre link smoothly, the following
parameters are considered:
• Line coding
• Data coding
• Data communication scheme
• Parallel to Serial Conversion
3.6.1 Line Coding [1]
There is a requirement for redundancy in line coding to provide efficient timing
recovery and synchronization as well as possible suitable shaping of the transmitted
signal power spectral density. Hence the choice of line code is an important
consideration within digital optical fibre system design. Binary line codes are
generally preferred because of the large bandwidth available in optical fibre
communications. In addition, these codes are less susceptible to any temperature
dependence of optical sources and detectors. Under these conditions, low level codes
are more suitable than codes which utilize to provide efficient timing recovery and
synchronization as well as possible suitable shaping.
Main purpose
• Allow receiver to sample the signal at the right time
• Signal to noise ratio at its maximum
• Maintain proper pulse spacing
• To indicate the start and end of each timing interval
- 31 -
Chapter 3: Hardware Design and Implementation
Figure 19: Line coding pattern
Basically, there are two types of two-level binary level codes that can be used for
optical fibre transmission links. They are Return-Zero (RZ) and Non-Return-Zero
(NRZ) format.
Figure 20: RZ Modulation
Figure 21: NRZ Modulation
- 32 -
Chapter 3: Hardware Design and Implementation
Return-Zero Coding (Transmitter)
Return to zero is a class of encoding method in which carrier (voltage or current)
return to zero after each transmission.
In the RZ program, the microprocessor (PIC16F876) chip generates two types of
clock pluses. One of the clock pulses is required for the shift register to serialize the
parallel input from the USB module, another clock pulse is for the RZ module. The
ratio of Shift register clock pulse to RZ clock pulse is 1:2. The flowchart of the
program is shown in Appendix B.
From the flow chart, we can see that there are two RZ clock pulses to one shift
register clock pulse. This is the sequence for one bit RZ transmission. This sequence
will go repeat for 8 times since there are 8 bits in one character. The following shows
the signal generation of one bit.
1 bit
Signal from shift register
Transmitted signal
Data signal return to zero Clock pulse generated for the shift register.
Clock pulse generated for the RZ circuit.
Figure 22: RZ signal generation
From the figure above, we can see that the transmitted signal differs from the shift
register’s signal. Transmitted signal does not remain high throughout the whole period
of the “1’s” from the shift register. This method of transmission is called Return to
Zero digital modulation. It combines with the clock signal into the transmitted signal
which will act as a clock recovery in the receiver circuit. This method uses twice the
- 33 -
Chapter 3: Hardware Design and Implementation
bandwidth that the NRZ method does. Hence, two extra clock pulses would be used
for the purpose for modifying the signal from the shift register.
The first clock will “push” the data signal from the shift register to the RZ circuit. It is
then followed by two clock signals generated for the operation of RZ module. The
first clock pulse will “push the date to the RZ circuit. The 2nd clock pulse will return
the signal to zero in the transmission line.
Return-Zero Coding (Receiver)
Received signal
Start bit
Start Bit detected
Signal fed to the shift register
Signal input starts here
Microprocessor detection circuit
Clock pulse for RZ conversion circuit
Clock pulse for shift register
Figure 23: Return-Zero Coding (R
A start bit will be detected by the PIC microprocessor. I
clock pulse. The first would be use to “push” the signal
will convert RZ signal into NRZ waveform. The secon
- 34 -
1
eceiver)
t will then g
into the RZ
d clock pul
0
01
0 0enerate 2 types of
circuit in which it
se will be used to
Chapter 3: Hardware Design and Implementation read the signal from the serial to parallel shift register. The PIC microprocessor will
eventually generate a clock pulse to the data using USB module from shift register.
Non-Return-Zero Coding (Transmitter)
The transmitter microprocessor programming consists of two programs, RZ and NRZ
module. The flow charts of these two programs are shown in Appendix B.
In the NRZ program, the microprocessor (PIC16F876) generates a type of clock pulse
that is being used for shift register. The purpose of this clock pulse is to serialize the
parallel input from the USB. The serialize data is than feed to the data line for
transmission.
Signal from Shift register
1 bit
Transmitted signal
Clock pulse generated for the shift register.
Figure 24: Generation of NRZ signal
The transmitter signal is the same as the signal generated out from the shift register.
There is no change in the signal generated from the shift register. This NRZ signal
will stay high for the duration of high or “1” as output from the shift register.
Non-Return-Zero Coding (Transmitter)
As the shift register is reading the NRZ signal, it is not necessary to change the input
signal. Thus PIC microprocessor needs to generate only one clock pulse for the shift
register. From the above Figure 25, it shows that when the microprocessor detects a
start bit, it will start to clock the shift register. The time duration for each clock pulse
is approximately one micro second, which is approximately the same clock pulse
generated by the transmitter’s clock. Thus only a clock pulse is needed for the shift
register to record in the data. After collecting all the 8 bits data, the PIC micro
- 35 -
Chapter 3: Hardware Design and Implementation
processor would finally generate a clock pulse to input the data from shift register to
the computer via USB module.
Start bit
Start Bit detected
PIC microprocessor detection
Clock pulse for shift register
Figure 25: Receiving NRZ
3.6.2 Data coding
A data code is standardized relationship between sig
Data codes are also codes character sets or character c
by transmitting binary and text data or by character c
data is usually call binary coding. Character codes
Standard for Information Interchange (ASCII) are m
coding. In this thesis, ASCII coding would be used as
for its internal communication [7].
3.6.3 Data communication scheme
Currently, two types of communication scheme is use
asynchronous transmission and synchronous transmis
and frame format.
3.6.4 Asynchronous Transmission
In asynchronous transmission, the transmit and rece
are set to approximately the same speed. A start bit is
- 36 -
1
signal
nalling elemen
odes. Transmis
odes. Non cha
such as Bau
ore commonly
it is used pres
in data comm
sion dependin
ive clocks are
transmitted a
0
0ts and characters.
sion can be done
racter or alphabet
dot and America
used than binary
ently in computer
unication, namely
g on their timing
free-running and
t the beginning of
Chapter 3: Hardware Design and Implementation each character, and at least one stop bit is sent at the end of character. The stop bit
leaves the line or channel in the mark condition, which represents binary 1, and the
start bit always switches the line to a space (binary 0). The timing remains accurate
throughout the limited duration of the character as long as the clocks at the transmitter
and receiver are reasonably close to the same speed .Figure 25 below shows the
arrangement of bits [7].
Parity Bit (optional)
Start Bit Data Bits (7 or 8 bit) Stop Bit
1 X X X X X X X X 0
Figure 26: Asynchronous transmission [7]
There is no set length of time between characters in asynchronous transmission. The
receiver monitors the line until it receives a start bit. It counts bits, knowing character
length being employed, and after the stop bit, it begins monitor the line again, waiting
stop bit. Parity is a form of error control. Not every bit is transmitted.
The efficiency of the communication system can be defined as
D
T
NNη =
where
η = efficiency
DN = number of data bits
TN = number of total bits
3.6.5 Synchronous Transmission
In synchronous transmission, the transmitter and receiver are synchronized to the
same clock frequency. As start and stop bits are not necessary, synchronous
communication is more efficient than asynchronous Instead, data is sent in blocks that
- 37 -
Chapter 3: Hardware Design and Implementation
- 38 -
are much longer than a single character. Blocks begin with an identifying sequence of
bits that allows proper framing and often identifies the content of the block [7].
Synchronous transmission is more difficult and more expensive to implement than
asynchronous transmission. It is used with higher transfer rates of communication:
Ethernet etc. It is used in fast transfer rates (100kps to 100Mbps). Therefore in this
thesis, asynchronous transmission is preferred [8].
Control Fields
8 bit flag
Figure 27: Block diagram of Synchronous Transmission [8]
DATA Field
Control Fields
8 bit flag
3.6.4 Parallel to Serial Conversion
Internally, the computer uses parallel communication sending at least 8 and often 16
or 32 bits along a bus. On the other hand, most data communication over longer
distances is serial. Thus there is a need to translate between parallel and serial data.
a) Parallel communication
b) Serial communication
Line Drivers/ Receiver
Single data line
Serial to parallel Parallel to serial
Destination
Destination Source
Source 8 or more data line
Figure 28: Parallel and serial communication [7]
Chapter 3: Hardware Design and Implementation
Figure 29: Parallel to serial conversion [8]
Figure 30: Shift register [8]
Figure 31: Parallel to serial conversion timing diagram [8]
- 39 -
Chapter 3: Hardware Design and Implementation
3.6.5 SHIFT REGISTERS
A shift register is a register in which the contents may be shifted one or more places
to the left or right. This type of register is capable of performing a variety of
functions. It may be used for serial-to-parallel conversion and for scaling binary
numbers. Before we get into the operation of the shift register, let's discuss serial-to-
parallel conversion, parallel-to-serial conversion, and scaling [8].
3.6.6 Serial and Parallel Transfers and Conversion
Serial and parallel are terms used to describe the method in which data or information
is moved from one place to another. SERIAL TRANSFER means that the data is
moved along a single line one bit at a time. A control pulse is required to move each
bit
Parallel transfer means that each bit of data is moved on its own line and that all bits
transfer simultaneously as they did in the parallel register. A single control pulse is
required to move all bits.
- 40 -
Chapter 3: Hardware Design and Implementation 3.7 NRZ/RZ Circuit Design
3.7.1 RZ transmitter module
AND Gate
Clock
D
C
Q
D-Latch
Inverter
0
Output
01
Input Signal
D
C
Q
D-Latch
Figure 32: Circuit Design for Return-Zero transmitter module
This module converts the NRZ signals generated from the micro controller,
PIC16F876 chip and convert it to RZ encoding scheme. Clock input is set at 4 Mega
hertz for a 1 Mega byte system. As the output of the PC is Non-Return Zero format,
that’s why only a Return Zero module is required for the circuit. A multiplexer will be
chosen to act as a switch between the two circuits (NRZ/RZ).
The Return Zero transmitter module basically includes the following logic gates
Components • Logic gate D-latch (74HCT175)
• Logic gate AND (74HCT08)
• Logic gate NOT (74HCT04)
• Logic gate OR (74HCT32)
- 41 -
Chapter 3: Hardware Design and Implementation
The MCU which is used for 2 applications: one is to synchronize between the
USBMOB2 and Shift Register, the other is to act as a clocking function in this circuit.
The concept is shown below.
Data of 10110011
Clock Inverted Signal Input Signal Output Signal
1 1 1
0 1 0
1 0 0
1 0 0
1 1 1
0 1 0
1 1 1
0 1 0
1 0 0
1 0 0
1 0 0
1 0 0
1 1 1
0 1 0
1 1 1
Table 3: Truth table of RZ transmitter module
After each bit is input to the logic, 2 clock pulses will change the logic to Return Zero
format. If a “1” is input to the circuit, the 1st clock pulse will output a “1”, however,
the 2nd clock pulse will force the “1” to a “0”. This applies to a “0” when the “0” bit
enters the logic gate. The final output will be a “0” for both 1st and 2nd clock pulse.
3.7.2 Multiplier Circuit
The multiplexer circuit is constructed to switch between NRZ/RZ module.
- 42 -
Chapter 3: Hardware Design and Implementation
RZ Circuit
Figure 33: Multiplexer circuit
From the circuit above, data will be fed from the host PC to both the AND gates.
When the switch is a high “1”, data will flow through the AND gate on the top and
the other AND gate beneath will only output a low “0”. The OR gate will eventually
combine the results and send to the output.
When the switch is a low “0”, data will flow through the AND gate below as the
inverter will invert the “0” to a “1” and the AND gate above will only output a low
“0”. The OR gate will combine the results and send to the output. This multiplexer
circuit is also used in selecting jitter and non-jitter module. The switch is also
connected to the MCU so that it is able to identify which module the user is selecting.
The Flowchart of the micro controller is shown in Appendix B-1. In the flowchart, it
describes how the MCU works in RZ and NRZ mode.
- 43 -
Chapter 3: Hardware Design and Implementation
3.7.3 Return-Zero receiver module
D
C
Q
D -L a tch 0
O u t p ut
O R G a t e
C loc k
01
I np u t S ig na l
Figure 34: Circuit design for Return-Zero receiver module
This module converts RZ signals generated from the transmitter and then converts it
to NRZ encoding scheme as the PC can only recognise NRZ format.
Clock input is set at 4 Mega hertz for a 1 Mega bit system.
The components needed for RZ receiver module is as follows:-
• Logic gate D-latch (74HCT175)
• Logic gate OR (74HCT32)
Basically there is a D-latch and the OR gate. The PIC MCU will also clock the D-
latch.
Each bit will have two clock pulses for them to complete the return zero format. In
this circuit, it will be easily to explain in the truth table.
- 44 -
Chapter 3: Hardware Design and Implementation
Clock D-latch
Signal
Data Signal Output
Signal
Final Data
0 1 1
1 0 1
1
0 0 0
0 0 0
0
0 1 1
1 0 1
1
0 1 1
1 0 1
1
0 0 0
0 0 0
0
0 0 0
0 0 0
0
0 1 1
1 0 1
1
0 1 1
1 1 1
1
Table 4: Truth table of RZ receiver module
Figure 35: Illustration of RZ input and output
- 45 -
Chapter 3: Hardware Design and Implementation
3.7.4 Software Testing
D
C
Q
D -Latch 1
R ece iver Ou tput
O R Ga te
A N D G ate
D
C
Q
D -Latch
Inverter
0
Transm itter Output
01
Input Signa l
D
C
Q
D -Latch
01C lock
B
A
C
Figure 36: Illustration of Software Design
By using the software LogiWorks, we are able to simulate the above hardware design
before hardware implementation.
Signals are input into the two modules using a toggle switch which can be
controlled by the user from Point A.
After going through the RZ module, a RZ encoded signal is produced from the
transmitter output Point B.
This signal is then feed to a module which converts the RZ signal back to the NRZ
module. Lastly the desired ouput is received from the receiver output at Point C.
- 46 -
Chapter 3: Hardware Design and Implementation
3.7.5 Hardware Testing
D
C
Q
D-Latch OR Gate
AND Gate
D
C
Q
D-Latch
Inverter
D
C
Q
D-Latch
Oscilloscope 2
Oscilloscope 1
Function Generator 4MHz
Function Generator 1MHz
Figure 37: Illustration of Hardware testing circuit
Figure 38: Output diagram of oscilloscope
By setting up the above circuit, we are able to capture the waveforms from Figure 38.
It shows the converted NRZ signal into RZ signal.
- 47 -
Chapter 4: Software Design and Implementation
- 49 -
4
SOFTWARE DESIGN AND IMPLEMENTATION 4.1 Overview of Software Design
Receiver module Transmitter module
Optical Link
Driver V-A
LED
Driver A-V
PD RZ/NRZ Module
RZ/NRZ Module
USB Module
RX PC
USB Module
TX PC
Figure 39: Overview of software Design
Chapter 4: Software Design and Implementation
- 50 -
4.2 BER (Bit-Error-Ratio)
4.2.1 Bit Error Ratio
In the simplest sense, the fundamental measure of performance for a digital
communications system is how accurately the receiver can be determines the logic
state of each transmitted bit. This figure of merit is called bit-error ratio, define as
Equation 2: [12]
where BER is the bit error ratio, E(t) is the number of bits received in error over time
t, and N(t) is the total number of bits transmitted in time t. Bit error ratio is a statistical
parameter. The measured value depends on the gating time, t, over which the data is
collected and on the processes casing the errors [12].
The performance of a digital transmission system can be calculated by its bit rate
distance product, i.e. the transmitter-receiver spacing that is feasible at the desired bit
rate. Many parameters influence this system performance; foremost are the available
transmitter power, the required input power at the receiver to obtain the desired bit
error rate (BER), and the overall system loss and bandwidth. The received power is
naturally related to the power launched into the fibre waveguide by the transmitter
and the losses encountered as the optical signal passes through fibres, connectors, and
splices. Bandwidth is determined by the fibre and the type of optical source used. The
loss of each fibre section will be designated as. The difference between the transmitter
power and the receiver sensitivity (at the desired BER) defines the optical link power
budget. In order to maintain the specified BER, the insertion loss between the optical
source and detector must not exceed the power budget value [11].
For errors due primarily to Gaussian noise, relatively stable results are obtained when
the gating time is sufficient to capture on the order of 50 to 100 errors. If the errors
occur in bursts caused by non-random effects such as channel crosstalk or external
interference, this simple measure of BER might not adequately system performance.
Chapter 4: Software Design and Implementation
- 51 -
A bit error ratio of 10-9 has been adopted as the minimum acceptable bit error ratio
for the link.
4.2.2 Bit Error Ratio Tester [12]
Bit error ratio is measured using the Bit Error Ratio Tester (BERT). Two types of bit
error measurements can be conducted. In-service testing is performed on the system
during actual operation to give early warning of problems. In one approach, a single
64kb/s line is taken out of service and a known test pattern injected onto the line. The
error performance of this line can be considered representative of all other lines on the
system.
Out-of service testing involves injecting a known test pattern onto the serial line. The
system cannot carry live traffic during the test, so it is best suited for research and
development or manufacturing test environments. The equipment used for out-of-
service testing is known as a bit-error-ratio tester, or BERT.
The concept behind bit-error-ratio testing is shown as follow:
Figure 40: Basic Bit error ratio tester
The BERT consists of 2 sections: a pattern generator and an error detector. The
pattern generator creates the test pattern together with a separate clock signal at the
selected data rate. This pattern is injected into the system under test and received at
the error detector’s data rate input. The error detector includes it own pattern
generator that produces an exact replica of the known test pattern and a comparator
that checks every received bit against this internally generated pattern. Each time the
received bit differs from the known transmitted bit, an error is logged.
Chapter 4: Software Design and Implementation
- 52 -
The pattern generator and the error detector must operate at identical clock rates and
the phase relationship between them must be stable. The easiest way to ensure this is
to use the pattern generator’s clock as the clock source for the error detector. This is
straightforward enough when the two units are in close physical proximity a direct
electrical connection can be made between them. When they are physically separated,
for example at opposite ends of a transmission link, a direct connection may not be
possible. In this case, the error detector’s clock signal must be recovered directly from
the data.
In general, the exact time delay through the system under test is not known.
Therefore, the error detector must have some condition for automatically
synchronizing its internally generated pattern to the incoming data. This
synchronization process make use of the fact that when the two patterns are out of
sync, the likelihood of a received bit matching the expected but is pure chance and
error ratio is approximately 0.5. So whenever the measured BER exceeds a predefined
threshold, typically set at 0.2, the error detector attempts to resynchronize to the data.
This is done by stepping the phase relationship between the two patterns until a BER
minimum is achieved.
Some pattern generators also include a separate trigger output which produces only a
single pulse at the start of every repetition of the pattern. The trigger output is not
used in BER testing but can be important in eye-diagram analysis.
BER tests may be performed on an entire system or individual network elements. In
the latter case, additional components may be needed to perform the test. For
example, to measure the sensitivity of an optical receiver, the electrical output of the
pattern generator must be applied to a test LED to test the link performance, an optical
receiver must be inserted in front of the error detector.
Launch conditions at the interface between the optical source and fibre waveguide
affect the actual end-to-end insertion loss of a fibre link. Light emitting diodes are
incoherent sources that tend to launch so-called leaky modes and cladding modes into
fibre that may result in a substantial excess loss, over the nominal loss of the fibre.
Excess losses of 3 to 4 dB are not uncommon for surface-emitter LEDs, but are
usually small or even negligible for edge-emitter LEDs and injection laser diodes.
This excess loss usually takes place within meters to hundreds of meters from the
Chapter 4: Software Design and Implementation
- 53 -
source and should be determined experimentally before a power budget analysis takes
place.
A margin in received power can be used to maintain the system BER in the presence
of noise phenomena that are known to occur but difficult to predict quantitatively. A
power budget analysis will determine whether or not a system is loss-limited, that is,
if the received power is sufficient to meet or exceed a BER specification. However, a
power budget analysis does not guarantee a minimum BER performance. System
performance can also be delay distortion limited. Maximum spacing between
transmitter and receiver is limited by excessive pulse broadening in the fibre, which
causes intersymbol interference with the attendant reduction in BER performance.
Effectively, the pulse spreading has lowered the receiver sensitivity and thus the
optical link budget. Eye patterns provide a quick way to check if intersymbol
interference is present. The delay distortion in the fibre is combined with pulse
broadening in the transmitter and receiver to cause the overall intersymbol
interference in the system. There are two sources of delay distortion in fibres: modal
distortion and chromatic dispersion. It is often more convenient to analyse the rise
time in a system than to determine the RMS impulse response. As a rough rule of
thumb, for intersymbol interference to have a negligible influence on receiver
sensitivity in a digital transmission link, the pulse rise time of the system should not
exceed 45% (Gaussian waveform) to 70% (exponential waveform) of the bit period
for Non-Return-Zero (NRZ) pulses. In systems, in which the system rise exceeds 70%
of the bit period, the receiver sensitivity penalty can be a strong function of the
received pulse shape as well as the specific receiver.
In this thesis, the transmitter has to generate a set of pseudo random codes. This is
done in the transmitter’s Graphical User Interface (GUI). User has to select a
character from the keyboard. A series of random characters for e.g. call CHARX is
calculated using a series of formulas preset in the program. The GUI than send this
series of characters into the link.
At the receiver, the user needs to select the same character as the input of the
transmitter. The character is then generated into a series of characters called CHARZ
using the same formula on the receiver. After it receives CHARX from transmitter,
the receiver GUI than uses CHARZ to compared with CHARX. But before it begins
Chapter 4: Software Design and Implementation
- 54 -
comparing, the characters have to be broken up into binary bits. Binary bit CHARX is
than compare with binary bit CHARZ. Error occurs when two bits from CHARX and
CHARZ are different. A graph is being plotted to record the number of number of
errors against the number of data bits.
4.3 Pseudo Random Generator
4.3.1 Concept
Pseudo random binary sequence (PRBS) generator is used to simulate random test
pattern for transmission across the link. It can be generate through hardware and
software. In hardware, it is generated using a train of D type flip – flops with feedback
as shown in the figure above. Error Detector identifies errors from the received data
by comparing it with an exact replica of the known test pattern and records any
differences it found.
Figure 41: Pseudo Random Generator register with feedback [12]
In this thesis, software is being implemented instead of hardware. By using software,
we are able to generate more patterns and it is less costly than using hardware.
Chapter 4: Software Design and Implementation
- 55 -
Table 4: ASCII table [15]
The above ASCII table shows the decimal and hex value of each symbol. In actual
fact, when the “ASCII Data” is being transmitted out of the source PC, the ASCII
character is being transmitted through a decimal value in binary format which has 8
bits of “1” or “0”. Since 128 bit is required for this thesis, 16 characters will be
generated out from a formula which will be implemented over at both transmitter and
receiver. An example of the character is shown below.
E.g. User key in ASCII “!” (From ASCII table, Decimal: 33, Binary 00100001
Formula: Decimal <=128 then
New decimal = Old decimal + 2
If exceed 128, then
New decimal = Old decimal – 101
Flowchart of PRBS is shown in Appendix B-3.
Chapter 4: Software Design and Implementation
- 56 -
4.4 Eye diagram
4.4.1 Concept
For evaluating the digital transmission systems, the eye diagram is the key tool to
estimate the system reliability. The eye diagram is a composite of multiple pulses
captured with a series of triggers based on data clock pulse fed separately into the
scope. The scope overlays the multiple pulses to form the eye diagram [19].
An eye diagram is a composite view of all the bit periods of a captured waveform
superimposed upon each other. In other words, the waveform curve from the start of
period 2 to the start of period 3 is overlaid on the curve from the start of period 1 to
the start of period 2 and so on for all bit periods [16].
Figure 42: An idealized eye diagram [16]
The figure above shows an idealized eye diagram, very straight and symmetrical with
smooth transitions (left and right crossing points) and a large wide open eye to
provide an ideal location to sample a bit. At this point, the waveform should have
settled to its high or low value and is least likely to result in a bit error.
Chapter 4: Software Design and Implementation
- 57 -
Figure 43: Concept of an eye diagram [12]
Figure 44: Definition of Q Factor [20]
Chapter 4: Software Design and Implementation
- 58 -
4.4.2 Setup of Eye diagram [16]
ChannelA
EXTTRIG
PC Optical RX
Eye Diagram Analysis
Oscilloscope
Optical LinkOptical
TX PC
Figure 45: Eye diagram set-up
An eye diagram is generated as shown above figure. The data signal is applied to the
oscilloscope’s vertical input. In our thesis, a digital phosphorous Tektronix 3054B
oscilloscope is used. It has a bandwidth of 500 MHz and a sample rate of 5GS/s on
each channel. The separate trigger signal at data rate is applied to its trigger input.
Ideally, the trigger signal is a square wave at the clock rate of the data.
The oscilloscope triggers on the first clock transition after its trigger circuit is armed.
Upon triggering, it captures whatever data waveform is present at the vertical input
and displays it on the screen. The scope is set for infinite persistence so that the
waveform remains on the screen and subsequent waveforms can continue to add to
the display.
After sending the first bit of waveform, the trigger restarts on the following clock
transition. The data pattern at this instant will most probably be different from the
previous pattern, so the display now shows a combination of two patterns. This
process continues so that eventually, after many trigger events, the entire different
one-zero combinations overlap on the screen as shown in figure 43: concept pattern
Chapter 4: Software Design and Implementation
- 59 -
4.5 Mask measurement
Mask tests are often used in production environments as an alternative to eye
parameter analysis. By comparing an eye diagram against a predefined mask, the
overall quality of the waveform can be assessed in one quick measurement. A mask
consists of two parts, as shown in Figure 45 below.
A set of regions or polygons on the oscilloscope screen are define keep-out areas for
the waveform. Waveforms that intrude into these polygons are counted as mask
violations.
Many masks use an amplitude scale that is defined relative to the mean one and zero
levels of the eye. Others require fixed voltage levels independent of measured signal
levels.
For our thesis, we are unable to show the mask measurement using the Tektronix
oscilloscope, but future work can be included using LabView Software.
Another alternative is to purchase the module from Tektronix Telecommunications
mask testing module (TDS3TMT).
Figure 46: Concept of Mask Testing [21]
Chapter 5: Presentation and Discussion of Results
- 61 -
5
PRESENTATION AND DISCUSSION OF RESULTS
5.1 Overview of This Chapter This chapter will discuss and list out the results of the measurements that we have
experimented.
5.2 Power Measurement Results The results are shown in Appendix A-1-A-4 5.3 Jitter Results The results are shown and explain in Appendix A-5 to A-9
Conclusion and Further Development
- 63 -
6
CONCLUSION AND FUTURE DEVELOPMEMENT
Overall I concluded that that this digital fibre optic link can serve as a good and useful
educational tool for students studying the physics of optic link. The various
measurement techniques carried out in this thesis will help them enhance their
knowledge and gain better understanding in making an efficient digital fibre-optic
link system.
The Optical-fiber transmission is looming as a major innovation in the field of
telecommunications. Its technical feasibility is being demonstrated in many on-going
field experiments and trials. The impact of this new technology upon the
communications field will depend on the economic viability of fiber systems
compared to conventional and alternative systems in various applications.
Advances in very high-speed digital application lines make it necessary to develop
long haul information superhighways cables capable of connecting at high bit-rates.
Conventional copper-cabled networks are stretched to their limits, and fibre optic
transmission is the known for its technology for the future. Optical fibres carry much
Conclusion and Further Development
- 64 -
more information than copper wire. With the available wavelength spectrum of light
divided into a series of parallel channels, thousands of signals can be transmitted
along a single fibre. However, attempts to increase the present transfer rates with
faster electronic circuits, using the existing binary approach of modulation by on-off
keying of the optical signal, lead to signal degradation effects that limit transmission
distances [18].
6.1 Further Development
Presently, the work we have completed so far has not maximised the full performance
of the link. We can change the crystal clock speed from 20 MHz to a 40 MHz.
The jitter was implemented by using data from the PC. We should change measuring
jitter at the clock frequency.
The link can be further improvised by using USB 2.0 instead of USB 1.0. This
increases the speed by 40 times and transfer data up to 480Mb/s. Jitter will also be
implemented at the receiver side with a clock recovery module instead. There is also
no jitter testing module for measuring jitter tolerance and jitter transfer, therefore the
testing of the link performance is greatly reduced.
LabVIEW software would also be used to simulate waveforms and analyse eye
diagrams instead of using the traditional digital oscilloscope. In this way, mask
measurement could also be developed for students to experiment different pre-defined
masks for testing the reliability of the optic fibre link.
The measurement methods used in this thesis did not meet with the current
Synchronous Optical Network (SONET) or International Telecommunications Union
(ITU) standard. Nevertheless, future work can be enhanced by using this standard so
that it will be on par with the current commercial products. Finally, if the above
changes can be met, the link will be served as an excellent commercial product for use
for students doing laboratory experiments.
References
- 65 -
References [1] John M. Senior, “Optical Fibre Communications”, Prentice-Hill Inc., 1999. [2] Force Incorporated, April 2003 (Application Note AN110C),
http://www.forceinc.com [3] Hewlett-Packard, http://www.hp.com, March 2003, [4] McGraw-Hill, Dr Kirk W.Lindstrom, May 2003
http://www.mhest.com/download/255810-Fiber_optic_circuit.pdf [5] Agilent Technologies, “Low Cost Fiber-Optic Links for Digital Applications
up to 155MBd (Application Bulletin 78)”, March 2003, http://www.agilent.com/pub/semiconductor/fiber/ab78.pdf
[6] Gerd Keiser, “Optical Fiber Communication”, 3rd Edition International
Editions, 2000. [7] Roy Blake, “Comprehensive Electronic Communication”, West Publishing
Company, 1997 [8] William Stallings,” Data and Computer communications”. Macmillan, 1991 [9] Integrated Publishing, “Logic families,” July 2003,
http://www.tpub.com/home.htm [10] FTDI Chip, March 2003, http://www.ftdichip.com [11] James C.daly,” Fibre Optics”, CRC press, 1984 [12] Dennis Derickson, “Fibre Optic Test and Measurement,” Prentice Hall, 1998 [13] Agilent Technologies,” Frequency agile jitter measurement system
(Application Note 1267)”, May 2003, http://www.agilent.com [14] D J H, Maclean, “Optical Line Systems”, John Wiley and Sons, 1996
[15] ASCII Table, “ASCII table and Description”, September 2003, http://www.asciitable.com
[16] Agilent Technologies,” Measuring Jitter in Digital Systems (Application note
1448-1”, July 2003, http://www.agilent.com
[17] Govind P.Agrawal, “Fiber-Optic Communication Systems,3rd edition”, John Wiley & Sons, Inc Publication, 2002
References
- 66 -
[ 18] Tingye Li, “The future of optical fibers for data communications”, Bell
laboratories, Crawford Hill Laboratory, Holmdel, N.J. 07733, 1995. [19] Myunghee Lee, “A Quasi-monolithic optical receiver using a standard digital
CMOS technology”, Department of Electrical and Computer Engineering, Georgia Institute of Technology, May 1996.
[20] Anritsu Corporation Measurement Solutions, Q Factor Measurement/Eye
Diagram Measurement, SDH/SONET Pattern Editing (Application Note No. MP1632/1763/1764 soft-E-F-1-(1.00), Last accessed May 2003, http://www.us.anritsu.com/
[21] Michael G.Hart, “Firmware Measurement Algorithms for the HP 83480
Digital Communications Analyzer”, December 1996, http://www.hpl.hp.com/hpjournal/96dec/dec96a2.htm
[[[2
Appendix A – Results and Simulations
- 67 -
APPENDIXES
Appendix A – Results and Simulations
Appendix A – Results and Simulations Power measurement
Results in terms of BIT ERROR RATIO Result in terms of Number of Error Bits Opt Power (dBm) BER (NRZ) BER (RZ) Opt Power (dBm) (NRZ) (RZ)
-24 0 0 -24 0 0 -26 0 0 -26 0 0 -28 0 0 -28 0 0 -30 0 0 -30 0 0 -31 0 0 -31 0 0 -32 0 0 -32 0 0
-32.5 0 1.000E-04 -32.5 0 4 -32.8 7.500E-05 3.500E-04 -32.8 3 14 -33 1.000E-04 8.750E-04 -33 4 35
-33.3 1.750E-04 1.925E-03 -33.3 7 77 -33.5 1.000E-03 4.425E-03 -33.5 40 177 -33.8 2.925E-03 6.700E-03 -33.8 117 268 -33.9 1.305E-02 1.110E-02 -33.9 522 444 -34 2.905E-02 3.955E-02 -34 1162 1582
-34.1 1.260E-01 1.424E-01 -34.1 5040 5694 -34.3 signal lost signal lost -34.3 signal lost signal lost
Table C1 Table C2
Table A-1: Output Power (dBm) vs. NRZ/RZ (No. of Bits) Total number of bits transmitted = 40K Bits
Bit Error Ratio Vs Receiver Input Power
-2.0E-02
0.0E+00
2.0E-02
4.0E-02
6.0E-02
8.0E-02
1.0E-01
1.2E-01
1.4E-01
1.6E-01
-34.5 -34 -33.5 -33 -32.5 -32
Receiver Input Power (dBm)
Bit
Erro
r Rat
io
(NRZ)(RZ)
Figure A-1: Bit Error Ratio against Receiver Input Power
- 68 -
Appendix A – Results and Simulations From the above figure A-1, we can see that the number of error bits increases as the optical power decreases. We can also see that the no. of error bits is the same for both NRZ and RZ condition.
No of Bit Errors Vs Receiver Input Power
0100020003000400050006000700080009000
-24 -30 -32.5 -33.3 -33.9 -34.3Receiver Input Power (dBm)
No
of E
rror
Bits
(NRZ)(RZ)
Figure A-2: No. of bit errors against Receiver Input Power
Displacement Optical Power(dBm) Power Loss BER 0 -23.18 0 0 10 -24.3 1.12 0 20 -24.95 1.77 0 30 -26.04 2.86 0 40 -27.53 4.35 0 50 -30.57 7.39 0 60 -34.86 11.68 40000 70 -41.05 17.87 40000
Table A-2: Upward Alignment Measurement
Displacement Optical Power(dBm) Power Loss BER
0 -23.18 0 0 10 -24.1 0.92 0 20 -25.22 1.12 0 30 -27.56 2.34 0 40 -31.53 3.97 0 50 -40.06 16.88 40000
Table A-3: Downward Alignment measurement
- 69 -
Appendix A – Results and Simulations
Lateral Misalignment Vs Optical Power Loss
02468
101214161820
0 10 20 30 40 50 60 70Lateral Displacement (um)
Opt
ical
Pow
er L
oss
(dB
)
Upward MisalignDownward Misalign
Figure A-3: Lateral Misalignment against Optical Power loss From this graph, we can see that as the lateral misalignments increases, the BER increases.
Upward Misalignment Displacement Optical Power(dBm) Power Loss No of bit errors BER
0 -23.18 0 0 0.00E+00 10 -24.3 1.12 0 0.00E+00 20 -24.95 1.77 0 0.00E+00 30 -26.04 2.86 0 0.00E+00 40 -27.53 4.35 0 0.00E+00 45 -29.05 4.75 0 0.00E+00 50 -30.57 7.39 0 0.00E+00 58 -34 9.7 1582 3.96E-02 60 -34.86 11.68 40000 1.00E+00
Download Misalignment Displacement Optical Power(dBm) Power Loss No of bit errors BER
0 -23.18 0 0 0.00E+00 10 -24.1 0.92 0 0.00E+00 20 -25.22 1.12 0 0.00E+00 30 -27.56 2.34 0 0.00E+00 40 -31.53 3.97 0 0.00E+00 45 -33.87 2.34 268 6.70E-03 50 -40.06 16.88 40000 1.00E+00
Table A-4: Lateral Alignment measurement
From the figure graph below, we can see that as the displacement value for the lateral alignment increases, coupling losses increased, number of bit errors with the Bit error ratio increases too. However optical power decreases.
- 70 -
Appendix A – Results and Simulations
0
0.05
0.1
0.15
0.2
0.25
0 10 20 30 40 50 60
Lateral Misaligment (µm)
BER
(NRZ)(RZ)
Figure A-4: Bit Error Rate against Lateral Misalignment
Bending Radius (mm) Original Power (dBm) Bend Power (dBm) Power Loss (dB) 20 -31.82 -32.75 0.93 18 -31.783 -32.9 1.117 16 -31.75 -33.43 1.68 14 -31.66 -33.6 1.94 12 -31.78 -33.97 2.19 10 -31.71 -34.3 2.59 5 -31.52 -37.27 5.75
Table A-5: Bending Radius measurement data
Power Loss Vs Bending Radius of Curvature
0
1
2
3
4
5
6
7
5 10 12 14 16 18 20
Radius of Curvature (mm)
Opt
ical
Pow
er L
oss
(dB
)
Figure A-4: Optical Power Loss against Bending Radius of Curvature
- 71 -
Appendix A – Results and Simulations
Eye diagram at –24dBm Eye diagram at –31dBm
Eye diagram at –32.5dBm Eye diagram at –33.0dBm
Eye diagram at –33.3dBm Eye diagram at –33.5dBm
- 72 -
Appendix A – Results and Simulations
Eye diagram at –33.9dBm Eye diagram at –34.1dBm
Jitter Measurement (Eye diagram)
Figure A-5: 0% Jitter
Figure A-6: 0.17 % Jitter
- 73 -
Appendix A – Results and Simulations
Figure A-7: 0.23% Jitter
Figure A-8: 0.3% Jitter
Figure A-9: 0.4% Jitter
- 74 -
Appendix A – Results and Simulations
The BER results below shows that RZ module is better than NRZ module. This is
made possible as the D-latched is used to control the clock; data from the clock is
free-running. But In actual fact, NRZ module should be having higher BER ratio from
theory.
Jitter compare 40000 Bits (NRZ/RZ)
-1.00E-020.00E+001.00E-022.00E-023.00E-024.00E-025.00E-026.00E-027.00E-028.00E-029.00E-021.00E-01
0% 10% 20% 30% 40% 50%
Jitter Implementation
Erro
rs o
ccur
NRZ ErrorRZ Error
Figure A-10: BER ratio vs Jitter compare
From the figure above, jitter increases with BER ratio increases linearly.
- 75 -
Appendix B – Flowchart of Software Implementation
- 76 -
Appendix B –Flowchart of Software Implementation
Transmitter Module
Start
Check for RZ/NRZ
selection RZNRZ
No No
Check for data
available?
Check for data
available?
Yes Yes
Clock Shift register
Clock Shift register Clock RZ circuit
Clock RZ circuit
Eighth bit send?
Eighth bit send?
NoYes Yes
Send Stop Bit
Figure B-1: Flowchart of transmitter module
Appendix B – Flowchart of Software Implementation
- 77 -
Receiver Module
Start
Check for RZ/NRZ
selection
Check for start bit
Eighth bit Received?
Trigger USB to read from Shift register
Clock Shift register
Clock RZ circuit
RZ
No
No
Yes
Yes
NRZ
No Check for start bit
Yes
Clock Shift register
Eighth bit Received?
No Yes
Figure B-2: Flowchart of Receiver module
Appendix B – Flowchart of Software Implementation
- 78 -
Pseudo Random Generator
Figure B-3: Pseudo Random Generator Flowchart
Appendix B – Flowchart of Software Implementation
- 79 -
BERT testing
Figure B-4: Flowchart of BERT testing
Appendix B – Flowchart of Software Implementation
- 80 -
Graphical User Interface
BER testing Program
Figure B-5: BER tester screen shot
File Transfer Program
Figure B-6: File Transfer Program Screen Sh
Total Length of file received
Received data
ot
Start Program File Transfer mode Plot error reading in excel Reset Program Quit
Open Port for file transmission Close port Open file for input BER testing program Quit
Appendix B – Flowchart of Software Implementation
- 81 -
GUI for Sending Picture File
Select file for conversion
Select file for sending
Figure B-7: GUI for Transferring File
Choose a random character from keyboard
Choose COM port
Choose Program Mode
Figure B-8: GUI for Transmitter PC
Appendix B – Flowchart of Software Implementation
- 82 -
GUI for Help Menu
Figure B-9: Attenuation Help Menu
Figure B-10: Jitter Help Menu
Figure B-11: Transmitter/Receiver Help Menu
Appendix B – Flowchart of Software Implementation
- 83 -
Figure B-12: Eye Diagram Help Menu
Appendix C – Schematic
- 84 -
Appendix C – Schematic Drawing
Figure C-1: PCB of RZ-Transmitter
Figure C-2: Schematic of RZ-Transmitter
Appendix C – Schematic
- 85 -
Figure C-2: Schematic of Return-Zero module (Receiver)
Figure C-3: PCB of RZ-Receiver
Appendix C – Schematic
- 86 -
Figure C-4: Eye Diagrams for BER ratio
Figure C-5: Simulated VPI BER vs Received Power
From the figure above, we can see that for a receiver optical power output of -24dBM, we can achieved a 10-9 BER. This is the same case for the datasheet found for our receiver circuit HFBR24-12.