Copyright © 2001, A. Richard Newton
Page 1
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
The MARCO/DARPAThe MARCO/DARPAGigascale Silicon Research CenterGigascale Silicon Research CenterOverview and Progress ReportOverview and Progress Report
DARPA Kickoff WorkshopDARPA Kickoff WorkshopWashington, DCWashington, DC
December 6December 6thth, 2001, 2001
DUSD(S&T)Semiconductor
Industry Suppliers
The Productivity GapThe Productivity Gap
3 Yr. Design
* @ $ 150 k / Staff Yr. (In 1997 Dollars) Source: SEMATECHSource: SEMATECH
Year Technology Chip Complexity Frequency Staff Staff Cost*1997 250 nm 13 M Tr. 400 MHz 210 90 M
1998 250 nm 20 M Tr. 500 270 120 M
1999 180 nm 32 M Tr. 600 360 160 M
2002 130 nm 130 M Tr. 800 800 360 M
Copyright © 2001, A. Richard Newton
Page 2
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Implications of Implications of NotNot Doing the ResearchDoing the Researchuu If we do not solve these longIf we do not solve these long--leadlead--time problems:time problems:vvAccelerated slowdown in design productivityAccelerated slowdown in design productivity
vv Increasing unpredictability in design cycleIncreasing unpredictability in design cycle
vv Inability to verify/correct complex designsInability to verify/correct complex designs
vvMajor NRE cost increase for complex designs (likely anyway!)Major NRE cost increase for complex designs (likely anyway!)
uuWhich leads to:Which leads to:vvExpensive chipsExpensive chips——large markets economically inaccessiblelarge markets economically inaccessible
vv Inability to guarantee hitting market windowInability to guarantee hitting market window
vvQuality issues in the fieldQuality issues in the field
Overall industry slowdownOverall industry slowdown
““It’s a Moonshot, Not Rocket Science”It’s a Moonshot, Not Rocket Science”
Proposed GSRC 10Proposed GSRC 10--Year Goal, November 1997Year Goal, November 1997
50nm
10GHz
35nm
20GHz
Motivated by “Grand Challenge” ProblemsMotivated by “Grand Challenge” Problems
Copyright © 2001, A. Richard Newton
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The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
DARPA ISAT Study, 1997
Copyright © 2001, A. Richard Newton
Page 4
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
What Would “Success” Look Like?What Would “Success” Look Like?uuDesign implementation with Design implementation with predictable, microprocessorpredictable, microprocessor--quality quality
components on an ASIC schedulecomponents on an ASIC schedulevvEmphasis on Emphasis on efficient, predictable, costefficient, predictable, cost--effectiveeffective component component
implementation strategiesimplementation strategies
vvRole of Role of reuse and communicationreuse and communication--based assembly and verificationbased assembly and verificationapproachesapproaches
vvEmphasize Emphasize energy and power managementenergy and power management
uuBuilding Building highlyhighly--reliable systems from unreliable/unpredictable reliable systems from unreliable/unpredictable componentscomponents and technologiesand technologiesvvAccurate Accurate statistical characterization of processstatistical characterization of process and its circuitand its circuit--level level
implicationsimplications
vvNew circuit design stylesNew circuit design styles to accommodate the aboveto accommodate the abovevv Integration with Integration with test, diagnosis and selftest, diagnosis and self--repair, including analogrepair, including analog
GSRC 10GSRC 10--Year Goal, March 1999Year Goal, March 1999
Copyright © 2001, A. Richard Newton
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The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
What Would “Success” Look Like?What Would “Success” Look Like?uuEnable Enable programmable solutions through programming programmable solutions through programming
support for complex, programmable IC’ssupport for complex, programmable IC’s
vvA natural A natural programmer’s modelprogrammer’s model that allows for efficient utilization that allows for efficient utilization of the platform for a variety of applicationsof the platform for a variety of applications
vvEmphasis on Emphasis on exploiting and managing concurrencyexploiting and managing concurrency in the in the application and its implementationapplication and its implementation
uuDevelop a solution (methodology and technologies) for Develop a solution (methodology and technologies) for the the effective and reliable exploitation of concurrency in effective and reliable exploitation of concurrency in the designthe design and correct implementation of hardware and and correct implementation of hardware and softwaresoftware--based singlebased single--chip systems and their interfaceschip systems and their interfaces
GSRC 10GSRC 10--Year Goal, March 1999Year Goal, March 1999
www.gigascale.orgwww.gigascale.org : A Critical and Effective Resource: A Critical and Effective Resource
uuExample: August 2001Example: August 200156,541 accesses56,541 accessesvv400,841 hits400,841 hitsvvAverage visit 3 pagesAverage visit 3 pagesvvServed 755 MbytesServed 755 MbytesvvBroad range of users:Broad range of users:tt 29% from 29% from comcomtt 9.2% from 9.2% from eduedutt 1% from 1% from mil, mil, govgovtt 21% overseas: 63 countries21% overseas: 63 countries
u France, Canada, Finland, Netherlands, Germany, Hong Kong, Japan heaviest visitors
Copyright © 2001, A. Richard Newton
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The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
GSRC Website Statistics: July 1999 GSRC Website Statistics: July 1999 –– August 2001August 2001
0
20,000
40,000
60,000
80,000
100,000
120,000
140,000
21-Jul
-99
21-Se
p-99
21-Nov-
99
21-Jan
-00
21-Mar-0
0
21-May-
00
21-Jul
-00
21-Se
p-00
21-Nov-
00
21-Jan
-01
21-Mar-0
1
21-May-
01
21-Jul
-01
Hits
/Wee
k 90,000 hits/week
The Gigascale Silicon Research CenterThe Gigascale Silicon Research Centerhttp://www.gigascale.orghttp://www.gigascale.org
“Empowering designersto realize the potential of gigascale silicon by enablingscaleable, heterogeneous, component-based design
with a single-pass route to efficient
silicon implementation from a microarchitecture”
““Empowering designersEmpowering designersto to realize the potential of gigascale siliconrealize the potential of gigascale silicon by enablingby enablingscaleable, heterogeneous, componentscaleable, heterogeneous, component--based designbased design
with a with a singlesingle--pass route to efficient pass route to efficient
silicon implementation from a silicon implementation from a microarchitecturemicroarchitecture””
Copyright © 2001, A. Richard Newton
Page 7
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Overarching GSRC Research Emphasis Overarching GSRC Research Emphasis for 2001for 2001——…? :…? :
“From Ad“From Ad--Hoc SystemHoc System--onon--aa--Chip DesignChip Designto Disciplined, Platformto Disciplined, Platform--Based Design”Based Design”
The Gigascale Silicon Research CenterThe Gigascale Silicon Research Centerhttp://www.gigascale.orghttp://www.gigascale.org
“Empowering designersto move from ad-hoc system-on-a-chip design
to disciplined, platform-based design by enablingscaleable, heterogeneous, component-based design
with a single-pass route to efficient
silicon implementation from a microarchitecture”
““Empowering designersEmpowering designersto to move from admove from ad--hoc systemhoc system--onon--aa--chip designchip design
to disciplined, platformto disciplined, platform--based designbased design by enablingby enablingscaleable, heterogeneous, componentscaleable, heterogeneous, component--based designbased design
with a with a singlesingle--pass route to efficient pass route to efficient
silicon implementation from a silicon implementation from a microarchitecturemicroarchitecture””
Copyright © 2001, A. Richard Newton
Page 8
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
What is a Platform?What is a Platform?uu Broadly stated, a Platform is a Broadly stated, a Platform is a restriction on the space of possible restriction on the space of possible
implementation choicesimplementation choices, providing a , providing a wellwell--defined abstraction of the defined abstraction of the underlying technology for the application developerunderlying technology for the application developer
uu A Platform is a A Platform is a coordinated family of hardwarecoordinated family of hardware--software software architecturesarchitectures, that , that satisfy a set of architectural constraintssatisfy a set of architectural constraints, imposed , imposed to allow the reto allow the re--use of use of wellwell--characterized hardware and software characterized hardware and software components and technologiescomponents and technologies. .
uu New platforms will be New platforms will be defined at the architecturedefined at the architecture--microarchitecturemicroarchitectureboundaryboundary
uu They will be They will be heterogeneous and componentheterogeneous and component--basedbased, and will provide a , and will provide a range of choices from structuredrange of choices from structured--custom to fully programmable custom to fully programmable implementationsimplementations
““Only the consumer gets freedom of choice;Only the consumer gets freedom of choice;designers need freedom designers need freedom fromfrom choice”choice”
((OrfaliOrfali, et al, 1996, p.522), et al, 1996, p.522)
Contact: Alberto Sangiovanni
The ChipThe Chip--Level Implementation GapLevel Implementation Gap
ProcessProcessExportationExportation
DesignDesignImplementationImplementation
Fabrication
Physical DesignPhysical Design Blocks of Standard Cells, Datapath &
Memory
Application
Architecture
Mask-level layout
Well-characterized cell library
Microarchitecture
RTL Description
Gate-Level Schematic
S SV V SG
SG
SSV
V
SS SSVV VV SSGG
Copyright © 2001, A. Richard Newton
Page 9
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Application
Architecture
Mask-level layout
Well-characterized cell library
Fabrication
The ChipThe Chip--Level Implementation GapLevel Implementation Gap
Microarchitecture
RTL Description
Gate-Level Schematic
Physical DesignPhysical DesignS SV V SG
SG
SSV
V
SS SSVV VV SSGG
ImplementationGap
Silicon Implementation Platform
Tradeoffs and Reuse ModelTradeoffs and Reuse ModelSystem ApplicationSystem Application
Silicon ProcessSilicon Process
PlatformPlatformExportationExportation
StructuredStructuredCustomCustom
RTLRTLFlowFlow
FPGAFPGA FPGA &FPGA &GPPGPP
ASIPASIP DSPDSP GPPGPP
ApplicationApplicationImplementationImplementation
ProgrammabilityProgrammabilityLow High
Cost to Develop/Iterate New ApplicationCost to Develop/Iterate New ApplicationHigh Lower
MOPS/mWMOPS/mWHigh Low
IUnknownIUnknown
IOleObjectIOleObjectIDataObjectIDataObject
IPersistentStorageIPersistentStorageIOleDocumentIOleDocumentIUnknownIUnknown
IFooIFooIBarIBar
IPGoodIPGoodIOleBadIOleBad
IUnknownIUnknownIFooIFoo
IBarIBarIPGoodIPGoodIOleBad
IOleBad
IUnknown
IUnknown
IOleObject
IOleObjectIDataObject
IDataObject
IPersistentStorage
IPersistentStorageIOleDocument
IOleDocument
IUnknownIUnknown
IOleObjectIOleObjectIDataObjectIDataObject
IPersistentStorageIPersistentStorageIOleDocumentIOleDocument
IUnknownIUnknown
IOleObject
IOleObjectIDataObject
IDataObject
IPersistentStorage
IPersistentStorageIOleDocument
IOleDocument
IUnknownIUnknown
IFoo IFoo IBar IBarIPGoodIPGood
IOleBadIOleBad
ArchitectureArchitecture
MicroarchitectureMicroarchitecture
Copyright © 2001, A. Richard Newton
Page 10
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Disciplined, PlatformDisciplined, Platform--Based ApproachBased ApproachSystem ApplicationSystem Application
Silicon ProcessSilicon Process
PlatformPlatformExportationExportation
StructuredStructuredCustomCustom
RTLRTLFlowFlow
FPGAFPGA
FPGA &FPGA &GPPGPP
Config.Config.ProcessorProcessor
DSPDSP
GPPGPP
ApplicationApplicationImplementationImplementation
ConstructiveFabrics
Fully ProgrammableSystems
Current ScenarioCurrent Scenario––ASIPS on the Rise in NetworkingASIPS on the Rise in Networking
Company Product RISC based Task SpecificProcessor based
ASIC
Level One IXP1200 aIBM PNP aMMC nP aMaker MXT aSitera PRISM IQ1200 aEZChip NP-1 aC-Port C-5 DCP aAgere PayloadPlus aFast-chip PolicyEdge aHi-fn 7711, 7751 aXaqti TeraPower-CL aBroadcom StrataSwitch aSolidum PAX.port 1100 aNetlogic Policy, CIDR aSwitchcore CXE aEntridia Opera a
Source: GSRC MESCAL Group
Contact: Kurt Keutzer, Sharad Malik
Copyright © 2001, A. Richard Newton
Page 11
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Application(s)
Instruction Set Architecture360 SPARC 3000
“Physical Implementation”
…
…
General-PurposeComputing
Application(s)…
Verilog, VHDL, …
ASIC FPGA
SynthesizeableRTL
Platform-BasedDesign
Application(s)
…
Microarchitecture & Software
Physical Implementation
… …
…Platform
Contact: Kurt Keutzer, Sharad Malik
The Keys to A Productive Future:The Keys to A Productive Future:“The Three R’s”“The Three R’s”
Readin’, ‘Ritin’, and ‘Rithmetic
Reuse, Regularity, and Reprogrammability
Copyright © 2001, A. Richard Newton
Page 12
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Regularity & Physical DesignRegularity & Physical Designu New design regularity has been the enabler for every quantum step
in design automation and design productivityu But DSM physical synthesis can not take us all the way to
affordable gigascale w/o additional forms of regularity!
uu Beyond Beyond MOSFETsMOSFETs, , FINFETsFINFETs, ..., we expect that logic patterns and , ..., we expect that logic patterns and implementation platforms will become more even regularimplementation platforms will become more even regular——via via selfself--assemblyassembly
1978
1985
1992
1999
Transistor Entry
a
b
s
q0
1d
clk Schematic Entry
Synthesis
Desi
gn P
rodu
ctiv
ity Physical Synthesis
2001
Technology GenerationContact: Larry Pileggi
DSM ASIC Implementation and ManufacturingDSM ASIC Implementation and Manufacturing
uu Part of our research has been to Part of our research has been to understand, model and understand, model and create forms of regularitycreate forms of regularity to overcome DSM problems to overcome DSM problems that include:that include:vvPrinting and manufacturing high yield silicon with nanometer Printing and manufacturing high yield silicon with nanometer
feature sizesfeature sizesvvCreating reliable designs with component parameters that vary Creating reliable designs with component parameters that vary
substantiallysubstantiallyvvDistributing power reliably and guaranteeing signal integrityDistributing power reliably and guaranteeing signal integrityvvStructured communication channels and/or clocking Structured communication channels and/or clocking
methodologiesmethodologiesvvProviding Providing accurate prediction capabilitiesaccurate prediction capabilities for systemfor system--level level
exploration exploration from the Architectural Platform levelfrom the Architectural Platform levelvvFacilitating reliable design signoff for guaranteed firstFacilitating reliable design signoff for guaranteed first--pass pass
successsuccess
Contact: Larry Pileggi
Copyright © 2001, A. Richard Newton
Page 13
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
SIP Design SystemSIP Design SystemProduct PlanningProduct PlanningProduct Planning
Performance/Volume/Cost Performance/Volume/Cost SpecsSpecs
Choice of Technology & Choice of Technology & Integration (2D vs. 2.5D)Integration (2D vs. 2.5D)
Choice of Design Style Choice of Design Style and Platformand Platform
Product DesignProduct DesignProduct Design
Extract Logic Level Extract Logic Level Regularity From System Regularity From System
Level DescriptionLevel Description
Choose Configurable Choose Configurable Regular Logic Pattern Regular Logic Pattern
Implementation Style (e.g., Implementation Style (e.g., VPGA, RPLA) VPGA, RPLA)
Perform System AssemblyPerform System Assembly
ManufacturingManufacturingManufacturingMask GenerationMask Generation
Wafer FabWafer Fab
Technology & Performance Constraints
Technology & Performance Constraints
Performance Targets &
Constraints
Performance Targets &
Constraints
High Performance & High Yielding ProductHigh Performance & High Yielding ProductHigh Performance & High Yielding Product
RLP Generation for Soft IPRLP Generation for Soft IPRLP Generation for Soft IP
Customization of Hard IPCustomization of Hard IPCustomization of Hard IP
Synthesis of Custom Blocks (Analog/Mixed Signal, RF)
Synthesis of Custom Blocks Synthesis of Custom Blocks (Analog/Mixed Signal, RF)(Analog/Mixed Signal, RF)
“Design Kit” Creation““Design Kit” CreationDesign Kit” Creation
Hard IP SynthesisHard IP Synthesis
Soft IP Generator Soft IP Generator DevelopmentDevelopment
Verify System Performance Verify System Performance & Yield& Yield
Cell Library Cell Library Development for Development for
Custom IPCustom IP
Contact: Wojtek Maly
Applications
Microarchitectures
Architectural Platform
Silicon Fabric Options
Silicon Implementation Platform
Architecture PlatformImplementation Instance
Physical Processes
Silicon ImplementationPlatform Instance
Platform Design Methodologies: Platform Design Methodologies: Platform StacksPlatform Stacks
ApplicationImplementation Instance
Contact: Alberto Sangiovanni
Copyright © 2001, A. Richard Newton
Page 14
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
A Discipline of PlatformA Discipline of Platform--Based DesignBased Design
Silicon Implementation PlatformSilicon Implementation Platform
Architectural PlatformArchitectural Platform
Manfacturing InterfaceManfacturing Interface
Silicon ImplementationSilicon Implementation
Basic device & interconnectstructures
Delay, variation,SPICE models
Microarchitecture(s)Microarchitecture(s)
Circuit Fabric(s)Circuit Fabric(s)
Functional Blocks,InterconnectCycle-speed, power, area
S SV V SG
SG
SSV
V
SS SSVV VV SSGG
ApplicationApplication
Architecture(s)Architecture(s)
Kernels/BenchmarksProgramming Model:Models/Estimators
Articulation Point
Articulation Point
Contact: GSRC Team!
From Methodology to SiliconFrom Methodology to Silicon
Layer C-code (lines)
State-transition Diagram (states)
User Interface 130
Mulaw 100
Transport 510
MAC 270 42
Transmit 120 16
Receive 140 5
Synchronization 9 TOTAL 1270 72
Behavior Capture as CFSMs
In cooperation with DARPA PAC/C Project
Mapping and Communication Refinement
Silicon Backplane
PhysicalLayer
Protocol
SDRAMContr
CPUXtensa
FlashContr
Debug PortDebug PortR/F chipR/F chip
Cache
Sm0(snoop)
Flash PortFlash Port SDRAM PortSDRAM PortSnoop PortSnoop Port
Voice PortVoice Port
UI Contr
Buttons/Buttons/displaydisplay
Protocol Processor• 1.3 M transistors in
0.18 µm CMOS• 17.5 mm2 core size• 12 mW average power• 1.2 V supply (core)• 12.5 MHz fclock
DATADATASRAMSRAM
64Kbit64Kbit
INSTRUCTIONINSTRUCTIONSRAMSRAM
64Kbit64Kbit
NETWORK/NETWORK/MACMAC
XTENSAXTENSA SONICSSONICS
I/OI/O
BISTBIST
CA
CH
EC
AC
HE
Silicon ImplementationContact: Jan Rabaey
Copyright © 2001, A. Richard Newton
Page 15
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
GSRC Themes for 2001GSRC Themes for 2001
Communication/Component-Based Design
Fully-ProgrammableSystems
Fully-ProgrammableSystems
Calibrating Achievable DesignCalibrating Achievable Design
ConstructiveFabrics
ConstructiveFabrics
Architecture
Microarchitecture
Design ValidationDesign Validation
Design TestDesign Test
+ Power and Energy in Design
+ Power and Energy in Design
Validation of Highly Concurrent,Com
ponent-Based DesignsValidation of Highly Concurrent,
Component-Based Designs
Self-Test of Mixed-Signal System
sSelf-Test of M
ixed-Signal Systems
R. BryantR. BryantE. ClarkeE. ClarkeD. DillD. DillT. HenzingerT. HenzingerK. SakallahK. Sakallah+ T. Austin+ T. Austin+ T. Reps+ T. Reps+ D. Engler+ D. Engler
K. KeutzerK. KeutzerS. MalikS. MalikR. NewtonR. Newton+ D. August+ D. August
L. PileggiL. PileggiA. KahngA. KahngR. BraytonR. BraytonJ. CongJ. CongW. MalyW. MalyM. SadowskaM. SadowskaA. SangiovanniA. SangiovanniA. StrojwasA. Strojwas+ H. Schmit+ H. Schmit
T. ChengT. ChengS. DeyS. DeyW. MalyW. MalyK. RoyK. Roy+ J. Abraham+ J. Abraham A. KahngA. Kahng
W. DaiW. DaiW. MalyW. MalyL. PileggiL. PileggiA. StrojwasA. Strojwas+ T+ T--J. KingJ. King+ I. Markov+ I. Markov+ H. Schmit+ H. Schmit+ D. Sylvester+ D. Sylvester
J. RabaeyJ. RabaeyG. De MicheliG. De MicheliK. RoyK. Roy+ A. Chandrakasan + A. Chandrakasan + M+ M--J. IrwinJ. Irwin+ B. Nikolic+ B. Nikolic
A. SangiovanniA. SangiovanniT. HenzingerT. HenzingerE. LeeE. LeeR. NewtonR. NewtonJ. RabaeyJ. Rabaey+ R. R. MarculescuMarculescu
Verification: SelfVerification: Self--Checking MicroprocessorChecking Microprocessor
uuAdd checking and recovery logic to microprocessorAdd checking and recovery logic to microprocessorvvMakes sure each instruction gets correct operands and resultsMakes sure each instruction gets correct operands and resultsvvSimple hardware can operate at full processor speedSimple hardware can operate at full processor speedtt Don’t need result of one instruction before starting anotherDon’t need result of one instruction before starting another
vvCorrect results when neededCorrect results when neededtt Can be slowCan be slow
Checker
RegisterFile
Retire
Issue Execute
Correct
Idea due to Todd Austin, Michigan
Contact: Randy Bryant
Copyright © 2001, A. Richard Newton
Page 16
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Benefits of SelfBenefits of Self--CheckingChecking
uu ValidationValidationvv By verifying the checking/correction logic, we can guarantee corBy verifying the checking/correction logic, we can guarantee correct behavior rect behavior
by overall systemby overall systemvv Much smaller task than verifying entire systemMuch smaller task than verifying entire system
uu Embedded SoftwareEmbedded Softwarevv Is a critical part of the overall validation problem and Is a critical part of the overall validation problem and will play an increasingly will play an increasingly
important role in our researchimportant role in our research. We will most likely tackle it in the context of a . We will most likely tackle it in the context of a family of platforms.family of platforms.
uu ReliabilityReliabilityvv Reduced sensitivity to transient effects such as radiation eventReduced sensitivity to transient effects such as radiation eventss
Builds on verification capabilities developed by David Dill (Stanford), Randy Bryant (CMU), and KaremSakallah (Michigan).
Contact: Randy Bryant
Checker
RegisterFile
Retire
Issue Execute
Correct
Cost of Silicon Manufacturing and TestCost of Silicon Manufacturing and Test
0.00000010.0000001
0.0000010.000001
0.000010.00001
0.00010.0001
0.0010.001
0.010.01
0.10.111
19821982 19851985 19881988 19911991 19941994 19971997 20002000 20032003 20062006 20092009 20122012
cost: cost: ¢¢--perper--transistortransistor
Fabrication capital cost per transistor (Moore’s law)
Test capital cost per transistor (“Moore’s law for test”)
Based on ‘97 SIA Roadmap Data & ‘99 ITRS Roadmap
1999 Roadmap
Functionaltesting
(manual TG)
Functionaltesting
(manual TG)
Structural testing
(scan, ATPG)
Structural testing
(scan, ATPG)
Built-in self-test
(embedded HW tester)
Built-in self-test
(embedded HW tester)
Embedded SW-based self-test (embedded SW
tester)
Embedded SW-based self-test (embedded SW
tester)
Test paradigms:
Analog/Mixed-signal DfT/BISTAnalog/Mixed-signal DfT/BIST
New Test Paradigm: Embedded SWNew Test Paradigm: Embedded SW--Based SelfBased Self--Testing Testing & Mixed& Mixed--Signal BISTSignal BIST
Contact: Tim Cheng
Copyright © 2001, A. Richard Newton
Page 17
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
uu Embedded SoftwareEmbedded Software--Based Self Testing Based Self Testing vv Platforms and methods for systematic design of embedded Platforms and methods for systematic design of embedded
software (SW) selfsoftware (SW) self--testertestervv SystemSystem--level level DfTDfT techniques to support SWtechniques to support SW--based selfbased self--testtestvv Embedded SWEmbedded SW--based selfbased self--diagnosisdiagnosisvv Embedded SWEmbedded SW--based defect characterizationbased defect characterization
uu Analog/MixedAnalog/Mixed--Signal SelfSignal Self--Testing Testing vv DSPDSP--based selfbased self--testing of analog/mixedtesting of analog/mixed--signal components signal components vv SelfSelf--testing of hightesting of high--resolution (resolution (≥≥16 bits) converters 16 bits) converters vv OnOn--chip measurement for highchip measurement for high--speed serial communication linksspeed serial communication links
Research AgendaResearch Agenda––GSRC Test ThemeGSRC Test Theme
Contact: Tim Cheng
““Power and Energy in Design” Power and Energy in Design” –– VisionVision(Joint with Interconnect FCRP)(Joint with Interconnect FCRP)
We are developing We are developing platform architecturesplatform architectures that that combine static and dynamic techniquescombine static and dynamic techniques to to select the operational parameters (voltage, select the operational parameters (voltage, frequency, threshold), frequency, threshold), minimizing energy or minimizing energy or powerpower dissipation (dissipation (active and standbyactive and standby) while ) while
meeting performance constraintsmeeting performance constraints
Contact: Jan Rabaey
Copyright © 2001, A. Richard Newton
Page 18
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
Classification and Quantification of Power Classification and Quantification of Power Management Techniques as a Function of Activity Management Techniques as a Function of Activity
(Active + Standby)(Active + Standby)
CompileTime
RunTime
Logic Styles,Stacked Transistors,
Transistor SizingMultiple VddMultiple Vt
Dynamic Vdd (DVS)Dynamic Vt (DVTS)
White Paper under Development
Activity 100% 0% standby
Signal ConditioningSupply resistance
Power downDVS, DVTS
Example: Leakage management techniques
Contact: Jan Rabaey
““Living ITRSLiving ITRS--2001” in GTX2001” in GTXuuFirst time ever:First time ever: consistency checks, unified assumptions consistency checks, unified assumptions
for power, frequency, die size, density, performancefor power, frequency, die size, density, performance
uuCreates linkagesCreates linkages between Design, Assembly/Packaging, between Design, Assembly/Packaging, Defect Reduction, Process Integration / Devices / Defect Reduction, Process Integration / Devices / Structures, Test, Overall Roadmap Technology Structures, Test, Overall Roadmap Technology Characteristics, …Characteristics, …
uuModels and studies are linked with ITRSModels and studies are linked with ITRS--2001 distribution2001 distribution
uu Improves Improves flexibility, quality, transparency of flexibility, quality, transparency of roadmappingroadmappingvvAllows semiconductor industry to better allocate R&D Allows semiconductor industry to better allocate R&D
investment: “Who investment: “Who shouldshould solve a given red brick wall?”solve a given red brick wall?”
uu2002 goal: 2002 goal: Increase fraction of ITRS captured within GTXIncrease fraction of ITRS captured within GTX
Contact: Andrew Kahng
Copyright © 2001, A. Richard Newton
Page 19
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
““Living ITRS” Example Study: Maximum Chip Area Living ITRS” Example Study: Maximum Chip Area Containing HighContaining High--Performance Logic (PIDS Chapter), Subject Performance Logic (PIDS Chapter), Subject
to Power Limits (Assembly/Packaging Chapter)to Power Limits (Assembly/Packaging Chapter)
àà Quantified Power Management Gap (High
Quantified Power Management Gap (High --
Performance MPU) for Design Technology
Performance MPU) for Design Technology
Contact: Andrew Kahng
A Discipline of PlatformA Discipline of Platform--Based DesignBased Design
Silicon Implementation PlatformSilicon Implementation Platform
Architectural PlatformArchitectural Platform
Manfacturing InterfaceManfacturing Interface
Silicon ImplementationSilicon Implementation
Basic device & interconnectstructures
Delay, variation,SPICE models
Microarchitecture(s)Microarchitecture(s)
Circuit Fabric(s)Circuit Fabric(s)
Functional Blocks,InterconnectCycle-speed, power, area
S SV V SG
SG
SSV
V
SS SSVV VV SSGG
ApplicationApplication
Architecture(s)Architecture(s)
Kernels/BenchmarksProgramming Model:Models/Estimators
Contact: Alberto Sangiovanni
Copyright © 2001, A. Richard Newton
Page 20
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
GSRCDesign and Test
Relationship to Other FRCs and Future PlansRelationship to Other FRCs and Future Plans
InterconnectFRC
Materials, Structures, andDevices
Circuits, Systems, andSoftware
Power &Energy
CADFPS, Fabrics
& BWRC
J. RabaeyG. De MicheliK. Roy+ A. Chandrakasan + M-J. Irwin+ B. Nikolic
CAD TeamFabrics Team+ T-J. King+ I. Markov+ H. Schmit+ D. Sylvester
FPS TeamFabrics TeamCCD TeamTest Team+ J. Abraham+ D. August+ H. Schmit
Higher Levels ofDesign Abstraction
Validation TeamCCD TeamFPS Team+ T. Austin+ D. Engler+ R. Marculescu+ T. Reps
Contact: Alberto Sangiovanni
““It’s a Moonshot, Not Rocket Science”It’s a Moonshot, Not Rocket Science”
Proposed GSRC 10Proposed GSRC 10--Year Goal, November 1997Year Goal, November 1997
50nm
10GHz
35nm
20GHz
Motivated by “Grand Challenge” ProblemsMotivated by “Grand Challenge” Problems
Copyright © 2001, A. Richard Newton
Page 21
The MARCO/DARPA Gigascale SiliconResearch Center for Design & Test
A. Richard NewtonDARPA Kickoff Workshop
November 6th, 2001Washington, DC
““Not Just Research As Usual”Not Just Research As Usual”uu The GSRC is a The GSRC is a unique experiment in longunique experiment in long--range, collaborative range, collaborative
researchresearch, enabling broad collaboration across many areas of EDA , enabling broad collaboration across many areas of EDA and Designand Design
uu In the 1960In the 1960--1980’s 1980’s DARPA played a key role in creating and DARPA played a key role in creating and maintaining a collaborative communitymaintaining a collaborative community in design and architecturein design and architecturevv Xerox PARC & the Alto, Berkeley Unix, RISC, RAID, Integrated EDAXerox PARC & the Alto, Berkeley Unix, RISC, RAID, Integrated EDA
Systems…Systems…
uu GSRC is about GSRC is about rebuilding and maintaining such a community of rebuilding and maintaining such a community of researchersresearchers in many in many fields related to design productivityfields related to design productivityvv By By leveraging modern, distributed collaborative infrastructure leveraging modern, distributed collaborative infrastructure
vv By By enabling and supporting a series of research themesenabling and supporting a series of research themes
vv By By developing and maintaining a welldeveloping and maintaining a well--defined, but broad goaldefined, but broad goal——the Moon the Moon ShotShot——that serves to integrate all participantsthat serves to integrate all participants
Contact: GSRC Team!