The ESA The ESA MUSICMUSIC Project Project Multi-User & Interference Cancellation - ESA/ESTEC Contract 13095/98/NL/SB
Advanced Mobile Satellite Systems & Technologies presentation days
ESA./ESTEC – 14-15 November 2000
AMSST Presentation Days – 14-15 November 2000
The MUSIC Project: Mission
The MUSIC experiment
(Multi-USer Interference Cancellation receiver)
is a research project supported by the European Space Agency
which is aimed at the validation of an
Adaptive Interference Mitigating Detector
suited for use in a CDMA-based mobile satellite network
AMSST Presentation Days – 14-15 November 2000
The MUSIC experiment
(Multi-USer Interference Cancellation receiver)
is a research project supported by the European Space Agency
which is aimed at the validation of an
Adaptive Interference Mitigating Detector
suited for use in a CDMA-based mobile satellite network
The MUSIC Project: Mission
AMSST Presentation Days – 14-15 November 2000
MUSIC Breadboard Setup
Noise Generator
Oscilloscope
SpectrumAnalyzer
GPIB
NoiseComUFX 7107
HPE4411B
MUSICReceiver
Serial Port
STMProteo Board +
STM/CPR EC-BAID ASIC
AWG
PC Slot
National Instr.PCI 5411
AMSST Presentation Days – 14-15 November 2000
Presentation Outline
• Overall System Description Overall System Description andand Architectural Issues Architectural Issues(M. Luise, CPR)
• Design of DSP HW Design of DSP HW andand Analog TX/RX ends Analog TX/RX ends(G. Colleoni, STM)
• Breadboard HW partitioning Breadboard HW partitioning andand ASIC Design ASIC Design(L. Fanucci, CPR)(L. Fanucci, CPR)
AMSST Presentation Days – 14-15 November 2000
Technical Specs Tables: MUSIC TX 1/2
Random data generator stream PG on each CDMA channel with
disable capability
Maximum channel data rate 64 kb/s
Minimum channel data rate 2 kb/s
Signature sequences type WH + E-PN or
E-Gold
Signature sequence period L 32, 64 or 128
Modulation/Spreading techniques DS-SS Balanced QPSK with
real (single-code) spreading
Chip-to-symbol relation , n=1,...,16
Max. # of interfering channels L
Interferers delay wrt the useful
channel
0-L programmable on each channel
with 0.1 chip resolution
chips
Interferers phase shift wrt the useful
channel
0-360 programmable on each channel
with unit resolution
degrees
Interferers carrier frequency offset wrt
to the useful channel
±70 on each channel with 1 Hz
resolution
kHz
Max. single-carrier C/I ±10 on each channel with 0.5 dB
resolution
dB
Maximum/minimum chip-rate 2.048/0.128 programmable in
steps of a factor 2 with 1 Hz
accuracy
Mc/s
Chip shaping SRC with roll-off factor 0.22
IF carrier frequency 70 MHz
Max. carrier frequency uncertainty
(useful channel)
±100 Hz
Output signal level -10 to -30 in 5-dB steps dBm
Spurious and harmonics Š-40 dB
AWGN range -3 to +30 in 1-dB steps dB
Ts nL c
Eb / N0
AMSST Presentation Days – 14-15 November 2000
Technical Specs Tables: MUSIC TX 2/2
Random data generator stream PG on each CDMA channel with
disable capability
Maximum channel data rate 64 kb/s
Minimum channel data rate 2 kb/s
Signature sequences type WH + E-PN or
E-Gold
Signature sequence period L 32, 64 or 128
Modulation/Spreading techniques DS-SS Balanced QPSK with
real (single-code) spreading
Chip-to-symbol relation , n=1,...,16
Max. # of interfering channels L
Interferers delay wrt the useful
channel
0-L programmable on each channel
with 0.1 chip resolution
chips
Interferers phase shift wrt the useful
channel
0-360 programmable on each channel
with unit resolution
degrees
Interferers carrier frequency offset wrt
to the useful channel
±70 on each channel with 1 Hz
resolution
kHz
Max. single-carrier C/I ±10 on each channel with 0.5 dB
resolution
dB
Maximum/minimum chip-rate 2.048/0.128 programmable in
steps of a factor 2 with 1 Hz
accuracy
Mc/s
Chip shaping SRC with roll-off factor 0.22
IF carrier frequency 70 MHz
Max. carrier frequency uncertainty
(useful channel)
±100 Hz
Output signal level -10 to -30 in 5-dB steps dBm
Spurious and harmonics Š-40 dB
AWGN range -3 to +30 in 1-dB steps dB
Ts nL c
Eb / N0
As output from WP200
AMSST Presentation Days – 14-15 November 2000
Technical Specs Tables: MUSIC RX 1/2
IF carrier frequency 70 MHz
Max. carrier frequency uncertainty ±100 Hz
Input power level -10 to -40 dBm
Max.power unbalance between trafficchannels
±6 dB
Maximum channel data rate 64 kb/s
Minimum channel data rate 2 kb/s
Minimum AWGN -1 dB
Signature sequences type WH + E-PN or E-Gold
Signature sequence period L 32, 64 or 128
Modulation/Spreading techniques DS-SS Balanced QPSK withreal (single-code) spreading
Chip-to-symbol relation , n=1,...,16
Max. # of interfering channels L
Maximum/minimum chip-rate 2.048/0.128 programmable insteps of a factor 2 with 1 Hz
accuracy
Mc/s
Chip shaping SRC with roll-off factor 0.22
Adaptive Detector stepsize programmable / adaptive withsignal amplitude
MHz
for acquisition andtracking @ dB
-24 dB
Signal at and dB
< 4 sec
Signal with 0.99 probability at and dB
< 8 sec
MTLL for code/phase tracking atBER=8·10-2
> 3·104 sec
Overall SNR degradation on AWGNwrt to theory, with 10 -3ŠBERŠ8·10 -
2
Š0.5 dB
Overall SNR degradation wrt to FPsimulation with ideal sync/EC -BAID config. , 10 -3ŠBERŠ8·10 -2
Š1.0 dB
Baseband data output binary hard-detected NRZ and 4-bitsoft output with NRZ clock signal
Eb / N0
Ts nL c
[Ec / I0 ]mi
Es / N0 0
T ac [Ec / I0 ]mi
Es / N0 0
Tac
[Ec /( N0 I0 ) mi Es / N0 0
AMSST Presentation Days – 14-15 November 2000
Technical Specs Tables: MUSIC RX 2/2
As output from WP200
IF carrier frequency 70 MHz
Max. carrier frequency uncertainty ±100 Hz
Input power level -10 to -40 dBm
Max.power unbalance between trafficchannels
±6 dB
Maximum channel data rate 64 kb/s
Minimum channel data rate 2 kb/s
Minimum AWGN -1 dB
Signature sequences type WH + E-PN or E-Gold
Signature sequence period L 32, 64 or 128
Modulation/Spreading techniques DS-SS Balanced QPSK withreal (single-code) spreading
Chip-to-symbol relation , n=1,...,16
Max. # of interfering channels L
Maximum/minimum chip-rate 2.048/0.128 programmable insteps of a factor 2 with 1 Hz
accuracy
Mc/s
Chip shaping SRC with roll-off factor 0.22
Adaptive Detector stepsize programmable / adaptive withsignal amplitude
MHz
for acquisition andtracking @ dB
-24 dB
Signal at and dB
< 4 sec
Signal with 0.99 probability at and dB
< 8 sec
MTLL for code/phase tracking atBER=8·10-2
> 3·104 sec
Overall SNR degradation on AWGNwrt to theory, with 10 -3ŠBERŠ8·10 -
2
Š0.5 dB
Overall SNR degradation wrt to FPsimulation with ideal sync/EC -BAID config. , 10 -3ŠBERŠ8·10 -2
Š1.0 dB
Baseband data output binary hard-detected NRZ and 4-bitsoft output with NRZ clock signal
Eb / N0
Ts nL c
[Ec / I0 ]mi
Es / N0 0
T ac [Ec / I0 ]mi
Es / N0 0
Tac
[Ec /( N0 I0 ) mi Es / N0 0
<
<
AMSST Presentation Days – 14-15 November 2000
Noise Generator
Oscilloscope
SpectrumAnalyzer
GPIB
MUSICReceiver
Serial Port
AWG
DAQ Board
Breadboard Control and Monitoring via LabVIEW
AMSST Presentation Days – 14-15 November 2000
Breadboard Control and Monitoring via LabVIEW
Noise Generator
Oscilloscope
SpectrumAnalyzer
GPIB
MUSICReceiver
Serial Port
AWG
DAQ Board
AMSST Presentation Days – 14-15 November 2000
A Corner of the MUSIC Lab in Pisa
AMSST Presentation Days – 14-15 November 2000
The MUSIC TX: SW Setup …
AMSST Presentation Days – 14-15 November 2000
The MUSIC TX: SW Setup …
AMSST Presentation Days – 14-15 November 2000
… SW CDMA Signal Generation ...
AWG
PC Slot
AMSST Presentation Days – 14-15 November 2000
… AWG Loading and Run
AWG
PC Slot
AMSST Presentation Days – 14-15 November 2000
Sat Channel Emulation: Noise Generation
LabView Virtual Instrument
NOISECOM UFX 7107
MUSIC Testing Overall Set-up
AMSST Presentation Days – 14-15 November 2000
The MUSIC TX/RX: Analog IF front-end
More in the presentation to follow…More in the presentation to follow…by G. Colleoni, STMicroelectronicsby G. Colleoni, STMicroelectronics
AMSST Presentation Days – 14-15 November 2000
MUSIC RX:Direct IF sampling
f (MHz)70605040302010
4.464 20.848 37.232 53.616 70
BIF
11.920 28.304 44.688 61.072
16.38416.384
Digital downconversion to baseband
f (MHz)2010
4.464 11.920
-10-20
-11.920-4.464f (MHz)2010
8.928 16.384
-10-20
-7.456
f (MHz)2010
7.456
-10-20
-16.384-8.928 16.384
-16.384
f (MHz)2010-10-20
-16.384 16.384
7.456-BIF/2-7.456+BIF/2
BIF/2-BIF/2
Spectrum after A/D conversion
AMSST Presentation Days – 14-15 November 2000
FLEX10K100ACPLD
ST18952RAM FLASH
RAM
MAX7032
JTAGRESET
VCXO
DIG.INP. CON 24SIMM xRAM
78S05
78S05
LM317T
LM317T
+12 V +5 V
CON 40 CON 40
ICD2053BProg.CLK
AD5323DAC
CY7B991ROBOCLK
CON40
CON40
CON40
CON 40
CON40
CON40
OPA2681
OPA2681
ADS807ADC
TL7702 POR
LED
ADS807ADC
74LCX245BUFFERS
74LCX245BUFFERS
74LCX245BUFFERS
ICD2053BProg.CLK
FLEX10K100ACPLD
TO LOGICANALYZER
TO LOGICANALYZER
EXT. BOARD PROG.
CON 8
BIT BLASTER
CON 10
AGC1 VC
AGC2 VC
IF / I IN
Q IN
AD5323DAC
AFC VC
EXT. CLK
QS3238BUS SW
LEDLED LED LEDLED LED
EXT. CLK
AMP. & ADC
BUFFERING
MASTER CLK GEN.
LOGIC100K Gates CPLD
ANALOGAGC
POWER SUPPLY & P-ON RESET
LOGIC100K Gates CPLD
DSP + Glue Logic
MEMORY Extension (SRAM or DRAM)
The PROTEO Signal Processing Board
AMSST Presentation Days – 14-15 November 2000
The PROTEO Signal Processing Board
FLEX10K100ACPLD
ST18952RAM FLASH
RAM
MAX7032
JTAGRESET
VCXO
DIG.INP. CON 24SIMM xRAM
78S05
78S05
LM317T
LM317T
+12 V +5 V
CON 40 CON 40
ICD2053BProg.CLK
AD5323DAC
CY7B991ROBOCLK
CON40
CON40
CON40
CON 40
CON40
CON40
OPA2681
OPA2681
ADS807ADC
TL7702 POR
LED
ADS807ADC
74LCX245BUFFERS
74LCX245BUFFERS
74LCX245BUFFERS
ICD2053BProg.CLK
FLEX10K100ACPLD
TO LOGICANALYZER
TO LOGICANALYZER
EXT. BOARD PROG.
CON 8
BIT BLASTER
CON 10
AGC1 VC
AGC2 VC
IF / I IN
Q IN
AD5323DAC
AFC VC
EXT. CLK
QS3238BUS SW
LEDLED LED LEDLED LED
EXT. CLK
AMP. & ADC
BUFFERING
MASTER CLK GEN.
LOGIC100K Gates CPLD
ANALOGAGC
POWER SUPPLY & P-ON RESET
LOGIC100K Gates CPLD
DSP + Glue Logic
MEMORY Extension (SRAM or DRAM)
AMSST Presentation Days – 14-15 November 2000
ADCDCO
I
Q
N-stage Integrator
Decimation
In-Phase Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd fd=4R c
f
N-stage Integrator
Decimation
Quadrature Front-End
N-stage Comb
Compensation Filter / CMF
CIC
fs fs fd
fs
fs
2
n s=4
Interp.
n s=2
2R c
fd=4R c 2
n s=4
Interp.
n s
2R
I/Q Soft DataL
CCTU
CCAU
Prompt-I
Prompt-Q
E/L-I
E/L-Q
E/L
EC-BAID Unit
I/Q Correlator
FED
Pilot Channel Code
Traffic Channel Code
Demux-I
Demux-Q
Rc
Rc
Rs
Rs
SNIR Estimation
SNIRRs
Symbol Start
Signal Detect / Demod. Enable
AFC Loop Filter
Int. Clock 8Rc
IF Input
fIF=70 MHz
Rc
Rc
Rc
Code epoch
Sync AGC
Symb. Clock
BER Measurem.
P Interface
BER
fs
IFd=4.464 MHzf
MUSIC RX Architecture
More on HW partitioning to follow…More on HW partitioning to follow…by L. Fanucci, CPR-Teamby L. Fanucci, CPR-Team
More on HW partitioning to follow…More on HW partitioning to follow…by L. Fanucci, CPR-Teamby L. Fanucci, CPR-Team
AMSST Presentation Days – 14-15 November 2000
The Digital Multi-Rate Front-End 1/2
ADC
DDS
nADC
nDCO
CIC
nCIC
nDCO
nADC
In-Phase
Quadrature
CORDIC
CIC
nCICCORDIC
LUT
Phase Accumulator FCW T sfIFD
nFCW
Clock fs
k
cos
sin
npha
nacc
Downconverting to Downconverting to BasebandBaseband via a DCO via a DCO
fIFD BBBB
AMSST Presentation Days – 14-15 November 2000
The Digital Multi-Rate Front-End 2/2
… …
z-1z
-1z-1 z
-1z-M z
-M z-M z-M
From Digital Down-Conversion
Stage 1 Stage 2 Stage N
Decimation
Stage N+1Stage N+2 Stage 2N
To Compensation Filter and CMF
fs fd
Integrator Section Comb Section
- - - -
Cascaded Integrator-Comb (CIC) FilterCascaded Integrator-Comb (CIC) Filter
A low-complexity solution to perform low-pass filtering and decimation with no noise spectrum aliasing
AMSST Presentation Days – 14-15 November 2000
Ancillary Receiver Functions
MONITORING AND MEASUREMENT
• Signal-to-noise plus interference ratio
• Bit error rate
• Chip Timing & Carrier Loop Lock
SYNCHRONIZATION
Timing
• Spreading code acquisition
• Chip clock tracking
Carrier
• Carrier frequency tracking
• Carrier phase recovery
DETECTION
• Signal Interpolation
• Signal sense
AMSST Presentation Days – 14-15 November 2000
CCAU
MAX
Threshold
Signal Presence
Maximum
#1
#2
#2L
Threshold Calculation
><
Code Phase
1
W
1
W
1
W
S/P
2Rc
2Rc
Sync-Code Polynomial
…
| • |2
Code Phase
I
Q
I/Q Correlator
Index of Maximum
Code Timing Acquisition Unit (CTAU)
Correlation Time:L symbol intervals
AMSST Presentation Days – 14-15 November 2000
0.001
0.01
0.1
1
PW
A
1 10 100 1000
Post-Correlation Window Length, W (symbols)
Synchronous InterferersM=1
L=K=64C/I=-6 dB
P/C=+6 dB=1.1
Eb/N0=0 dB
Orthogonal Pilot Non Orthogonal Pilot
Performance of CTAU with Different Kind of Pilots
AMSST Presentation Days – 14-15 November 2000
x [( l m+1) T d + n T c/2] x [ l mT d + n T c/2 ]
1 - m
m
y (tm,n)
T d
Linear Interpolation Unit (LIU)
lm=integer delay, m=fractional delay
Td= Tc/4
AMSST Presentation Days – 14-15 November 2000
2
m
lm
k
Interp.On-Time
to EC-BAID, FED4R c
2R c
Rc
UpdateUnit
CED
I/Q samplesfrom
Front-End
AGC
from SACU
Early Late
Chip Clock Tracking Unit (CCTU)
AMSST Presentation Days – 14-15 November 2000
'kTc
Pilot Codec i
E
L
EL Samplesfrom Interpolator
|Z (-)|2
|Z (+)|2
.
. 2
2
k
AGC, k
from SACU
Chip-timing Error Detector (CED)
Non-coherent, non decision-aided processing – Lock detector not shown
AMSST Presentation Days – 14-15 November 2000
ˆ (k 1) ˆ (k) e(k)
e (k )m x(k)x(k 2)
LOOPFILTER
MRFEU+ LIU
N
Despread. LDCO NL
FDD SACU
e j (n )
ˆ (k)
e (k) x(k)
xREF
to EC-BAID
Pilot code
from ADC
NfsNfs fs
Nfs
Rs
RsRs
Rs
()
z 2
m()
x(k)
e(k)
Automatic Frequency Control Unit (AFCU)
Frequency Error Detector (FED)
AMSST Presentation Days – 14-15 November 2000
LOOPFILTER
LOOK-UPTABLE
PED
DEC
y(k) ˆ c kz(k)
e j ˆ ( k)
ˆ (k) e (k)
e (k) m ˆ c kz(k) ˆ (k 1) ˆ (k) (k)
(k) (k 1) (1 )e (k) e (k 1)
Carrier Phase Recovery Unit (CPRU)(embedded with EC-BAID)
Decision-Aided at EC-BAID output !
AMSST Presentation Days – 14-15 November 2000
The MUSIC core: The EC-BAID 1/2
REPLICA CODE
GENERATOR
LOCAL OSCILLATOR
CMFC-BAID
DETECTOR
PHASE & FREQUENCY
ERROR DETECTOR
Re{ }
IF INPUT SIGNAL
e-j t
1
g (t)R
1/Tc1/Ts
y(m)
c (m)1
b (r)1
1
1
e-j ( )
SIGNAL SAMPLES OUTPUT
EC-BAID: Extended Complex-valued Blind Adaptive Interference-mitigating Detector
is a baseband single-channel digital detector to counteract multiple-access interference
E
F. Giannetti. R. De Gaudenzi, M. Luise: "Design of a Low-Complexity Adaptive Interference-Rejection Detector for DS/SS Receivers in CDMA Radio Networks", IEEE Trans. Commun, vol. COM-46 n. 1, Jan 1998.
AMSST Presentation Days – 14-15 November 2000
The MUSIC core: The EC-BAID 2/2
y(r)
y(rL)
y(rL 1)
y(rL L 1)
CMF
g (t)R
1/Tc
y(m)
CMF outputs array
b1(r) 1
Lh1 (r)T y(r)
Symbol-RateDetector Output
The C-BAID is a linear The C-BAID is a linear adaptive detectoradaptive detector with complex-valued with complex-valued coefficients coefficients h h11(m) ,(m) , m=0,1,...,L-1m=0,1,...,L-1
x1 (r 1) x1(r) b1(r) y *(r ) y * (r)Tc1
Lc1
Recursive Adaptation RuleRecursive Adaptation Rule
h1 c1 x1x1
Tc1 0,Canonical DecompositionCanonical Decomposition
AMSST Presentation Days – 14-15 November 2000
Features of the EC-BAID
• BlindBlind : no need for training sequences to aid algorithm convergence, nor knowledge of interferers' parameters
• Robust to asynchronous MAIRobust to asynchronous MAI even for large interferer-to-useful channel power ratios
• Insensitive to the unknown phaseInsensitive to the unknown phase of the useful signal and compatible with conventional QPSK phase estimators
• Robust to residual carrier frequency errorsRobust to residual carrier frequency errors with respect toconventional DA-MMSE
• InsensitiveInsensitive to carrier frequency offsets on the interfering signals
• Suited to low-power ASICSuited to low-power ASIC implementation on a low-cost user terminal.
J. Romero-Garcia, F. Giannetti. R. De Gaudenzi, M. Luise: “A Frequency Error Resistant Blind CDMA Detector",IEEE Trans. Commun., July 2000
AMSST Presentation Days – 14-15 November 2000
Interference-Mitigation Capability of EC-BAID
Spreading FactorL=64
WH+E-PN Codes
1 User + 18 Interferers
6 dB STRONGER than the useful channel each.
(C/I)sc=-6 dB
AMSST Presentation Days – 14-15 November 2000
The EC-BAID ASIC with Embedded CPRU 1/2
PromptTo Data Detector
Chip Clock
Rs
Rc
Code Phase
EC-BAID Algorithm
Rc
Strobes
Traffic Code Polynomial
Signature Code Generator
Traffic Code
6
L
PED
Phase Rotator
e-j
Phase Loop Filter
e{ }Rs
Symbol Clock
Rs
ROM Sin/Cos
^
EC-BAID Unit
Phase-Rotated Strobes
Rc
AMSST Presentation Days – 14-15 November 2000
The EC-BAID ASIC with Embedded CPRU 2/2
0.25 m Technology
R. De Gaudenzi, E. Letta, L. Fanucci, F. Giannetti, M. Luise: "VLSI Implementation of a CDMA Blind Interference-Mitigating Detector", to appear on the IEEE Jou. Sel. Areas Commun
More on ASIC Design to follow…More on ASIC Design to follow…by L. Fanucci, CPR-Teamby L. Fanucci, CPR-Team
More on ASIC Design to follow…More on ASIC Design to follow…by L. Fanucci, CPR-Teamby L. Fanucci, CPR-Team
1
1
7
Clock_8Rc
Reset_N
Symbol_Start
Prompt_I
Prompt_Q
4BAID_Q
EC_BAID
1 4BAID_I
7
Rs
fs
fs
Rs
8Rc
1Symb_strobe
Rs
1CPRU_lock
L_se
l
Test
_En
3
Gam
ma_
BA
ID
21
Par
am
Rac
k
Req
Bac
t
1 1 1 1
STM & TEAM
EC-BAID
AMSST Presentation Days – 14-15 November 2000
Some Results: Bit-True Simulations 1/2
i ) W H + E - G O L D s e q u e n c e s
i i ) L = 6 4
i i i ) i d e a l c a r r i e r f r e q u e n c y / p h a s e r e c o v e r y
i v ) a s y n c h r o n o u s M A I w i t h e v e n l y - d i s t r i b u t e d d e l a y s o n o n e s y m b o l p e r i o d
v ) a d a p t a t i o n s t e p B A ID = 2 - 1 5
v i ) N = 3 2 a c t i v e u s e r s w i t h C / I = - 6 d B e a c h .
v i i ) C I C d e c i m a t i o n f a c t o = 8
i x ) C C T U s t e p s i z e a n d i n i t i a l t i m i n g e r r o r : C C T U = 2 - 7 , 0 T c / 4
0.001
2
3
4
567
0.01
2
3
4
567
0.1
2
3
4
567
1
BE
R
109876543210
Eb/N0 (dB)
WH+E-GOLDL=64N=32
C/I=-6 dBUnif. Asynchr. MAI
FE: =8.
CCTU: ACQ = SS = 2-7
0 = Tc / 4.
EC_BAID: = 2-15
WLEN = 2
trans / tx = 50 / 100 Ksymb.
FE + CCTU + EC_BAID ( BIT TRUE)
FE + CCTU + EC_BAID ( Floating Point )
• 7-bit LIU input/outputs with 5-bit representation of fractional delay .
• 9-bit representation of estimated delay
• 7-bit input/output SACU signals with 7-bit gain factor
AMSST Presentation Days – 14-15 November 2000
Some Results: Bit-True Simulations 2/2
0.001
2
3
4
567
0.01
2
3
4
567
0.1
2
3
4
567
1
BE
R
109876543210
Eb/N0 (dB)
WH+E-GOLDL=64N=32
C/I = -6 dB Unif. Asynch. MAI
EC-BAID: = 2-15
WLEN = 2
trans / tx = 50 / 100 Ksymb.
CPRU: = 45°
EC-BAID (floating point)
EC-BAID (bit true)
EC-BAID + CPRU (bit true)
i ) W H + E - G O L D s e q u e n c e s
i i ) L = 6 4
i i i ) i d e a l c a r r i e r f r e q u e n c y r e c o v e r y
i v ) a s y n c h r o n o u s M A I
v ) a d a p t a t i o n s t e p B A ID = 2 - 1 5
v i ) N = 3 2 a c t i v e u s e r s w i t h C / I = - 6 d B e a c h .
v i i ) C I C d e c i m a t i o n f a c t o = 8
i x ) C C T U s t e p s i z e a n d i n i t i a l t i m i n g e r r o r : C C T U = 2 - 7 , 0 T c / 4
AMSST Presentation Days – 14-15 November 2000
70—MHz IF CDMA Signal + Noise
Chip Rate= 2.048 Mchip/sL=64, Bit-rate=64 kb/s
Data+Pilot Channel
Chip Rate= 2.048 Mchip/sL=64, Bit-rate=64 kb/s
Data+Pilot Channel
AMSST Presentation Days – 14-15 November 2000
BB Filtered/Interpolated Digital CDMA Signal
AMSST Presentation Days – 14-15 November 2000
The Double-PROTEO Config with EC-BAID on FPGA
AMSST Presentation Days – 14-15 November 2000
Current Status and Further Development Steps
• EC-BAID FPGA Implementation finalized
• ASIC layout finalized
• Final Receiver BER Testing Started
• ASIC foundry run scheduled
• ASIC Integration and Testing planned
Soon to be ended...
AMSST Presentation Days – 14-15 November 2000
CIC Equalization
AMSST Presentation Days – 14-15 November 2000
Signal Decimation with the CIC Filter 1/2
H f sin M
f
fd
sin ffd
N
fd fs
=decimation factor
AMSST Presentation Days – 14-15 November 2000
G(f)
ffd 2fd fd=fs
fd/M
1
M=1
… fs/2
M=2
f '=0.455fs f "=0.545fs
Spectral Images from Down-Conversion
BBB=0.1525fd
Useful Signal
Spectrum
Spectral Images from Decimation
Signal Decimation with the CIC Filter 2/2
That’s How the CIC Works
AMSST Presentation Days – 14-15 November 2000
AWG Aperture Equalizer
Heq f 1
P f fs1
sinc f fs
| P(f) |
X(f) X(f)
f (MHz)fs = 16.384
X(f) X(f)
fIFD= 4.464 fmax= 5.71
Y(f)
f (MHz)fs = 16.384fIFD= 4.464 fmax= 5.71
1 f/fs 0.272 0.349
AMSST Presentation Days – 14-15 November 2000
SAWTEK 851549
fIFD
Local Oscillator
Mixer
AWG
To: Noise Generation& Combining
Signal+MAI
IF Filter
fLO
fIF
… more in the detailed presentation… more in the detailed presentation
TX/RX Filtering
AMSST Presentation Days – 14-15 November 2000
HW Partitioning of RX Functions
AMSST Presentation Days – 14-15 November 2000
Name IN/OUT From/To #bit Rate Description
Clock_4Rc In Master control/Clock Generator
1 4Rc
4Rc Clock(4Rc Enable Strobe+Master Clock)
Reset_N In Master control 1 Global Reset (active low)
Early_Late_I In Int_Demux 7 Rc Early/Late In-Phase signal
Early_Late_Q In Int_Demux 7 Rc Early/Late In-Quadrature signal
Rho_AGC In AGC 7 Rs AGC gain control
Pilot_Code In Code Generator 128 Pilot Code Sequence
L_sel In Master Control 2 Code Length Select
Signal_Detect In CTAU 1 Signal Detect Flag
Code_Epoch In CTAU 1 Acquired Code Epoch
Fract_Del Out Int_Demux 5 Rs Interpolator sampling time (fractional)
Int_Del Out Int_Demux 2 RsInterpolator sampling time (integer)
Symbol_Start Out EC_Baid 1 Start of Symbol Strobe
CCTU_Lock Out DSP/AGC 1 CCTU Lock Flag
Bit-True Design Sample (Hierarchical Diagram)
1
6
6
7
Clock_4Rc
Reset_N
Early_Late_I
Early_Late_Q
Rho_AGC
1 1
Signal_Detect Code_Epoch
128 2
Pilot_Code L_sel
5
1
Fract_Del
Symbol_StartC C T U
1 Rs4Rc
Rc
Rc
Rs
2Int_Del
Rs
1CCTU_Lock
CCTU HD
CCTU
AMSST Presentation Days – 14-15 November 2000
k from CCTU E k
| E k |CCTU Lock
1- T
LP - IIR.
CCTU Lock Detector
Low-pass Filtering
Nonlinearity Threshold with Hysteresis
AMSST Presentation Days – 14-15 November 2000
0.0001
0.001
0.01
0.1
1
BE
R
10008006004002000
Normalized Time (KSymbols)
timing error = 0 timing error = -0.05 Tc
L = 64, N = 32 C/I = -6 dB
unif. Asynchr. MAI Eb / N0 = 10. dB
BAID = 2-13
The EC-BAID Long-term BER Dirft
AMSST Presentation Days – 14-15 November 2000
Adaptive EC-BAID with Leakage
kBAIDkk exx 1
kBAIDkk exx 1
Standard EC-BAID
x k1 1 BAID xk BAIDek
Leakage factor
EC-BAID with Leakage
AMSST Presentation Days – 14-15 November 2000
0.001
2
3
4
567
0.01
2
3
4
567
0.1
BE
R
-20 -19 -18 -17 -16 -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0
Log2(Lfactor)
timing error = -0.05 T c
NO timing error Theory (NO timing error & NO leakage)
L = 64, N = 32, C/I = -6 dBunif. Asynch. MAI
BAID= 2-13
Leak = (1 - Lfactor BAID)tran / tx = 500 / 1000 KSymb.
Leak Factor Optimization
AMSST Presentation Days – 14-15 November 2000
Optimization of the EC-BAID: Window Length
10-5
10-4
10-3
10-2
10-1
100
BE
R
4.03.53.02.52.01.51.00.50.0
W
K=10Eb/N0=8dB
=6 10-4
=3 10-4
=1 10-4
=5 10-5
Optimum Length: 2 symbol intervals (0.5+1+0.5)
AMSST Presentation Days – 14-15 November 2000
EC-BAID Functional Block Diagram 1/2
AMSST Presentation Days – 14-15 November 2000
EC-BAID Functional Block Diagram 2/2