STAR-TOF DOE Review 125 Sept 2006 @BNL
STAR-TOF DOE Review
TDC Electronics
@BNL 25 September 2006
STAR-TOF DOE Review 225 Sept 2006 @BNL
Contents
1. Status summary
2. Development plan
3. Test / Production plan
STAR-TOF DOE Review 325 Sept 2006 @BNL
1. Status Summary
• Well-tested prototypes are being redesigned to optimize the system and to add a final data aggregation layer.
• Substantial non-technical delay places TDC board (TDIG) changes on critical path
• Run 7 installation and test will include the new production TDIG and TCPU designs, as well as all major system components and interfaces
• Test / Production planning and design have begun in parallel
STAR-TOF DOE Review 425 Sept 2006 @BNL
Run 5 TDC system timing performance
Start-timing resolution for 200 GeV (blue) and the 62 GeV (magenta) Cu+Cu data from Run-5 TDIG data from RHIC Run 5. Photomultiplier inputs to TDIG. (http://wjllope.rice.edu/~TOF/TOFr5/Run5data/)
STAR-TOF DOE Review 525 Sept 2006 @BNL
Run 5 TDC system functional performance
PID cuts for electrons (upper left) through protons (lower right) in 1/beta-space for the 200 GeV data.TDIG data from RHIC Run 5. (http://wjllope.rice.edu/~TOF/TOFr5/Run5data/)
STAR-TOF DOE Review 625 Sept 2006 @BNL
2. Development Plan
• TDIG changes
• TCPU changes
• System integration
• Tray-level cosmic testing at UT
• Tray-level installation at STAR for Run 7
STAR-TOF DOE Review 725 Sept 2006 @BNL
Major non-changes to TDIG / TCPU
• HPTDC operation:
– configuration
– control
– calibration
– data readout
• HPTDC performance metrics
• LVDS data transfer between boards
• STAR integration – Trigger and DAQ
• Microprocessor and programmable logic firmware
STAR-TOF DOE Review 825 Sept 2006 @BNL
TDIG change summary
• Remove discriminators
– Front end electronics perform discrimination
• Remove 1 of 4 HPTDC chips
– Front end electronics perform pulse stretching to allow rising and falling edge timing
measurements on the same channel
• Add multiplicity data transfer
• Attempt to reduce timing measurement crosstalk
– Topological randomization (common detector inputs spread across TDCs)
– Improved capacitive decoupling of HPTDC power supplies
• Improved microprocessor (8 bit to 16 bit – largely code compatible)
STAR-TOF DOE Review 925 Sept 2006 @BNL
All TDIG Changes• Removed 1 HPTDC chip• Rerouted (Reassigned) Event input channels to HPTDC channels• Redesigned Upstream and Downstream signals and connectors• Changed MCU from 8-bit PIC18F to 16-bit PIC24H microcontroller• Changed MCU clock from 20 MHz to 40 MHz• Changed MCU programming from assembly to C-language• Removed external CAN controller (now incorporated within PIC24H)• Added MCU-controlled CAN termination• Removed external RAM from MCU• Moved board-ID (tray-position switch) from FPGA to MCU• Added Silicon Serial Number (unique ID) to MCU I2C bus.• Added power-status monitoring and HPTDC power control• Added USB communication controller• Changed FPGA from Cyclone to Cyclone II• Added CPLD for control of FPGA configuration memories• Removed discriminator circuits (function now on TINO boards)• Removed (-) voltage input.• Added power input from TINO board.• Added test signal output to TINO board.• Added analog temperature input from TINO board• Removed 2 temperature monitors.
STAR-TOF DOE Review 1025 Sept 2006 @BNL
TDIG Block Diagram
TINO data connectors
(solder side)
TINO power connector
(solder side)
HPTDC
HPTDC
HPTDC
FPGA
MCU
CAN XCVR
DAC
TEST HEADER
Board Power
POSITION (Address) SWITCH
TEMPERATURE SENSOR
Threshold
8 bits
8 bits
8 bits
Signal Tap header
Config eprom 2
Config eprom 1
Byteblaster header
USB I/F
USB
CAN
small PLD
multiplicity
tray test pulse derived from local osc
2 x temperature voltage to MCU Power Ctl / Status
I2C from MCU
UPSTREAM data buffers
DOWNSTREAM data buffers
50 pin .1" connector 50 pin .1" connector
I2C Bus
Silicon Serial Number
DISPLAY
CONTROL / STATUS
REGISTERFPGA Configuration
Status
FPGA Configuration
Status
INTERRUPTS
Raw Power
STAR-TOF DOE Review 1125 Sept 2006 @BNL
System Clock distribution
FANOUT
ATTENUATION (3)
HPTDC (3)
DIFFERENTIAL LVPECL OVER RIBBON CABLE
oscillatorLVDS over 20 ft. CAT6 cable
Buffer
THUB
Data serializer
/deserializerfanout
TCPU
Data serializer
/deserializer
Silicon LabsPLL Fanout
Buffer Buffer Buffer
40 Mhz DIFFERENTIAL LVPECL OVER RIBBON CABLE
DIFFERENTIAL LVPECL OVER RIBBON CABLE
TO 2nd group of 4 TDIG boards
FANOUT
ATTENUATION (3)
HPTDC (3)
FANOUT
ATTENUATION (3)
HPTDC (3)
FANOUT
ATTENUATION (3)
HPTDC (3)
DIFFERENTIAL LVPECL OVER RIBBON CABLE
DIFFERENTIAL LVPECL OVER RIBBON CABLE
TDIG TDIG TDIG TDIG
STAR-TOF DOE Review 1225 Sept 2006 @BNL
Major changes to TCPU
• Remove trigger command input and programmable logic
for processing those commands (moved to THUB)
• Remove DDL fiber output to DAQ (moved to THUB)
• Simplify clock distribution circuitry
• Add LVDS output to THUB over CAT6 cable
• Add multiplicity output to STAR trigger
• Simplify data transfer between boards
STAR-TOF DOE Review 1325 Sept 2006 @BNL
TCPU Block Diagram
?
FPGA Altera Cyclone II
EP2C20
MCU PIC24F
CAN XCVR
TEST HEADER
Board Power
POSITION (Address) SWITCH
CAN #1
TEMPERATURE SENSOR
Signal Tap header
Config eprom 2
Config eprom 1
Byteblaster header
CAN
small PLD
Multiplicity (8 w/ no clock)
Power Ctl / Status
DOWNSTREAM #1 data buffers
DOWNSTREAM #2 data buffers
50 pin .1" connector 50 pin .1" connector
I2C Bus
Silicon Serial Number
DISPLAY (LEDs)
CONTROL / STATUS
REGISTERFPGA Configuration
Status
FPGA Configuration
Status
INTERRUPTS
To TRIGGER
CAN XCVR
CAN #2
CAN #2
CAN #2
To 4x TDIG To 4x TDIG
? CAT5 / CAT6
To THUB
Serial Interface
Power
STAR-TOF DOE Review 1425 Sept 2006 @BNL
Electronics Development Milestones
Delivery Schedule MilestoneTDIG
quantityTCPU
quantity Date
Complete initial TDIG testing and order balance of TDIG prototoype boards 14-Nov-06
1Complete delivery of TDIG prototype boards 20 10-Jan-06
Complete TCPU initial testing 10-Jan-06
2 Deliver TCPU prototype boards 5 30-Jan-06
Total TDIG / TCPU prototype boards 20 5
STAR-TOF DOE Review 1525 Sept 2006 @BNL
3. Test / Production Plan
• Production schedule
• Test requirements definition
• Automated Test system design
• TDIG test fixture design
• TCPU test fixture design
• Production infrastructure
STAR-TOF DOE Review 1625 Sept 2006 @BNL
Electronics Production Milestones
Delivery Schedule MilestoneTDIG
quantityTCPU
quantity DateBegin TDIG production 15-Dec-06
3 Deliver TDIG / TCPU pilot production 20 6 15-Mar-074 Deliver TDIG / TCPU pilot production 30 6 15-Apr-075 Deliver TDIG / TCPU pilot production 50 6 15-May-07
6 Deliver TDIG / TCPU production 60 7 14-Jun-077 Deliver TDIG / TCPU production 70 9 14-Jul-078 Deliver TDIG / TCPU production 80 9 13-Aug-079 Deliver TDIG / TCPU production 90 9 12-Sep-07
10 Deliver TDIG / TCPU production 90 9 12-Oct-0711 Deliver TDIG / TCPU production 90 9 11-Nov-0712 Deliver TDIG / TCPU production 90 12 11-Dec-0713 Deliver TDIG / TCPU production 90 12 10-Jan-0814 Deliver TDIG / TCPU production 90 12 9-Feb-0815 Deliver TDIG / TCPU production 90 12 10-Mar-0816 Deliver TDIG / TCPU production 76 12 9-Apr-08
Total TDIG 1016 130
STAR-TOF DOE Review 1725 Sept 2006 @BNL
TDIG / TCPU Production Readiness
• Parts purchasing and inventory system is in-place.
• Vendor / Supplier accounts are in-place.
• Multiple vendor/supplier sources for most items identified.
• Final Assembly and Testing Area available
• Test automation software identified.
• Test equipment identified and most is on-hand.
STAR-TOF DOE Review 1825 Sept 2006 @BNL
TDIG / TCPU Production Risks
• Tray level system test is critical to design validation
– Cosmic testing at UT– Run 7 installation
• HPTDC shipments from CERN
– Apparently in good shape
• Need to qualify multiple assembly vendors (and possibly board vendors)
• Working with parts distributors on volume purchase agreements with scheduled delivery to reduce lead-time risk
STAR-TOF DOE Review 1925 Sept 2006 @BNL
Production test summary
• Engineering prototypes will be subject to extensive engineering
evaluation and performance testing in-system
• Majority of board testing will take place at Blue Sky Electronics
• Testing will follow a documented board-level acceptance test
procedure
• Testing will be automated via fixture design and Labview software
environment
• Boards and test data will be delivered together, with test data
traceable to specific boards
STAR-TOF DOE Review 2025 Sept 2006 @BNL
Electronics Test Flow
Board Level
acceptance test
Tray level board test (17 boards + cables)
Tray assembly Tray test
Final Assembly and Visual Inspection
Rice TINO production
TDIG and TCPU board delivery
TDIG and TCPU board production by Blue Sky Electronics
Detector and Tray Production
Bare board test
PCB Supplier
Automated board stuffing
Automated board test (flying probe)
Board Assembly House
Burn-inInitial Test
Integration and Configuration by Rice Univ. et.al.
Production Parts Kit
Parts Supplier
STAR-TOF DOE Review 2125 Sept 2006 @BNL
TDIG Test System
TDIG Unit Under Test (UUT)
TDIG Test Fixture
Host Computer running LabView with
appropriate I/O adapter card(s)
Controlled Power Supply (UUT Power)
Result File
CAN Bus
Result Report (Traveler)
Commands / Responses / Status / Signals To/From Test Fixture
Event / Function Generator
“Events”
Voltage Set / Current Readback (GPIB / RS232 / etc)
“Event” generation settings (Rate, width, delay) (GPIB / RS232 / etc)
Power to UUT
“Upstream” Connector “Downstream” Connector
“TINO” Power / Status Connector
“TINO” Event Input Connectors
STAR-TOF DOE Review 2225 Sept 2006 @BNL
TDIG Block Diagram
TINO data connectors
(solder side)
TINO power connector
(solder side)
HPTDC
HPTDC
HPTDC
FPGA
MCU
CAN XCVR
DAC
TEST HEADER
Board Power
POSITION (Address) SWITCH
TEMPERATURE SENSOR
Threshold
8 bits
8 bits
8 bits
Signal Tap header
Config eprom 2
Config eprom 1
Byteblaster header
USB I/F
USB
CAN
small PLD
multiplicity
tray test pulse derived from local osc
2 x temperature voltage to MCU Power Ctl / Status
I2C from MCU
UPSTREAM data buffers
DOWNSTREAM data buffers
50 pin .1" connector 50 pin .1" connector
I2C Bus
Silicon Serial Number
DISPLAY
CONTROL / STATUS
REGISTERFPGA Configuration
Status
FPGA Configuration
Status
INTERRUPTS
Raw Power
STAR-TOF DOE Review 2325 Sept 2006 @BNL
TDIG Test Fixture Block Diagram
`
TINO data connectors
TINO power connector
“Threshold”
8 bits lvds
8 bits lvds
8 bits lvds
CAN Bus
Simulated multiplicity (3 bits)tray test pulse derived from TDIG osc
2 x simulated “temperature” voltage to MCU
UPSTREAM data buffers / level
translators
DOWNSTREAM data buffers / level
translators
50 pin .1" connector Upstream
50 pin .1" connector Downstream
A / D Conv.
D / A Conv. X 2
Digital Out
Power to UUT
Level conversion
Level conversion
Level conversion
Level conversion
Test Event
Selector
Digital Out
Test event contol& Host-generated
Test Event
Digital In
Digital Out
Digital In
Digital Out
From Downstream connector
To Downstream connector
From Upstream connector
To Upstream connector
40 MHz Oscillator
Digital Out
40_MHz Upstream Clock
External Event Generator
Power fromExternalSupply
Frequency counter
Host computer I/O Connections
Test Clock Out (J14 connector
Clock out
Freq. counter control
Simulated Multiplicity (3 bits lvds)
External Event Gen. control
External Supply control
Connections to TDIG Board UUT
STAR-TOF DOE Review 2425 Sept 2006 @BNL
TCPU Test System
TCPU Unit Under Test (UUT)
TCPU Test Fixture
Host Computer running LabView with
appropriate I/O adapter card(s)
Controlled Power Supply (UUT Power)
Result File
CAN Bus
Result Report (Traveler)
Commands / Responses / Status / Signals To/From Test Fixture
Voltage Set / Current Readback (GPIB / RS232 / etc)
Power to UUT
Upstream / Downstream #1
Upstream / Downstream #2
Pow
er
MultiplicitySerial“Cat6”
CAN Bus #2
STAR-TOF DOE Review 2525 Sept 2006 @BNL
TCPU Block Diagram
?
FPGA Altera Cyclone II
EP2C20
MCU PIC24F
CAN XCVR
TEST HEADER
Board Power
POSITION (Address) SWITCH
CAN #1
TEMPERATURE SENSOR
Signal Tap header
Config eprom 2
Config eprom 1
Byteblaster header
CAN
small PLD
Multiplicity (8 w/ no clock)
Power Ctl / Status
DOWNSTREAM #1 data buffers
DOWNSTREAM #2 data buffers
50 pin .1" connector 50 pin .1" connector
I2C Bus
Silicon Serial Number
DISPLAY (LEDs)
CONTROL / STATUS
REGISTERFPGA Configuration
Status
FPGA Configuration
Status
INTERRUPTS
To TRIGGER
CAN XCVR
CAN #2
CAN #2
CAN #2
To 4x TDIG To 4x TDIG
? CAT5 / CAT6
To THUB
Serial Interface
Power
STAR-TOF DOE Review 2625 Sept 2006 @BNL
TCPU Test Fixture
“Trigger” connector
Power Connector
CAN Bus
Simulated multiplicity
Upstream / Downstream #1
data buffers / level translators
Upstream / Downstream #2
data buffers / level translators
50 pin .1" connector Upstream /
Downstream #1
50 pin .1" connector Upstream /
Downstream #2
Digital In
Power to UUT
Level conversion
Digital Out / In
“THUB”-like data
Digital In
Digital Out
Digital In
Digital Out
From Up / Downstream #2
To Up / Downstream #2
From Upstream / Downstream #1 connector
To Upstream / Downstream #2 connector
40 MHz Oscillator
Digital Out40_MHz Upstream Clock
Power fromExternalSupply
Frequency counter
Host computer I/O Connections
Test Clock Out Clock out
Freq. counter control
Simulated Multiplicity (lvds)
External Supply control
SerDes
“THUB” connector
Connections to TCPU Board UUT
STAR-TOF DOE Review 2725 Sept 2006 @BNL
• Little or no post-test operations on boards
– No jumper changes or baseline firmware reconfiguration– Test what gets shipped; Ship what was tested.
• Traceability and firmware configuration management
– External and Internal serial number labeling for each board.– Automated test procedures generate archived files in addition to
board traveler delivered with board.– Test results available for review if subsequent problems occur.– FPGA / MCU / EPROM checksums or version IDs included in
test log.– Firmware changes subject to Engineering Change procedure.
Blue Sky Electronics – TDIG and TCPU Test Remarks
STAR-TOF DOE Review 2825 Sept 2006 @BNL
TDIG and TCPU Test (continued)
• Failure Analysis
– Failure symptom and resolution log kept for review and guidance.– Single failure treated as an anomaly.– Multiple observations of same/similar failure becomes cause for
concern.– Concern leads to engineering review of:
• Design and execution • Production practice / assembly shop performance• Part sources / handling• Part selection• Testing procedures
STAR-TOF DOE Review 2925 Sept 2006 @BNL
• Test sequences may be augmented to capture or evoke late failures or problems observed after delivery.
• Test procedures, sequences, and test equipment are documented.
• Production tests form the basis of regression test of Engineering Changes.
• Test procedure itself subject to Engineering Change procedure.
TDIG and TCPU Test (continued)
STAR-TOF DOE Review 3025 Sept 2006 @BNL
• Engineering Change Procedure
– Why – What is the problem or symptom– Who - is initiating it– What - will be changed (board rev, parts list, etc).
• Does it impact boards already shipped? • What happens to work-in progress?
– When - is it to happen (become effective).– Confirmation – that the change has happened (how to tell that a
particular unit has been changed).
• Documentation of Reworks and/or Engineering Changes applied to boards is kept as part of board history (traveler and test files).
• Procedure and equipment not ISO-type compliant
TDIG and TCPU Test (continued)
STAR-TOF DOE Review 3125 Sept 2006 @BNL
Tested Item Test or Operation Performed Reason for Test or Operation
1 Board Manufacture
1.1 BOM / KIT Validation of contents and count. Sufficient and correct parts available for build.
1.1.3 Programming Files Pre-programming of configuration and firmware prior to board bring-up test is desirable. This is preferably done by chip supplier or assembly shop.
Pre-programming saves time/effort/equipment in bringing up each board.
1.2.3 Electrical Test Bare-board electrical test at PCB shop because board is multiple-layer and fine-line.
Shorts / opens in bare PCB due to fabrication.
1.3.3 Flying Probe Test Flying probe testing by assembly shop against netlist and/or "golden" board.
Identify missing or mis-oriented components; dry or bridged solder joints.
TDIG Production Testing Matrix 1/9
STAR-TOF DOE Review 3225 Sept 2006 @BNL
2 Board Bring-up Test (Manual)
2.1 Visual check / Chip Install / Jumper Setting
Confirm proper inspection marks from prior tests
Boards failed tests 1.2.3 or 1.3.3 erroneously not removed from production cycle.
2.2 Power-up Check Ramp up Vin, watch Current in. Stop test if "out of bounds"
Current HI ==Short, reversed component, unprogrammed memory; LO==Missing component, unprogrammed memory
2.3 Verify Clocks Check for local-oscillator working Insures at least some base functionality
2.4 FPGA Check for FPGA configuration successful Insures FPGA configuration memory programmed and readable
2.5 MCU Self-Test Simple configuration and LED blink Insures MCU configuration/program memory programmed and configured
TDIG Production Testing Matrix 2/9
STAR-TOF DOE Review 3325 Sept 2006 @BNL
3 Board Acceptance Test (Automated)
3.1 Save external board serial number Assembly shop serial numbers and barcodes individual boards. This external S/N becomes part of traceability chain
Provides traceability back to assembler if problems are encountered. Provides correspondence between human-readable and electronic serial numbering.
3.2 Connect board to test fixture 3.1 Test System block diagrams (TDIG_Test_System.vsd)
3.3 Automated Test Procedure Test results saved, archived, and added to board traveler for delivery to customer.
3.3.1 Receive/Send Daisy-Chain Data Send simple asynchronous command thru upstream connector; receive reply through downstream connector
Validates MCU operational (hardware / software), clock operating. At least enough of board operating to communicate.
3.3.2 Receive/Send CAN Messages Send simple CAN message and get reply Validates CAN transceiver and communication path.
TDIG Production Testing Matrix 3/9
STAR-TOF DOE Review 3425 Sept 2006 @BNL
TDIG Production Testing Matrix 4/9
3.4 Verify I2C functions As follows: Validates I2C bus and attached components
3.4.1 Read S/N Rom (U60) CAN bus read serial number request. Confirms I2C bus and adds electronic serial number to traceability file.
3.4.2 Write LEDs (U34) CAN bus set LED patterns. Confirms I2C bus write capability. Validates LED connections
3.4.3 Check Temperature (U37) Confirms temperature monitor.
3.4.3.1 Read Temperature (U37) CAN bus read temperature request; confirm reasonable value
Confirms temperature monitor.
3.4.3.2 Set Temperature to cause interrupt (U37)
CAN bus set temperature limit request to cause temperature alarm interrupt.
Confirms temperature monitor and MCU interrupt capability.
STAR-TOF DOE Review 3525 Sept 2006 @BNL
TDIG Production Testing Matrix 5/9
3.4.4 Auxiliary I2C Port
3.4.4.1 Write/Read (U35) CAN bus request write to auxiliary I/O. Connect external to JU2 pins 2, 4, 6, 8. Verify external device can see level change.
Confirms extra I/O.
3.4.4.2 Write/Read (U35) CAN bus request read of Board ID switch.
Confirms ability to read switch.
3.4.5 Write Threshhold DAC (U38) CAN bus request write to DAC output. Loopback result from "TINO" connector for measurement by host.
Confirm DAC ability to set voltage(s) for TINO
3.4.6 Check PLD Status for reasonable (U36)
CAN Bus read (check) signals: PLD-CONFIG-DONE; PLD-INIT-DONE; PLD-nSTATUS; PLD-CRC-ERROR; SPARE-PLD
Confirms FPGA is configured and signals are available for reprogramming activity.
STAR-TOF DOE Review 3625 Sept 2006 @BNL
TDIG Production Testing Matrix 6/9
3.4.7 Check operation of TDC Power ENABLE and ERROR (U36)
This checks power-control truth table Confirms MCU is able to control TDC power and monitor (interrupt) on TDC-POWER-ERROR
3.5 Verify FPGA Initialization CAN bus request to trigger FPGA reconfigure
Confirm ability of MCU to trigger reconfiguration. Confirm correct operation of status signals (as in 3.4.6)
3.6 Verify FPGA EPROMS
3.6.1 Verify FPGA EPROM #1 Read CAN bus request to read EPROM #1 ID and/or Checksum
Confirm expected EPROM code present. Confirm functionality of CPLD
3.6.2 Verify FPGA EPROM #2 Read CAN bus request to read EPROM #2 ID and/or Checksum and/or check-for-blank
Confirm expected EPROM status. Confirm functionality of CPLD
3.6.3 Verify FPGA EPROM #2 Write CAN bus request to program EPROM #2 with duplicate code.
Confirm EPROM can be programmed. Confirm functionality of CPLD
STAR-TOF DOE Review 3725 Sept 2006 @BNL
TDIG Production Testing Matrix 7/9
3.7 Verify HPTDC Initialization CAN bus request to power-up and initialize HPTDC chips
Confirm HPTDC powers-up and can be
3.8 Check TINO_TEMP1 and TINO_TEMP2
CAN bus read request for TINO_TEMP1 and TINO_TEMP2 values driven in from external fixture (J13 pins 1 and 3)
Confirm MCU A/D conversion.
3.9 Check USB for reasonable status (U58)
MCU Enable USB Confirm expected status of USB serdes and FPGA logic.
3.10 Check remaining Upstream and Downstream connector Signals
Drive signals into downstream (e.g. multiplicity) from host computer, verify expected response on upstream side.
Confirms operation of downstream and upstream receivers and drivers and FPGA connections involved.
3.10.1 Check operation of Clock enable and Clock select (UCLK, DCLK, Local Clock, U25, U33, U24)
Enable and select various clock sources. Observe expected operation at TEST_CLK_OUT (J14)
Confirms operation of UCLK receiver, Local Clock Oscillator, and Clock Multiplexor and MCU ability to control clock operations.
STAR-TOF DOE Review 3825 Sept 2006 @BNL
TDIG Production Testing Matrix 8/9
3.11 Verify HPTDC measurements
3.11.1 HPTDC Loopback Data from FPGA
Command FPGA to issue "self-test" events. Observe expected result values.
Verify the ability of FPGA to generate events and each HPTDC chip to collect and measure events (i.e. proper initialization etc.)
3.11.2 HPTDC Acquire Data from External Source
Command TDIG to acquire external data with "known" delays and distributions. Observe expected result values. (One event-per-trigger)
Verify the ability of each HPTDC chip to collect and measure events. Also checks HPTDC-to-FPGA datapath and FPGA logic
3.11.3 HPTDC Picket-Fence from external source
Command TDIG to acquire external data with "known" delays and distributions. Observe expected result values. (Multiple events-per-trigger)
Verify the ability of each HPTDC chip to collect and measure events. Also checks HPTDC-to-FPGA datapath and FPGA logic
3.11.4 Cable-Delay Test Command TDIG to acquire external data with known (small) delays. Observe expected result values. Single-or-multiple events-per-trigger.
Verify the ability of each HPTDC chip to collect and measure events. Also checks HPTDC-to-FPGA datapath and FPGA logic
STAR-TOF DOE Review 3925 Sept 2006 @BNL
3.12 Tests with TINO Connected
3.12.1 Multiple-Channel Tests Command TDIG to acquire data from multiple channels simultaneously.
Verify system compatibility of TDIG with TINO. Evaluate crosstalk between channels.
3.11.5 Code Density Test (INL Curve) Command TDIG to acquire external data with random delays. Observe expected near-equality of histogram counts across measurement cells. There should be no "missing codes" whose event counts are near-0.
Verify the ability of each HPTDC chip to collect and measure events. Also checks HPTDC-to-FPGA datapath and FPGA logic
3.11.6 Multiple-Channel Tests Command TDIG to acquire data from multiple channels simultaneously.
Verify the ability of the HPTDC chips to measure events arriving on multiple channels and for the FPGA to process and transmit those measurements.
TDIG Production Testing Matrix 9/9
4 Board Burn-In
4.1 Burn-in Test / Exercise Connect multiple TDIG boards to TCPU and test fixture. Exercise features of board (except EEPROM writing) at normal and elevated operating temperature.
Verify system compatibility of TCPU, TDIG, and TINO. Evaluate crosstalk between channels. Evaluate system behavior.