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UVM Update
Register Package
Verification Engineer
Agnisys Technology Pvt. Ltd.
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Agenda
Introduction to UVM
UVM Register Model
Our experience with using Register Model Register Model Generator
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Verification Methodologies
History February 2011 Accellera releases UVM 1.0
Recently, June 2011 UVM 1.1 is released
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Introduction to UVM
Universal Verification Methodology
A methodology and a class library for building
Advanced Reusable Verification Components
Relies on strong, proven industry foundations
Engineers worldwide can write thorough and
reusable test environments
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UVM Environment
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Module top () as top level element.
Test Class
Contains Testbench
Reusable components
with different config
Source: Accellera DAC Presentation
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Whats in UVM ?
Base Classes
Factory Classes
Phasing
Configuration
TLM
Sequences & Sequencers
Message Reporting
Register Model
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Base Classes
Facilitate the design of modular, scalable, reusable verification
environments
The basic building blocks for all environments are components
and the transactions they use to communicate
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establish structal
hierarchy
phase--build,
connect, run, etc.
transactions
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Factory Classes
Manufacture (create) UVM objects andcomponents.
Only one instance of the factory is present in a
given simulation
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cl ass uvm_component _r egi st r y #(t ype T = uvm_component ,str i ng Tname = ""
) extends uvm_obj ect _wr apper
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Several new runtime phasesin parallel with run_phase()
By default, all components must allow all other
components to complete a phase before allcomponents move to next phase
Phasing
Source: Accellera DAC Presentation
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Configuration & TLM
Configuration The configuration & resource classes, access to store or receive from
database.
uvm_resource_db
uvm_config_db
Configuration mechanism advantages: Wild cards and regular expressions allow configuration of multiple attributes with a
single command
Run-time configuration support
TLM
Unidirectional put/get interfaces
TLM 2.0
Well-defined completion semantics
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put
Initiator
Initiator
target
target
get
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Sequencers & Sequences
Sequences
User-defined procedures that generate multiple
uvm_sequence_item-based transactions
Reused, extended, randomized, and combined
sequentially and hierarchically
Sequencers
Arbiter for controlling transaction flow
pullorpush semantic between Driver
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http://../Users/Sandy/Desktop/uvm-1.1/docs/html/files/seq/uvm_sequence_item-svh.htmlhttp://../Users/Sandy/Desktop/uvm-1.1/docs/html/files/seq/uvm_sequence_item-svh.html8/9/2019 Sandeep DVClub
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Messages print trace information with advantages
over $display:
Aware of its hierarchy/scope in testbench
Allows filtering based on hierarchy, verbosity, andtime
Message Reporting
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`uvm_i nf o( "PKT", "Packet Sent , UVM_LOW) ;
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Agenda
Introduction to UVM
UVM Register Model
Our experience with using Register Model Register Model Generator
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Register Model
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Object oriented Shadow Model for Registers
and Memories in DUT
Components
Field
Register
Register File
Memory
Block
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Register Model
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R0
F1 F2 F3 F4
F10 F11
F10 F11
.
.
.
F10 F11
F5 F6 F7
F8 F9
F5 F6 F7
F8 F9
.
.
F5 F6 F7
F8 F9
MEM_0
R0
R1
ARR[0]
ARR[1]
RF1 [0]
ARR[n]
RF0 [0]
RF0 [1]
RF1 [1]
RF0 [m]
RF1 [m]
MEM0
Registers
Register Arrays
Register File Array
Memory
R0
F1 F2 F3 F4
F10 F11
F10 F11
.
.
.
F10 F11
F5 F6 F7
F8 F9
F5 F6 F7
F8 F9
.
.
F5 F6 F7
F8 F9
MEM_0
R0
F1 F 2 F3 F4
F10 F11
F10 F11
.
.
.
F10 F11
F5 F6 F7
F8 F9
F5 F6 F7
F8 F9
.
.
F5 F6 F7
F8F9
MEM_0
BLOCK
BLK_1
.
.
. BLK_n
uvm_reg
uvm_mem
uvm_reg_file
uvm_reg_block
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Register Package Usage
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Adapter Backdoor
Read-Write
Bus Agent
Bus Specific
R/W
Generator
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Mirroring
Register model mirrors content of registers in DUT
Updated on read() and write()
Scoreboard for checking
Memories :
uvm_mem::peek()
uvm_mem::poke()
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R0
R1
APB
R0.read (. . .);
. . .
R1.write (. . .);
R0
R1
DUT
SequenceSequencer Driver
Monitor
Scoreboard
Monitor
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Front-door vs. Back-door Front Door: Normal bus access
Back Door
Access RTL directly in zero-time
Load memory
Hardware writable
Counter, status flags Must define hdl_path
Generator-specific
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R0
R1
APB
R0.read (. . .);
. . .
R1.write (. . .);
R0
R1
DUT
SequenceSequencer Driver
Monitor
Scoreboard
Monitor
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Agenda
Introduction to UVM
UVM Register Model
Our experience with using Register Model Register Model Generator
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And For Regi st er Arr ays:
f oreach ( reg_array[ i ] )begi n
r eg[ i ] . c l ear_hdl _pat h( ) ;r eg[ i ] . add_hdl _pat h_sl i ce( $sf or mat f ( DUT_ARRAY[ %0x] " , i ) , 0, 32) ;
end
HDL Path
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HDL pat h component s ar e speci f i ed usi ng the f ol l owi ng met hods:
a) uvm_r eg_bl ock: : conf i gur e( ) and uvm_r eg_bl ock: : add_hdl _pat h( )b) uvm_r eg_f i l e: : conf i gur e( ) and uvm_r eg_f i l e: : add_hdl _pat h( )c) uvm_r eg: : conf i gur e( ) and uvm_r eg: : add_hdl _pat h_sl i ce( )d) uvm_mem: : conf i gur e( ) and uvm_mem: : add_hdl _path_s l i ce( )
CODE:R0. cl ear _hdl _pat h( ) ;
R0. add_hdl _pat h_sl i ce( "dut . R0", 0, 32) ;R1. cl ear _hdl _pat h( ) ;
R1. add_hdl _pat h_sl i ce( "dut . R1", 0, 64) ;
Clear HDL paths if
mentioned above in
configure()
array name
R0
R1
APB
R0
R1
DUT
SequenceSequencer Driver
Monitor
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Mapping in Block
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Base Address
Byte addressing:
consecutive
addresses refer are
1 byte apart
APB_map = cr eate_map( "APB" , h0, 4, UVM_LI TTLE_ENDI AN, 1) ;APB_map_map. add_r eg ( R0, h0) ;APB_map. add_r eg ( R1, h4) ;
endianess
byte-width
of the bus
R0 - 32 bit
R1 - 64 bit
If (Byte addressing == 0) then
Bus width = Max size of Register
in Register Model
R0
R1
APB
R0
R1
DUT
SequenceSequencer Driver
APB_map = cr eat e_map( "APB" , h0, 8, UVM_LI TTLE_ENDI AN, 0) ;APB_map_map. add_r eg ( R0, h0) ;APB_map. add_r eg ( R1, h4) ;
Monitor
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Coverage
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For all elements except in Register File
Pre-defined Functional Coverage Type Identifiers UVM_NO_COVERAGE
UVM_CVR_FIELD_VALS
UVM_CVR_REG_BITS UVM_CVR_ADDR_MAP
UVM_CVR_ALL
Not instantiated by default Can be large. Instantiate only when needed.
To enable:
Coverage models for
bits read or written
in registers.
No coverage models.
Coverage models foraddresses read or written
in an address map.
Coverage models for
values of fields.
All coverage models.
R0
F1 F2 F3 F4
.
.
R1
7 6 5 4 3 2 1 0
.
F5 F6 F7
F8 F9
MEM_0
Block
R2
R3 0x015
0x000
0x008
0x014
0x020
- 0x030uvm_reg::include_coverage (*, (UVM_CVR_REG_BITS + . . ));
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class my_reg_R1 extends uvm_reg;
rand uvm_reg_field F1;
rand uvm_reg_field F2;
rand uvm_reg_field F3;
covergroup cg_vals;
F1: coverpoint F1.value[6:0];
F2: coverpoint F2.value[13:0];
F3: coverpoint F3.value[19:0];
endgroup
function new(string name = "my_reg_R1");
super.new(name, 32,build_coverage(
UVM_CVR_FIELD_VALS));. . .
endfunction
virtual function void sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
bit is_read,
uvm_reg_map map);
if (has_coverage(UVM_CVR_FIELD_VALS))
cg_vals.sample();
endfunction
virtual function void sample_values();
super.sample_values();
if (get_coverage(UVM_CVR_FIELD_VALS))
cg_vals.sample();
endfunction
. . .
endclass
class block_MEM0 extends uvm_mem;
local uvm_reg_addr_t m_offset;
covergroup cg_addr;QUADRANTS : coverpoint m_offset {
bins FIRST = {[0:2]};
bins SECOND = {[3:5]};
bins THIRD = {[6:8]};
bins FOURTH = {[9:11]};
}
endgroup
function new(string name = "block_mem_reg");
super.new(name, 'h30, 32, "RW",build_coverage(UVM_CVR_ADDR_MAP));
if (has_coverage(UVM_CVR_ADDR_MAP))
cg_addr = new();
endfunction
`uvm_object_utils(block_MEM0)
virtual function void sample(uvm_reg_addr_toffset, bit is_read, uvm_reg_map map);
if (get_coverage(UVM_CVR_ADDR_MAP))begin
m_offset = offset;
cg_addr.sample();
end
endfunction
endclass
class block_block extends uvm_reg_block;
block_MEM0 MEM0;
block_R1 R1;
local uvm_reg_addr_t m_offset;
covergroup cg_addr;
block_MEM0 : coverpoint m_offset {
bins hit = { ['h18 : 'h47] };
}
block_reg1 : coverpoint m_offset {
bins hit = { h4 };
}
endgroup
function new(string name = "block_block");
super.new(name,
build_coverage(UVM_CVR_ADDR_MAP));
if (has_coverage(UVM_CVR_ADDR_MAP))
cg_addr = new();
endfunction
virtual function void sample(uvm_reg_addr_t
offset, bit is_read, uvm_reg_map map);if (get_coverage(UVM_CVR_ADDR_MAP))begin
m_offset = offset;
cg_addr.sample();
end
endfunction
endclass : block_block
Register
Arrays
Register
File
Memory
Register
Coverage
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R0
F1 F2 F3
F10 F11
F10 F11
.
.
.
F10 F11
F5 F6 F7
F8 F9
F5 F6 F7
F8 F9
.
.F5 F6 F7
F8 F9
MEM_0
R0
R1
ARR[0]
ARR[1]
RF1 [0]
ARR[n]
RF0 [0]
RF0 [1]
RF1 [1]
RF0 [m]
RF1 [m]
MEM0
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Pre-Defined Sequences
SEQUENCES
uvm_reg_hw_reset_seq
uvm_reg_bit_bash_seq
uvm_reg_access_seq
uvm_mem_walk_seq
uvm_mem_access_sequvm_reg_mem_built_in_seq
uvm_reg_mem_hdl_paths_seq
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ATTRIBUTES
NO_REG_TESTS
NO_MEM_TESTS
NO_REG_HW_RESET_TEST
NO_REG_BIT_BASH_TEST
NO_REG_ACCESS_TESTNO_MEM_WALK_TEST
NO_MEM_ACCESS_TEST
Factory given Sequences hdl_path Access needed
uvm_resource_db#(bit)::set({"REG::", regmodel.blk.r0.get_full_name()},
"NO_REG_TESTS", 1, this);
Sequence
ignores thisRegister
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Special Registers
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Pre-Defined Registers Indirect Indexed Registers
class my_blk extends uvm_reg_block;
ind_idx_reg IND_IDX;
ind_data_reg IND_DATA;
ind_reg INDIRECT_REG[256];virtual function build();
. .
`ifdef INCA
begin
uvm_reg r[256];
foreach(INDIRECT_REG[i])
r[i]=INDIRECT_REG [i];
IND_DATA.configure(IND_IDX, r, this, null);end
`else
IND_DATA.configure(IND_IDX, INDIRECT_REG , this,
null);
`endif
. .
default_map = create_map(, 0, 4, UVM_BIG_ENDIAN);
default_map.add_reg(IND_IDX, 0);
default_map.add_reg(IND_DATA, 4);endclass
[0:7]
IND_DATA
INDIRECT_REG[0]
INDIRECT_REG[1]
INDIRECT_REG[2]
.
.
.
.
INDIRECT_REG[255]
INDIRECT_REG[256]
IND_IDX
Indirect Register Array
(External)
Not in the Register Map
my_blk0x00
0x04
data
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Special Registers
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Aliased Registers
Accessible from multiple addresses in the same address map.
Fields in aliased registers will have different behavior depending on
the address used to access them.
cont. .
R0
F1 F2 F3 F4
h100
F10 F11
F10 F11
h200
F10 F11
Ra
Rb
AliasedRegisters
class my_reg_Ra extends uvm_reg;
rand uvm_reg_field F1;
. . . .
F1.configure(this, 8, 0, "RW", . . .);
endfunction
endclass
class my_reg_Rb extends uvm_reg;uvm_reg_field F1;
. . . .
F1.configure(this, 8, 0, "RO", . . .);
endfunction
endclass
class my_blk extends uvm_reg_block;rand my_reg_Ra Ra;
rand my_reg_Rb Rb;
virtual function build();
. . . .
default_map.add_reg(Ra, h0100);
default_map.add_reg(Rb, h0200);
begin
alias_RaRb RaRb;RaRb =
alias_RaRb::type_id::create("RaRb",,get_full_name());
RaRb.configure(Ra, Rb);
end
endfunction
endclass
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Special Registers
FIFO
RO and WO Sharing the Same Address
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class fifo_reg extends uvm_reg_fifo;
function new(string name = "fifo_reg");
super.new(name,8,32,UVM_NO_COVERAGE);
endfunction: new
`uvm_object_utils(fifo_reg)
endclass
default_map.add_reg(R1, 'h100, "RO");
default_map.add_reg(W1, 'h100, "WO");
endfunction : build
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Agenda
Introduction to UVM
UVM Register Model
Our experience with using Register Model Register Model Generator
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Generation of Register Model
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GENERATOREDA
Vendors
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Why use a Generated Register Model
Create correct-by-construction models
Coverage types
Constraints
Backdoor access
Special register
Sync with specification
Ease of use
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Free UVM Register tools
Cadence : RGM
IP-XACT to UVM
Synopsys : Ralgen
RALF to UVM
Agnisys : IDSExcel
Excel to UVM
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Summary
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UVM register package must be used for any
serious SoC verification
Not using a register model is painful
Not using a generated register model is very
painful
Any questions?
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UVM: Factory Classes
Three basic operations for creating components:1. Registering objects and components types with the
factory
2. Designing components to use the factory to create
objects or components3. Configuring the factory with type and instance
overrides, both within and outside components
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cont. .
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Register Model Usage
Physical Interface
Read- Write
Checking
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APB
Register
Model
R0.read (. . .);
. . .
R1.write (. . .);
R0
R1
DUT
SequenceSequencer Driver
Monitor
Scoreboard
Monitor
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Introspection
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Special Registers
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Aliased Registers
cont. .
R0
F1 F2 F3 F4
h100
F10 F11
F10 F11
h200
F10 F11
Ra
Rb
AliasedRegisters
cl ass wr i t e_al so_t o_F ext ends uvm_r eg_cbs;l ocal uvm_r eg_f i el d m_t oF;
f unct i on new( uvm_r eg_f i el d t oF);m_t oF = t oF;
endf unct i onvi r t ual f uncti on voi d post _pr edi ct( uvm_r eg_f i el d f l d,
uvm_r eg_data_t val ue,uvm_predi ct_e ki nd,uvm_pat h_e pat h,uvm_reg_map map) ;
i f ( ki nd != UVM_PREDI CT_WRI TE) return;voi d' ( m_t oF. pr edi ct ( val ue, - 1, UVM_PREDI CT_WRI TE, path, map) ) ;
endf unct i onendcl ass cl ass al i as_RaRb ext ends uvm_obj ect ;
pr otected r eg_Ra m_Ra;pr otected r eg_Rb m_Rb;`uvm_obj ect _ut i l s( al i as_RaRb)f unct i on new( st r i ng name = "al i as_RaRb") ;
super . new( name) ;
endf unct i on: newf unct i on voi d conf i gur e( r eg_Ra Ra, r eg_Rb Rb) ;wr i t e_al so_t o_F F2F;m_Ra = Ra;m_Rb = Rb;F2F = new( Rb. F1) ;uvm_r eg_f i el d_cb: : add( Ra. F1, F2F) ;
endf uncti on : conf i gur eendcl ass : al i as_RaRb
cl ass my_bl k ext ends uvm_r eg_bl ock;r and my_r eg_Ra Ra;r and my_r eg_Rb Rb;
vi r t ual f unct i on bui l d( ) ;def aul t _map = cr eat e_map( " " , 0, 4, UVM_BI G_ENDI AN) ;
Ra = r eg_Ra: : t ype_ i d: : creat e( "Ra", , get _f ul l _name( ) ) ;. . .Rb = r eg_Rb: : t ype_ i d: : creat e( "Rb", , get _f ul l _name( ) ) ;. . .def aul t _map. add_r eg( Ra, h0100) ;def aul t _map. add_r eg( Rb, h0200) ;
begi nal i as_RaRb RaRb;
RaRb = al i as_RaRb: : t ype_i d: : creat e( "RaRb", , get _f ul l _name( ) ) ;RaRb. conf i gur e(Ra, Rb) ;
endendf unct i onendcl ass