Registersand Shift Registers
Discussion D8.2
D Flip-Flop
0 0 11 1 0X 0 Q0 ~Q0
D CLK Q ~Q
D gets latched to Q on the rising edge of the clock.
Positive edge triggered
CLK
D Q
~QCLK
D Q
~Q
A 1-Bit Register
CLK
D Q
~Q
CLK
Q0
~Q0
LOAD
INP0
Q0next = Q0 & ~LOAD | INP0 & LOAD
reg1Q0
~Q0
LOAD
INP0
CLK
A 1-Bit Register
If LOAD = 1, then INP0 gets latched to Q0 on the rising edge of the clock, CLK
reg1Q0
~Q0
LOAD
INP0
CLK
A 4-Bit Register
reg1Q0
~Q0
LOAD
INP0
reg1Q1
~Q1INP1
reg1Q2
~Q2INP2
reg1Q3
~Q3INP3
CLK
reg1Q0
~Q0
LOAD
INP0
CLK
Implementing Registers in Verilog
// A 4-bit register with asynchronous clear and loadmodule reg4(Clk,Clear,Load,D,Q);
input [3:0] D;input Clk,Clear,Load;output [3:0] Q;reg [3:0] Q;
always @(posedge Clk or posedge Clear)if(Clear == 1)
Q <= 0;else if(Load)
Q <= D;endmodule Reg
Clear
Clk
D(3:0)
Load
Q(3:0)
4-Bit Shift Register
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
data_in
CLK
Q0Q1Q2Q3
shift4.vmodule ShiftReg(clk,clr,data_in,Q); input clk; input clr; input data_in; output [3:0] Q;
reg [3:0] Q;
// 4-bit Shift Register always @(posedge clk or posedge clr)begin if(clr == 1)
Q <= 0; else
begin Q[3] <= data_in; Q[2:0] <= Q[3:1];end
endendmodule
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
data_in
CLK
Q0Q1Q2Q3
Note non-blocking assignment
shift4 simulation
Ring Counter
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q0Q1Q2Q3
ring4.vmodule ring4(clk,clr,Q); input clk; input clr; output [3:0] Q;
reg [3:0] Q;
// 4-bit Ring Counter always @(posedge clk or posedge clr)begin if(clr == 1)
Q <= 1; else
begin Q[3] <= Q[0]; Q[2:0] <= Q[3:1];end
endendmodule
ring4 simulation
Johnson Counter
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q3 Q2 Q1 Q0
module johnson4(clk,clr,Q); input clk; input clr; output [3:0] Q;
reg [3:0] Q;
// 4-bit Johnson Counter always @(posedge clk or posedge clr)begin if(clr == 1)
Q <= 0; else
begin Q[3] <= ~Q[0]; Q[2:0] <= Q[3:1];end
endendmodule
johnson4.v
Johnson Counter
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q3 Q2 Q1 Q0
A Random Number Generator
CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q CLK
D Q
!Q
CLK
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
0 0 0 1 11 0 0 0 81 1 0 0 C1 1 1 0 E1 1 1 1 F0 1 1 1 71 0 1 1 B0 1 0 1 5
Q3 Q2 Q1 Q0
1 0 1 0 A1 1 0 1 D0 1 1 0 60 0 1 1 31 0 0 1 90 1 0 0 40 0 1 0 20 0 0 1 1
module rand4(clk,clr,Q); input clk; input clr; output [3:0] Q;
reg [3:0] Q;
// 4-bit Random number generator always @(posedge clk or posedge clr)begin if(clr == 1)
Q <= 1; else
begin Q[3] <= Q[3] ^ Q[0]; Q[2:0] <= Q[3:1];end
endendmodule
rand4.v
A Random Number Generator
clk
inp
Q2
Q0
Q1
outp
Clock Pulse
module clk_pulse(clk,clr,inp,outp); input clk; input clr; input inp; output outp;
wire outp; reg [2:0] Q;
// clock pulse generator always @(posedge clk or posedge clr)begin if(clr == 1)
Q <= 0; else
begin Q[2] <= inp; Q[1:0] <= Q[2:1];end
endassign outp = Q[2] & Q[1] & ~Q[0];
endmodule
clk_pulse.v
clk
inpQ2
Q0Q1
outp